Array substrate for maintaining pixel electrode potential level and manufacturing method thereof

Abstract

The application relates to the technical field of display, and provides an array substrate for maintaining pixel electrode potential level, which comprises a glass substrate, a first metal layer plated on the upper surface of the glass substrate and forming spaced distribution gate, first CK signal wire and third CK signal wire, a gate insulation layer plated on the upper surface of the glass substrate and the first metal layer, a pixel electrode plated on the upper surface of the gate insulation layer, a first electrode block, a second electrode block, a third electrode block, an active layer plated on the upper surface of the gate insulation layer, a second metal layer plated on the upper surface of the gate insulation layer and forming spaced distribution source, drain and first signal connecting wire, and a conductive layer plated on the upper surface of the passivation layer. The application has the advantage that the potential level of the conductive layer is opposite to the potential level of the gate, the coupling effect of the gate to the drain and the coupling effect of the conductive layer to the drain are counteracted, and the Feedthrough voltage is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to an array substrate for maintaining pixel electrode potential level and a manufacturing method thereof. BACKGROUND

[0002] For TFT-LCD display, the side of TFT connected with pixel electrode is called drain, the capacitance formed between drain and gate metal is called parasitic capacitance C gd . The gate of TFT device is connected with horizontally distributed gate line, for controlling the opening and closing of TFT device; the source of TFT device is connected with vertically distributed data line, for writing data voltage which is wanted to be displayed into TFT device; when TFT is opened, the source and drain are conducted, data voltage enters into drain and then reaches liquid crystal capacitance Cst through pixel electrode, for adjusting the transmittance of liquid crystal; when TFT is closed, the source and drain are cut off, data voltage of source cannot enter into drain. Data voltage of source is periodically positive and negative, which is the positive and negative deflection voltage of liquid crystal.

[0003] In combination Figure 1 with Figure 2 , at the moment when TFT is closed, the gate voltage V g instantly drops from high level V high to low level V low . Due to the existence of parasitic capacitance C gd , the instantaneous change of V g will be coupled to drain, resulting in the drop of drain voltage, and because TFT device has been closed at this moment, the voltage difference between pixel electrode and drain will cause the voltage jump of pixel electrode, and this jump ΔV is called Feedthrough voltage. Figure 2 In the waveform diagram, V g is gate voltage, V d is ideal drain voltage, is actual common electrode voltage, i.e. the center point of actual positive and negative deflection voltage, V p (t) is actual pixel electrode voltage, V com is ideal common electrode voltage which makes liquid crystal keep the same voltage at both ends in positive and negative polarity state, V offset is the deviation of ideal common electrode voltage from actual common electrode voltage, Tf is the switching period of TFT device, V lc > V com is the region where pixel electrode voltage is greater than current ideal common electrode voltage, V lc < V com is the region where pixel electrode voltage is less than current ideal common electrode voltage.

[0004] As Figure 2 shown, due to the existence of Feedthrough voltage, the ideal common electrode V com point deviates from the center position of the actual provided positive and negative polarity deflection voltage, that is, the ideal common electrode voltage changes, but the actual provided positive and negative polarity deflection voltage remains unchanged, which results in that the liquid crystal has different deflection angles in the positive and negative polarity states, so that the light transmittance of the array substrate is different, causing flicker of the picture of the liquid crystal display. Therefore, reducing the Feedthrough voltage is a problem to be solved at present. SUMMARY

[0005] The technical problem to be solved by the present application is to provide an array substrate for maintaining the potential level of a pixel electrode and a manufacturing method thereof. By arranging a conductive layer above the drain electrode, the potential level of the conductive layer is opposite to the potential level of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are mutually offset, thereby reducing the Feedthrough voltage and maintaining the potential level of the pixel electrode.

[0006] The present application is implemented as follows:

[0007] An array substrate for maintaining the potential level of a pixel electrode, comprising:

[0008] a glass substrate;

[0009] a first metal layer plated on the upper surface of the glass substrate, forming spaced gate electrodes, first CK signal lines and third CK signal lines, the potential level of the first CK signal lines being opposite to the potential level of the third CK signal lines;

[0010] a gate insulating layer plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with first, second and third holes, the gate electrodes being exposed from the first holes, the first CK signal lines being exposed from the second holes, and the third CK signal lines being exposed from the third holes;

[0011] a pixel electrode plated on the upper surface of the gate insulating layer and located laterally to the gate electrodes;

[0012] a first electrode block plated in the first holes and connected to the gate electrodes;

[0013] a second electrode block plated in the second holes and connected to the first CK signal lines;

[0014] a third electrode block plated in the third holes and connected to the third CK signal lines;

[0015] The first electrode block, the second electrode block, the third electrode block and the pixel electrode are made of the same material;

[0016] The active layer is plated on the upper surface of the gate insulation layer and is located directly above the gate electrode;

[0017] The second metal layer is plated on the upper surface of the gate insulation layer and forms the source electrode, the drain electrode and the first signal connection line which are distributed at intervals. The source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, the drain electrode is also connected to the pixel electrode, the right end of the first signal connection line is connected to the first electrode block, and the left end of the first signal connection line is connected to the second electrode block.

[0018] The passivation layer is plated on the upper surface of the gate insulation layer, the active layer, the second metal layer and the pixel electrode. The passivation layer is provided with a fourth hole, and the third electrode block is exposed to the fourth hole.

[0019] The conductive layer is plated on the upper surface of the passivation layer and is located directly above the drain electrode. The upper surface of the passivation layer is also plated with a second signal connection line. The conductive layer is connected to the right end of the second signal connection line, and the left end of the second signal connection line is connected to the third electrode block through the fourth hole.

[0020] Further, it further comprises:

[0021] The second metal layer also forms the TP trace which is distributed at intervals.

[0022] The passivation layer is also provided with a fifth hole, and the TP trace is exposed to the fifth hole.

[0023] The common electrode is plated on the upper surface of the passivation layer. The lead wire of the common electrode is also connected to the TP trace through the fifth hole.

[0024] Further, the first metal layer and the second metal layer are both Ti / AL / Ti three-layer structure or MO / AL / MO three-layer structure.

[0025] Further, the gate insulation layer is SiOx single-layer structure or SiNx / SiOx double-layer structure. The passivation layer is made of SiO2. The outer insulation layer is made of SiOx, SiNO or SiNx.

[0026] Further, the active layer is made of IGZO. The conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all made of ITO.

[0027] Further, the first metal layer also forms a second CK signal trace and a fourth CK signal trace which are spaced apart, the second CK signal trace has opposite potential level to the fourth CK signal trace;

[0028] The first CK signal trace is connected with the gate of the array substrate of the first row, the second CK signal trace is connected with the gate of the array substrate of the second row, the third CK signal trace is connected with the conductive layer of the array substrate of the third row, and the fourth CK signal trace is connected with the conductive layer of the array substrate of the fourth row.

[0029] Further, the signal timing phase of the first CK signal trace is earlier than that of the second CK signal trace by a quarter of a period, and the signal timing phase of the third CK signal trace is earlier than that of the fourth CK signal trace by a quarter of a period.

[0030] A manufacturing method of an array substrate for maintaining pixel electrode potential level, comprising the following steps:

[0031] S1, plating a first metal layer on the upper surface of a glass substrate to form a gate, a first CK signal trace and a third CK signal trace which are spaced apart, the first CK signal trace has opposite potential level to the third CK signal trace;

[0032] S2, plating a gate insulating layer on the upper surface of the glass substrate and the first metal layer;

[0033] S3, opening a first hole, a second hole and a third hole in the gate insulating layer, the gate is exposed to the first hole, the first CK signal trace is exposed to the second hole, and the third CK signal trace is exposed to the third hole;

[0034] S4, plating a pixel electrode on the upper surface of the gate insulating layer, the pixel electrode is also located on the side of the gate;

[0035] Plating a first electrode block, a second electrode block and a third electrode block in the first hole, the second hole and the third hole respectively, the first electrode block is connected with the gate, the second electrode block is connected with the first CK signal trace, and the third electrode block is connected with the third CK signal trace;

[0036] The first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;

[0037] S5, plating an active layer on the upper surface of the gate insulating layer, the active layer is located directly above the gate;

[0038] S6, plating a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode and a first signal connection line distributed at intervals, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, the drain electrode also being connected to the pixel electrode, the right end of the first signal connection line being connected to the first electrode block, and the left end of the first signal connection line being connected to the second electrode block;

[0039] S7, plating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode;

[0040] A fourth hole is formed in the passivation layer, and the third electrode block is exposed from the fourth hole;

[0041] S8, plating a conductive layer and a second signal connection line on the upper surface of the passivation layer, the conductive layer also being located directly above the drain electrode, the right end of the conductive layer being connected to the second signal connection line, and the left end of the second signal connection line being connected to the third electrode block through the fourth hole.

[0042] Further, the method further comprises:

[0043] In the S6, the second metal layer also forms TP traces distributed at intervals;

[0044] In the S7, a fourth hole and a fifth hole are etched in the passivation layer at the same time, and the TP traces are exposed from the fifth hole;

[0045] In the S8, a conductive layer, a second signal connection line and a common electrode are plated on the upper surface of the passivation layer at the same time, and a lead of the common electrode is connected to the TP traces through the fifth hole.

[0046] Further, the conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all made of ITO material.

[0047] The advantages of the present application are as follows: 1. The conductive layer is arranged above the drain electrode, a supplementary capacitor is formed between the conductive layer and the drain electrode, the signal of the gate electrode is provided by the first CK signal line, the signal of the conductive layer is provided by the third CK signal line, the potential of the conductive layer is opposite to the potential of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are counteracted, the voltage difference between the pixel electrode and the drain electrode is reduced, the Feedthrough voltage is reduced, the potential level of the pixel electrode is maintained, and the picture flicker of the liquid crystal display is reduced; when the size of the supplementary capacitor is equal to the size of the parasitic capacitor, the Feedthrough voltage is eliminated, and the picture display stability of the liquid crystal display is improved. 2. Under the control of the first CK signal line, the second CK signal line, the third CK signal line and the fourth CK signal line, the first row of TFT devices and the second row of TFT devices of the liquid crystal display screen are opened and closed in sequence, the first row of pixels and the second row of pixels of the display screen are set to have brightness in sequence, and the liquid crystal display screen is stably displayed row by row. 3. The conductive layer is arranged at a position close to the contact between the drain electrode and the active layer, the field strength at the position is larger, the Schottky barrier formed by the contact between the semiconductor of the active layer and the metal wire of the drain electrode can be reduced, the contact resistance can be reduced, and the on-state current is increased. 4. ITO has good conductivity and light transmittance, the pixel electrode, the first electrode block, the second electrode block and the third electrode block of the present application are all made of ITO, so the pixel electrode, the first electrode block, the second electrode block and the third electrode block can be formed in the same process, the conductive layer and the common electrode of the array substrate of the present application are all made of ITO, so the conductive layer and the common electrode can be formed in the same process, which can simplify the substrate structure and improve the production capacity. 5. By pre-opening the first hole, the second hole and the third hole in the gate insulating layer, and then filling the first electrode block, the second electrode block and the third electrode block respectively, the influence of subsequent process etching on the metal of the first metal layer is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0048] The present application will be further described below with reference to the embodiments and the accompanying drawings.

[0049] Figure 1 is a schematic diagram of the parasitic capacitor between the gate electrode and the drain electrode of the TFT device in the background technology.

[0050] Figure 2 is a schematic diagram of the deviation of the potential level of the common electrode V com from the ideal state due to the existence of the Feedthrough voltage in the background technology.

[0051] Figure 3 is a design diagram of the array substrate for maintaining the potential level of the pixel electrode of the present application.

[0052] Figure 4 is Figure 3FIG. 1 is a circuit diagram of the first row of TFT devices on the array substrate.

[0053] Figure 5 yes Figure 3 FIG. 1 is a circuit diagram of the second row of TFT devices on the array substrate.

[0054] Figure 6 This is a timing diagram of the first CK signal routing, the second CK signal routing, the third CK signal routing, and the fourth CK signal routing in the present invention.

[0055] Figure 7 It is a top view schematic diagram of the array substrate for maintaining the pixel electrode potential level of the present invention.

[0056] Figure 8 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 1 .

[0057] Figure 9 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 2 .

[0058] Figure 10 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 3 .

[0059] Figure 11 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 4 .

[0060] Figure 12 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 5 .

[0061] Figure 13 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 6 .

[0062] Figure 14 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 7 .

[0063] Figure 15 The present invention is a process for manufacturing an array substrate for maintaining pixel electrode potential level. Figure 8 .

[0064] Reference numerals:

[0065] Glass substrate 1; pixel display area 11;

[0066] Gate 2;

[0067] First CK signal wire 31; second CK signal wire 32; third CK signal wire 33; fourth CK signal wire 34;

[0068] Gate insulating layer 4; first dug hole 41; second dug hole 42; third dug hole 43;

[0069] Pixel electrode 5; first electrode block 51; second electrode block 52; third electrode block 53;

[0070] Active layer 6;

[0071] Source 7;

[0072] Drain 8;

[0073] First signal connecting line 91; right end 911 of the first signal connecting line; left end 912 of the first signal connecting line; second signal connecting line 92;

[0074] Passivation layer 10; fourth dug hole 101; fifth dug hole 102;

[0075] Conductive layer 20;

[0076] TP wire 30;

[0077] Common electrode 40. DETAILED DESCRIPTION

[0078] The array substrate for maintaining the potential level of the pixel electrode and the manufacturing method thereof provided by the embodiment of the present application solve the defect that the flicker of the liquid crystal display picture caused by the existence of the Feedthrough voltage in the background art, and achieve the technical effects of reducing the Feedthrough voltage, maintaining the potential level of the pixel electrode and stabilizing the liquid crystal display picture.

[0079] The technical solution in the embodiment of the present application is as follows to solve the above-mentioned defects:

[0080] The main improvement of the present application is that the conductive layer is plated above the drain after the passivation layer is plated, and the conductive layer and the drain form a complementary capacitor C 补充 The potential level of the conductive layer is just opposite to the potential level of the gate of the TFT array substrate at any time, and there is a parasitic capacitor C gd between the drain and the gate. In this way, the coupling effect of the gate on the drain and the coupling effect of the conductive layer on the drain are offset to each other, so that the voltage difference generated between the pixel electrode and the drain is reduced, the voltage jump of the pixel electrode is reduced, and the Feedthrough voltage is reduced. The signal of the gate is provided by the first CK signal wire, the signal of the conductive layer is provided by the third CK signal wire, and when the complementary capacitor C 补充 is equal to the parasitic capacitor C gdWhen the size of the feedthrough voltage caused by the signal change of the gate is consistent with the size of the parasitic capacitance C 补充 , the feedthrough voltage caused by the signal change of the gate can be eliminated. gd The size of the parasitic capacitance C

[0081] The first hole, the second hole and the third hole are pre-formed in the gate insulating layer, and then the first electrode block, the second electrode block and the third electrode block are filled respectively, so that the influence of subsequent process etching on the metal of the first metal layer is avoided. The signal of the first CK signal line passes through the second electrode block, the first signal connection line and the first electrode block to the gate in sequence, and the signal of the third CK signal line passes through the third electrode block and the second signal connection line to the conductive layer.

[0082] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings of the specification and specific embodiments.

[0083] Referring to Figures 1 to 15 , the preferred embodiments of the present application.

[0084] An array substrate for maintaining the potential level of a pixel electrode, comprising:

[0085] A glass substrate 1;

[0086] A first metal layer is plated on the upper surface of the glass substrate 1, forming a gate 2, a first CK signal line 31 and a third CK signal line 33 which are spaced apart. The potential of the first CK signal line 31 is opposite to that of the third CK signal line 33.

[0087] A gate insulating layer 4 is plated on the upper surface of the glass substrate 1 and the first metal layer. The gate insulating layer 4 is provided with a first hole 41, a second hole 42 and a third hole 43. The gate 2 is exposed to the first hole 41, the first CK signal line 31 is exposed to the second hole 42, and the third CK signal line 33 is exposed to the third hole 43.

[0088] A pixel electrode 5 is plated on the upper surface of the gate insulating layer 4 and is located beside the gate 2.

[0089] A first electrode block 51 is plated in the first hole 41 and is connected to the gate 2.

[0090] A second electrode block 52 is plated in the second hole 42 and is connected to the first CK signal line 31.

[0091] A third electrode block 53 is plated in the third hole 43 and is connected to the third CK signal line 33.

[0092] The first electrode block 51, the second electrode block 52, the third electrode block 53 and the pixel electrode 5 are made of the same material;

[0093] The active layer 6 is plated on the upper surface of the gate insulation layer and directly above the gate 2;

[0094] The second metal layer is plated on the upper surface of the gate insulation layer 4, forming the source 7, the drain 8 and the first signal connection line 91 which are distributed at intervals, the source 7 is connected with the left end of the active layer 6, the drain 8 is connected with the right end of the active layer 6, the drain 8 is also connected with the pixel electrode 5, the right end 911 of the first signal connection line is connected with the first electrode block 51, and the left end 912 of the first signal connection line is connected with the second electrode block 52;

[0095] The passivation layer 10 is plated on the upper surface of the gate insulation layer 4, the active layer 6, the second metal layer and the pixel electrode 5, the passivation layer 10 is provided with the fourth hole 101, and the third electrode block 53 is exposed from the fourth hole 101;

[0096] The conductive layer 20 is plated on the upper surface of the passivation layer 10 and directly above the drain 8, and the upper surface of the passivation layer is also plated with the second signal connection line 92, the conductive layer 20 is connected with the right end of the second signal connection line 92, and the left end of the second signal connection line 92 is connected with the third electrode block 53 through the fourth hole 101.

[0097] In the present application, the conductive layer 20 is arranged above the drain 8, a complementary capacitor is formed between the conductive layer 20 and the drain 8, the signal of the gate 2 is provided by the first CK signal line 31, the signal of the conductive layer 20 is provided by the third CK signal line 33, the potential of the conductive layer 20 is opposite to that of the gate 2, the coupling effect of the gate 2 on the drain 8 and the coupling effect of the conductive layer 20 on the drain 8 are offset to each other, the voltage difference between the pixel electrode 5 and the drain 8 is reduced, the Feedthrough voltage is reduced, and the picture flicker of the liquid crystal display is reduced; when the size of the complementary capacitor is equal to that of the parasitic capacitor, the Feedthrough voltage is eliminated, the potential level of the pixel electrode 5 is maintained, and the picture display stability of the liquid crystal display is improved; the V com The potential of the common electrode 40 in the ideal state deviates from the center position of the positive and negative polarity deflection voltage actually provided; the liquid crystal maintains the same voltage value at both ends in the positive and negative polarity states, and the deflection angle of the liquid crystal in the positive and negative polarity states is the same, so that the light transmittance of the array substrate is the same, and the picture of the liquid crystal display is stable.

[0098] The conductive layer 20 is arranged at a position close to the contact between the drain 8 and the active layer 6, where the field intensity is larger, so that the Schottky barrier formed by the contact between the semiconductor of the active layer 6 and the metal wire of the drain 8 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.

[0099] The first, second and third holes 41, 42 and 43 are formed in the gate insulation layer 4 in advance, and then the first, second and third electrode blocks 51, 52 and 53 are filled in the holes respectively, so that the subsequent etching process does not affect the metal of the first metal layer. The first, second and third electrode blocks 51, 52 and 53 are made of the same material as the pixel electrode 5, so that the pixel electrode 5, the first, second and third electrode blocks 51, 52 and 53 can be formed in the same process, which simplifies the substrate structure, improves the production capacity, and reduces the cost. When the fourth hole 101 is etched in the passivation layer 10, the etching is stopped when the third electrode block 53 is exposed in the fourth hole 101, so that the third CK signal line 33 is not etched, and the outermost metal of the third CK signal line 33 in the first metal layer is not damaged. The conductive layer 20 is connected with the third electrode block 53 through the fourth hole 101, and the conductive layer 20 and the third electrode block 53 are both made of ITO.

[0100] The second metal layer also forms the TP lines 30 which are distributed at intervals.

[0101] The passivation layer 10 also has a fifth hole 102, and the TP lines are exposed in the fifth hole 102.

[0102] The common electrode 40 is plated on the upper surface of the passivation layer 10, and the common electrode 40 is connected with the TP lines 30 through the fifth hole 102. One end of the liquid crystal Cst of the liquid crystal display is connected with the pixel electrode 5, and the other end is connected with the common electrode 40. The full name of the TP line is Touch Panel Senser Line, and the TP line provides a voltage signal for the common electrode.

[0103] The first metal layer and the second metal layer are both Ti / AL / Ti three-layer structures or MO / AL / MO three-layer structures.

[0104] The gate insulation layer 4 is a single-layer structure of SiOx or a double-layer structure of SiNx / SiOx, the passivation layer 10 is made of SiO2, and the outer insulation layer is made of SiOx, SiNO or SiNx.

[0105] The active layer 6 is made of IGZO, and the conductive layer 20, the pixel electrode 5, the first electrode block 51, the second electrode block 52, the third electrode block 53, the second signal connecting line 92 and the common electrode 40 are all made of ITO. ITO has good conductivity and light transmittance, and the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are all made of ITO, so that the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 can be formed in the same process, and the conductive layer 20 and the common electrode 40 of the array substrate are all made of ITO, so that the conductive layer 20 and the common electrode 40 can be formed in the same process, thereby simplifying the substrate structure and improving the production capacity.

[0106] The first metal layer further forms the second CK signal line 32 and the fourth CK signal line 34 which are spaced apart, and the potential of the second CK signal line 32 is opposite to that of the fourth CK signal line 34.

[0107] The first CK signal line (CK1) is connected with the gate of the array substrate of the first row, the second CK signal line (CK2) is connected with the gate of the array substrate of the second row, the third CK signal line (CK3) is connected with the conductive layer of the array substrate of the third row, and the fourth CK signal line (CK4) is connected with the conductive layer of the array substrate of the fourth row.

[0108] For the first row of the array substrate, the first hole 41 is formed at the position of the first row gate 2, the second hole 42 is formed at the position of the first CK signal line 31, and the third hole 43 is formed at the position of the third CK signal line 33, and the first row of the array substrate has the first signal connecting line 91 and the second signal connecting line 92; for the second row of the array substrate, the first hole 41 is formed at the position of the second row gate 2, the second hole 42 is formed at the position of the second CK signal line 32, and the third hole 43 is formed at the position of the fourth CK signal line 34, and the second row of the array substrate also has the first signal connecting line 91 and the second signal connecting line 92.

[0109] The signal timing phase of the first CK signal wire 31 is earlier than that of the second CK signal wire 32 by a quarter of a period, and the signal timing phase of the third CK signal wire 33 is earlier than that of the fourth CK signal wire 34 by a quarter of a period. When the first CK signal wire 31 drives the gate 2 of the first row of TFT devices to be high, the source 7 and the drain 8 of the first row of TFT devices are turned on, and the data voltage signal is written to the pixel electrode 5. After a quarter of a period, the second CK signal wire 32 drives the gate 2 of the second row of TFT devices to be high, the source 7 and the drain 8 of the second row of TFT devices are turned on, and the data voltage signal is written to the pixel electrode 5. When the first CK signal wire 31 is high, the third CK signal wire 33 is low, and when the first CK signal wire 31 is low, the third CK signal wire 33 is high. Similarly, the potential of the second CK signal wire 32 is opposite to that of the fourth CK signal wire 34. Under the control of the first CK signal wire 31, the second CK signal wire 32, the third CK signal wire 33 and the fourth CK signal wire 34, the array substrate makes the display screen be sequentially lit from top to bottom or from bottom to top by row by row of pixels. For example, when the first CK signal wire is 10V, the third CK signal wire is -15V; when the first CK signal wire is -15V, the third CK signal wire is 10V.

[0110] The drive IC is also included, which is connected with the first CK signal wire 31, the second CK signal wire 32, the third CK signal wire 33 and the fourth CK signal wire 34. The drive IC is used to give different timing signals to the first CK signal wire 31, the second CK signal wire 32, the third CK signal wire 33 and the fourth CK signal wire 34.

[0111] The working principle of the array substrate for maintaining the potential level of the pixel electrode of the present application is as follows:

[0112] Here, the present embodiment is described by taking the single-side level transmission 4CK design as an example (note that the circuit design of the present application is not limited to single-side level transmission 4CK, but can also be double-side level transmission). The timing diagram is as shown in Figure 5 Figure 4 is Figure 3 ​Circuit diagram of all pixels in the first row. Simply put, the image is displayed by lighting up the pixels row by row, either from top to bottom or from bottom to top. Pixel lighting requires that the gate 2 corresponding to the TFT device in that row be at a high potential. This allows the TFT device to turn on, allowing data signals to be written to the pixel electrode 5, thereby controlling the liquid crystal twist and illuminating the pixel. Taking the first row of pixel display as an example, when the first CK signal line 31 is at a high potential, the third CK signal line 33 is at a low potential. The high potential of the first CK signal line 31 is transmitted to the first row gate 2, the first row TFT device is turned on, the pixel electrode 5 signal is written, and the low potential of the third CK signal line 33 is transmitted to the first row conductive layer 20; when the first CK signal line 31 switches to a low potential, the third CK signal line 33 switches to a high potential, the gate 2 switches from a high potential to a low potential, and the parasitic capacitance formed by the gate 2 and the drain 8 will have a coupling effect, thereby pulling down the drain 8 voltage. However, since the third CK signal line 33 is switched from a low potential to a high potential at this time, that is, the conductive layer 20 of the first row is switched from a low potential to a high potential, the supplementary capacitance formed by the conductive layer 20 and the drain 8 will also have a coupling effect, thereby pulling up the drain voltage. Therefore, the drain voltage will not change due to the gate jump, that is, the voltage of the pixel electrode will not change. Note that the design requires C 补充 with C gd The purpose of this design is to ensure that there are two feedthrough voltages, one increasing and one decreasing, of equal magnitude at the drain 8. Similarly, each row of TFT devices can avoid the feedthrough voltage caused by the gate 2 production jump.

[0113] From a microscopic perspective, it is actually the migration of charges between the drain 8 and the pixel electrode 5 that causes the amount of charge stored on the pixel electrode 5 to change, thereby causing the voltage to change. After the pixel electrode 5 is charged, the potential between the drain 8 and the pixel electrode 5 is equal, and no electron migration occurs between them. However, since the gate 2 voltage switches from a high potential to a low potential at this moment, this change will be coupled to the drain 8 through the parasitic capacitance formed by the gate 2 and the drain 8. At this time, a voltage difference will be generated between the drain 8 and the pixel electrode 5, causing charge migration between the drain 8 and the pixel electrode 5, thereby causing the pixel electrode 5 to change. The starting point for the present invention to solve this problem is to add a conductive layer 20, which forms a supplementary capacitor C with the drain 8. 补充 Then, opposite potential signals are given to the gate 2 and the conductive layer 20 through the first CK signal line 31 and the third CK signal line 33, respectively, which offsets the coupling effect of the parasitic capacitance and the supplementary capacitance and improves the working performance of the device.

[0114] A manufacturing method of an array substrate for maintaining pixel electrode potential level, comprising the following steps:

[0115] S1, refer to Figure 8 Plating a first metal layer on the upper surface of the glass substrate 1 to form a gate 2, a first CK signal trace 31, a second CK signal trace 32, a third CK signal trace 33 and a fourth CK signal trace 34, the potential of the first CK signal trace is opposite to that of the third CK signal trace, and the potential of the second CK signal trace 32 is opposite to that of the fourth CK signal trace 34;

[0116] The gate 2 is used to turn on and off the TFT device, the first CK signal trace 31 is used to transmit the first row gate 2 signal, the second CK signal trace 32 is used to transmit the second row gate signal, the third CK signal trace 33 is used to transmit the first row conductive layer 20 signal, and the fourth CK signal trace 34 is used to transmit the second row conductive layer signal; the material of the first metal layer can be selected from any one of MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure (MO as the top layer), and AL / Ti double-layer structure (Ti as the top layer), and PVD film formation. The resistance of AL is small and is used for conduction (which can be replaced by Cu), which can reduce impedance and power consumption; secondly, the expansion coefficient of MO or Ti is small, which can inhibit the deformation of AL in high-temperature process and prevent oxidation of AL.

[0117] S2, refer to Figure 9 Plating a gate insulating layer 4 on the upper surface of the glass substrate 1 and the first metal layer;

[0118] The gate 2 insulating layer acts as an insulating medium and a capacitive medium between the gate 2 and the active layer 6, and is made of a single layer of SiOx or a double layer of SiNx / SiOx, and is formed by CVD. Considering that the current requirements for TFT devices are fast response and low power consumption, which are achieved by reducing the size of TFT devices, and in order to realize the miniaturization of the device, the gate insulating layer 4 needs to select a suitable high-K material (such as HfO2), but considering that there are many defects in the interface of HfO2, if it is directly in contact with the active layer 6 or the gate 2 metal, it may affect the stability of the device, so a good interface of SiOx or SiNx (SiNx can only be used as a contact film layer with the gate metal layer, if it is used as a contact surface with IGZO, the residual H in the SiNx film layer will destroy the characteristics of IGZO) can be considered as a contact surface, such as a three-layer structure of SiOx / HfO2 / SiOx as a GI insulating layer, in order to ensure the advantages of high-K material, the thickness of HfO2 in the three-layer structure needs to be larger than that of SiOx.

[0119] S3, refer toFigure 10 The first, second and third holes 41, 42 and 43 are formed in the gate insulating layer 4, the gate 2 is exposed in the first hole 41, the first CK signal line 31 is exposed in the second hole 42, and the third CK signal line 33 is exposed in the third hole 43;

[0120] For the first row of the array substrate, the first hole 41 is formed at the position of the first row of the gate, the second hole 42 is formed at the position of the first CK signal line 31, and the third hole 43 is formed at the position of the third CK signal line 33. For the second row of the array substrate, the first hole 41 is formed at the position of the second row of the gate, the second hole 42 is formed at the position of the second CK signal line 32, and the third hole 43 is formed at the position of the fourth CK signal line 34. The first, second and third holes 41, 42 and 43 are formed outside the pixel display area 11.

[0121] The first, second and third holes 41, 42 and 43 are formed by dry etching. The first and second holes 41 and 42 provide the connection between the first CK signal line 31 (or the second CK signal line 32), the first signal connection line 91 and the gate 2. The third hole 43 provides the connection between the third CK signal line 33 (or the fourth CK signal line 34) and the second signal connection line 92.

[0122] S4, referring to Figure 11 The pixel electrode 5 is plated on the upper surface of the gate insulating layer 4, and the pixel electrode 5 is also located beside the gate 2.

[0123] The first, second and third electrode blocks 51, 52 and 53 are respectively plated in the first, second and third holes 41, 42 and 43. The first electrode block 51 is connected with the gate 2, the second electrode block 52 is connected with the first CK signal line 31, and the third electrode block 53 is connected with the third CK signal line 33.

[0124] The first, second and third electrode blocks 51, 52 and 53 are made of the same material as the pixel electrode 5.

[0125] The pixel electrode 5, the first, second and third electrode blocks 51, 52 and 53 are made of ITO, mainly because ITO has good conductivity and light transmittance, PVD film forming and acid wet etching. By pre-forming the first, second and third holes 41, 42 and 43 in the gate insulating layer 4, and then filling the first, second and third electrode blocks 51, 52 and 53, the subsequent etching process is avoided to affect the first metal layer.

[0126] S5, referring toFigure 12 S5, refer to

[0127] The material of the active layer 6 is metal oxide semiconductor such as IGZO, PVD film forming, and etching is wet etching.

[0128] S6, refer to Figure 13 S7, refer to

[0129] The material of the second metal layer can be selected as MO / AL / MO three-layer structure or Ti / AL / Ti three-layer structure, PVD film forming, and acid wet etching. The resistance of AL is small and is used for conducting electricity (Cu can be used instead), which can reduce impedance and power consumption; secondly, the expansion coefficients of the outer metal MO or Ti are small, which can inhibit the deformation of AL in high-temperature processing and prevent oxidation of AL.

[0130] S7, refer to Figure 14 S8, refer to

[0131] The fourth and fifth holes 101 and 102 are etched in the passivation layer 10, the third electrode block 53 is exposed from the fourth hole 101, and the TP trace 30 is exposed from the fifth hole 102; the fourth and fifth holes 101 and 102 are outside the pixel display area 11.

[0132] The passivation layer 10 is made of SiO2 and formed by CVD. A fourth hole 101 and a fifth hole 102 are formed by dry etching. The fourth hole 101 provides a connection between the third CK signal trace 33 and the conductive layer 20, while the fifth hole 102 provides a connection between the common electrode 40 and the TP trace 30. Since the gate insulating layer 4 below the fourth hole 101 has been opened to form a third hole 43 in step S4, and the third hole 43 is covered by the third electrode block 53 made of ITO with excellent conductivity, and the upper surface of the TP trace 30 is located at the same position as the upper surface of the third electrode block 53, the etching depth of the fourth hole 101 and the fifth hole 102 is the thickness of one layer of the passivation layer 10. As a result, the outer protective metal layer of the third CK signal trace 33 of the first metal layer is not etched, thereby preventing the inner metal line (AL) from being exposed to air and oxidized due to the loss of the outer protective metal layer (MO or Ti) of the third CK signal trace 33, thereby increasing the contact resistance.

[0133] S8, see Figure 15 At the same time, the conductive layer 20, the second signal connection line 92 and the common electrode 40 are plated on the upper surface of the passivation layer 10. The conductive layer 20 is also located directly above the drain electrode 8. The conductive layer 20 is connected to the right end of the second signal connection line 92. The left end of the second signal connection line 92 passes through the fourth hole 43 and is connected to the third electrode block 53. The lead of the common electrode 40 passes through the fifth hole 102 and is connected to the TP trace 30.

[0134] like Figure 7 As shown, the conductive layer 20 and the second signal connection line 92 do not cover the channel of the active layer 6; this prevents the voltage signal of the conductive layer 20 and the second signal connection line 92 from interfering with the channel of the active layer 6, thereby ensuring the working stability of the active layer.

[0135] The material of the conductive layer 20 and the common electrode 40 is ITO, mainly because ITO has good conductivity and light transmittance, PVD film formation, and acid wet etching. The materials of the conductive layer 20 and the common electrode 40 are both ITO, so the conductive layer 20 and the common electrode 40 can be formed in the same process, which can simplify the substrate structure and improve production capacity. The conductive layer 20 is designed to be directly above the source 7 in order to form a capacitor structure with the drain 8, and the capacitance of the supplementary capacitor formed by the conductive layer 20 and the drain 8 is consistent with the capacitance of the parasitic capacitor formed by the gate 2 and the drain 8. This can be achieved by regulating the facing area of ​​the conductive layer 20 and the film layer distance to achieve equal capacitance.

[0136] While the foregoing description has described specific embodiments of the application, one ordinary skill in the art will appreciate that various modifications and changes can be made thereto without departing from the spirit and scope of the application, as set forth in the appended claims.

Claims

1. An array substrate for maintaining pixel electrode potential level, characterized in that: include: glass substrate; a first metal layer, plated on the upper surface of the glass substrate, forming a gate, a first CK signal line, and a third CK signal line that are spaced apart, wherein the potential of the first CK signal line is opposite to that of the third CK signal line; a gate insulating layer, plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with a first hole, a second hole, and a third hole, the gate being exposed through the first hole, the first CK signal trace being exposed through the second hole, and the third CK signal trace being exposed through the third hole; a pixel electrode, plated on the upper surface of the gate insulating layer and located on the side of the gate; a first electrode block, plated on the first hole and connected to the grid; a second electrode block, plated on the second hole and connected to the first CK signal trace; a third electrode block, plated on the third hole and connected to the third CK signal trace; The first electrode block, the second electrode block, and the third electrode block are made of the same material as the pixel electrode; an active layer, plated on the upper surface of the gate insulating layer and located directly above the gate; a second metal layer, plated on the upper surface of the gate insulating layer, forming a source electrode, a drain electrode, and a first signal connection line that are spaced apart, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, and the drain electrode being further connected to the pixel electrode, the right end of the first signal connection line being connected to the first electrode block, and the left end of the first signal connection line being connected to the second electrode block; a passivation layer, plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer, and the pixel electrode, wherein the passivation layer is provided with a fourth hole, and the third electrode block is exposed through the fourth hole; A conductive layer is plated on the upper surface of the passivation layer and is also located directly above the drain. A second signal connection line is also plated on the upper surface of the passivation layer. The conductive layer is connected to the right end of the second signal connection line, and the left end of the second signal connection line passes through the fourth hole and is connected to the third electrode block.

2. The array substrate for maintaining pixel electrode potential level according to claim 1, wherein: Also includes: The second metal layer also forms TP traces distributed at intervals; The passivation layer is further provided with a fifth hole, and the TP trace is exposed through the fifth hole; A common electrode is plated on the upper surface of the passivation layer, and a lead of the common electrode passes through the fifth hole and is connected to the TP trace.

3. The array substrate for maintaining pixel electrode potential level according to claim 2, wherein: The first metal layer and the second metal layer are both a Ti / Al / Ti three-layer structure or a MO / Al / MO three-layer structure.

4. The array substrate for maintaining pixel electrode potential level according to claim 2, wherein: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and the passivation layer is made of SiO2.

5. The array substrate for maintaining pixel electrode potential level according to claim 2, wherein: The active layer is made of IGZO material, and the conductive layer, pixel electrode, first electrode block, second electrode block, third electrode block and common electrode are all made of ITO material.

6. The array substrate for maintaining pixel electrode potential level according to claim 1, wherein: The first metal layer further forms a second CK signal line and a fourth CK signal line that are spaced apart from each other, and the potential of the second CK signal line is opposite to that of the fourth CK signal line; The first CK signal line is connected to the gate of the array substrate in the first row, the second CK signal line is connected to the gate of the array substrate in the second row, the third CK signal line is connected to the conductive layer of the array substrate in the first row, and the fourth CK signal line is connected to the conductive layer of the array substrate in the second row.

7. The array substrate for maintaining pixel electrode potential level according to claim 6, wherein: The signal timing phase of the first CK signal line is one quarter cycle earlier than the signal timing phase of the second CK signal line, and the signal timing phase of the third CK signal line is one quarter cycle earlier than the signal timing phase of the fourth CK signal line.

8. A method for manufacturing an array substrate for maintaining pixel electrode potential level, characterized in that: The following steps are involved: S1. Plate a first metal layer on the upper surface of a glass substrate to form a gate, a first CK signal line, and a third CK signal line that are spaced apart. The potential of the first CK signal line is opposite to that of the third CK signal line. S2, coating a gate insulating layer on the upper surface of the glass substrate and the first metal layer; S3, opening a first hole, a second hole, and a third hole in the gate insulating layer, wherein the gate is exposed through the first hole, the first CK signal trace is exposed through the second hole, and the third CK signal trace is exposed through the third hole; S4, plating a pixel electrode on the upper surface of the gate insulating layer, wherein the pixel electrode is also located on the side of the gate; Plating a first electrode block, a second electrode block, and a third electrode block on the first hole, the second hole, and the third hole, respectively, wherein the first electrode block is connected to the gate, the second electrode block is connected to the first CK signal trace, and the third electrode block is connected to the third CK signal trace; The first electrode block, the second electrode block, and the third electrode block are made of the same material as the pixel electrode; S5, depositing an active layer on the upper surface of the gate insulating layer, wherein the active layer is located directly above the gate; S6. Plate a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode, and a first signal connection line that are spaced apart. The source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, and the drain electrode is also connected to the pixel electrode. The right end of the first signal connection line is connected to the first electrode block, and the left end of the first signal connection line is connected to the second electrode block. S7, coating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, the second metal layer, and the pixel electrode; A fourth hole is formed in the passivation layer, wherein the third electrode block is exposed in the fourth hole; S8. Plate a conductive layer and a second signal connection line on the upper surface of the passivation layer, wherein the conductive layer is also located directly above the drain electrode, the conductive layer is connected to the right end of the second signal connection line, and the left end of the second signal connection line passes through the fourth hole and is connected to the third electrode block.

9. The method for manufacturing an array substrate for maintaining pixel electrode potential level according to claim 8, wherein: Also includes: In the step S6, the second metal layer further forms TP traces distributed at intervals; In S7, a fourth hole and a fifth hole are simultaneously etched in the passivation layer, and the TP trace is exposed in the fifth hole; In the step S8 , the conductive layer, the second signal connection line and the common electrode are simultaneously plated on the upper surface of the passivation layer, and the lead of the common electrode is further connected to the TP line through the fifth hole.

10. The method for manufacturing an array substrate for maintaining pixel electrode potential level according to claim 9, wherein: The conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all made of ITO.

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