Display panel and preparation method thereof
By setting vias on the insulating layer to achieve electrical connection between the first and second wiring layers, the problem of low production yield during the splicing of large-size Micro-LED display panels is solved, and the stability and reliability of the display panels are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU VISTAR OPTEOLECTRONICS CO LTD
- Filing Date
- 2021-11-19
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies for manufacturing large-size Micro-LED display panels face challenges such as high technical difficulty during the splicing process, immature equipment and processes, and easy breakage of metal traces, resulting in low production yield.
By setting vias on the insulating layer, electrical connection between the first and second wiring layers is achieved, avoiding the need for opening vias on the substrate layer. This method of using insulating layer electrical connection improves the production yield of display panels.
This improves the production yield of display panels, avoids breakage caused by opening holes in the substrate layer, and enhances the stability and reliability of display panels.
Smart Images
Figure HDA0003365274910000011 
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Figure HDA0003365274910000031
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology
[0002] Micro-LED (micron-sized light-emitting diode) display panels have advantages such as long lifespan, high brightness, and compatibility with flexible substrates, making them a future trend in the display field. However, due to limitations in manufacturing capabilities, large-size Micro-LED display panels need to be spliced together from several smaller Micro-LED display panels. Therefore, how to achieve seamless splicing between small-size Micro-LED display panels has become one of the main bottlenecks in the production of large-size Micro-LED display panels.
[0003] Currently, the main technical directions for large-size splicing include glass side wiring, glass drilling, and flexible bending to the glass substrate. However, these solutions currently have problems such as high technical difficulty, immature processes / equipment, and easy breakage of metal wiring. Summary of the Invention
[0004] This application provides a display panel and a method for manufacturing the same, which can improve the production yield of the display panel.
[0005] A first aspect of this application provides a display panel, the display panel comprising: a substrate layer having a first side and a second side disposed opposite to each other; a first wiring layer disposed on the first side of the substrate layer, a portion of the first wiring layer extending outside the substrate layer or having a connection portion disposed at an opening of the substrate layer, the connection portion including at least a portion of a pad; a second wiring layer disposed on the second side of the substrate layer; and an insulating layer disposed on the side of the first wiring layer facing the substrate layer, the orthographic projection of the insulating layer on the first wiring layer at least partially covering the connection portion, wherein the insulating layer has vias corresponding to the pads, and the second wiring layer is electrically connected to the pads through the vias.
[0006] A second aspect of this application provides a method for fabricating a display panel, the method comprising: providing a display panel preform, the display panel preform comprising: a substrate layer having a first side and a second side disposed opposite to each other; a first wiring layer disposed on the first side of the substrate layer, a portion of the first wiring layer extending outside the substrate layer or forming a connection portion at an opening of the substrate layer, the connection portion including at least a portion of a pad; an insulating layer disposed on the side of the first wiring layer facing the substrate layer, and at least a portion of the orthographic projection on the first wiring layer covering the connection portion; forming vias corresponding to the pads on the insulating layer; forming a second wiring layer on the second side of the substrate layer, the second wiring layer being electrically connected to the pads through the vias.
[0007] The beneficial effects are: the display panel of this application can electrically connect the first wiring layer and the second wiring layer by setting an insulating layer, which eliminates the need to open holes in the substrate layer. This avoids the phenomenon of breakage caused by opening holes in the substrate layer in the prior art, thereby improving the production yield of the display panel. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0009] Figure 1 This is a flowchart illustrating one embodiment of the method for manufacturing the display panel of this application;
[0010] Figure 2 yes Figure 1 Process flow diagram of the preparation method;
[0011] Figure 3 yes Figure 1 Process flow diagram for step S110;
[0012] Figure 4 This is a partial process flow diagram of another embodiment of the method for manufacturing the display panel of this application;
[0013] Figure 5 This is a partial process flow diagram of another embodiment of the method for manufacturing the display panel of this application;
[0014] Figure 6 This is a partial process flow diagram of another embodiment of the method for manufacturing the display panel of this application;
[0015] Figure 7 This is a partial process flow diagram of another embodiment of the method for manufacturing the display panel of this application;
[0016] Figure 8 This is a schematic diagram of the structure of one embodiment of the display panel of this application;
[0017] Figure 9 This is a schematic diagram of another embodiment of the display panel of this application;
[0018] Figure 10 This is a schematic diagram of another embodiment of the display panel of this application. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0020] It should be noted that the solution in this application can be applied not only to Micro-LED (micron-sized light-emitting diode) display panels, but also to other types of display panels, such as LCD (Liquid Crystal Display) display panels and OLED (Organic Light-Emitting Diode) display panels. However, for ease of explanation, the following description will use Micro-LED display panels as the reference.
[0021] Combination Figure 1 and Figure 2 In the first embodiment of this application, the method for manufacturing the display panel includes:
[0022] S110: Provides display panel preform 10.
[0023] Combination Figure 3 In this embodiment, the method for preparing the display panel preform 10 includes:
[0024] (a1) A buffer layer 12 is formed on the first side 111 of the substrate layer 11.
[0025] The substrate layer 11 plays a major supporting role in the display panel preform 10. Its material can be glass or other materials such as polyimide. The substrate layer 11 includes a first side 111 and a second side 112 disposed opposite to each other. The buffer layer 12 can be made of inorganic or organic materials; for example, the material of the buffer layer 12 includes at least one of silicon nitride and silicon oxide. The methods for forming the buffer layer 12 include, but are not limited to, vapor deposition and electroplating.
[0026] (b1) A first trace layer 13 is formed on the side of the buffer layer 12 away from the substrate layer 11, wherein the first trace layer 13 includes pads 131.
[0027] The material of the first wiring layer 13 is a conductive material, such as copper or aluminum.
[0028] The first routing layer 13 includes pads 131 and a first trace (not shown), which is electrically connected to the pads 131. The number of pads 131 may be more than one, and they can be distributed as needed.
[0029] During fabrication, a conductive layer is first formed on the side of the buffer layer 12 away from the substrate layer 11, and then a patterned conductive layer is formed to obtain the first wiring layer 13.
[0030] (c1) A light-emitting layer 14 is formed on the side of the first wiring layer 13 away from the substrate layer 11.
[0031] The light-emitting layer 14 includes a light-emitting unit 141, which is electrically connected to the pad 131 via a first trace of the first trace layer 13. After receiving an electrical signal transmitted by the first trace, the light-emitting unit 141 emits light. The light-emitting unit 141 is a Micro-LED light-emitting unit.
[0032] (d1) A cover plate 15 is formed on the side of the light-emitting layer 14 away from the substrate layer 11.
[0033] The cover plate 15 serves as a support to prevent the first wiring layer 13 and the light-emitting layer 14 from bending and deforming during subsequent processes.
[0034] The material of the cover plate 15 can be glass or metal, and there are no restrictions on it.
[0035] It is understandable that other functional layers, such as an encapsulation layer, can be formed before the cover plate 15 is formed on the side of the light-emitting layer 14 facing away from the substrate layer 11.
[0036] (e1) Remove part of the substrate layer 11 corresponding to the pad 131 to expose part of the buffer layer 12.
[0037] An opening 113 can be formed at the location of the pad 131 on the substrate layer 11 using methods such as laser cutting, mechanical cutting, or chemical etching, thereby exposing part of the buffer layer 12. At the same time, the portion of the first trace layer 13 corresponding to the opening 113 is defined as the connection portion 132, wherein the connection portion 132 includes at least a portion of the pad 131. That is, the orthogonal projection of the opening 113 on the first trace layer 13 covers the pad 131, or at least partially covers the pad 131.
[0038] When an opening 113 is formed at the position of the pad 131 corresponding to the substrate layer 11 by chemical etching, the buffer layer 12 can be used as an etching barrier layer.
[0039] (f1) A support layer 16 is formed on the side of the exposed portion of the buffer layer 12 away from the first wiring layer 13, wherein the support layer 16 and the buffer layer 12 together constitute an insulating layer 17.
[0040] The material of the support layer 16 can be either inorganic or organic, and there are no restrictions on this.
[0041] In this embodiment, the support layer 16 is disposed on the same layer as the substrate layer 11, and the thickness of the support layer 16 is equal to the thickness of the substrate layer 11. The shape and area of the support layer 16 correspond to the shape and area of the connection portion 132. That is, the orthogonal projection of the support layer 16 on the first wiring layer 13 covers the connection portion 132.
[0042] In other embodiments, the thickness of the support layer 16 may be different from the thickness of the substrate layer 11, or the area of the support layer 16 may be smaller than the area of the connection portion 132. That is, the orthographic projection of the support layer 16 on the first wiring layer 13 only covers a portion of the connection portion 132.
[0043] Through the above steps, the display panel preform 10 was obtained.
[0044] S120: A via 171 corresponding to the pad 131 is formed on the insulating layer 17.
[0045] Continue reading Figure 2 It is understandable that the via 171 penetrates the support layer 16 and the buffer layer 12.
[0046] The via 171 can be formed by mechanical cutting, laser cutting, or chemical etching, etc., and there are no restrictions.
[0047] S130: A second trace layer 18 is formed on the second side 112 of the substrate layer 11, and the second trace layer 18 is electrically connected to the pad 131 through the via 171.
[0048] The second trace layer 18 includes a second trace (not shown). The second trace is electrically connected to the pad 131 through the via 171, so that the second trace can introduce external electrical signals. Then the external electrical signals pass through the pad 131 and the first trace to reach the light-emitting unit 141, causing the light-emitting unit 141 to emit light.
[0049] The material and forming method of the second wiring layer 18 are the same as those of the first wiring layer 13, and will not be described again here.
[0050] In order to protect the second wiring layer 18 and prevent oxidation, corrosion and other phenomena from affecting the normal display of the light-emitting unit 141, this embodiment also forms a protective layer 19 on the side of the second wiring layer 18 away from the substrate layer 11. The protective layer 19 at least partially covers the second wiring layer 18 with its orthogonal projection.
[0051] S140: Remove cover plate 15.
[0052] The purpose of the cover plate 15 is to prevent the first wiring layer 13, light-emitting layer 14, etc. exposed in the opening 113 from bending due to lack of support from the substrate layer 11 after step (e1), which would affect subsequent processes. After step (f1), the support layer 16 can replace the removed part of the substrate layer 11 to provide support, so the cover plate 15 is no longer needed. Therefore, the cover plate 15 is removed in step S140, and then the display panel 101 is obtained.
[0053] In related technologies, in order to electrically connect the first wiring layer 13 and the second wiring layer 18, one approach is to drill holes in the substrate layer 11 of the glass plate. However, the process of drilling holes in the glass plate is complex, and the glass plate is prone to breakage after dense drilling. Therefore, product scrap is likely to occur during the manufacturing process, resulting in a low yield of the display panel.
[0054] In the preparation process of the above embodiment, vias 171 are opened on the insulating layer 17 to electrically connect the first wiring layer 13 and the second wiring layer 18. By opening vias 171 on the insulating layer 17 instead of opening holes on the substrate layer 11, the defect of low product yield caused by drilling holes on the substrate layer 11 can be avoided.
[0055] In the above embodiment, the buffer layer 12 serves to support the pads 131 in the first trace layer 13, preventing the pads 131 from detaching when part of the substrate layer 11 is removed. However, in other embodiments, to save costs, the buffer layer 12 may be omitted, such as... Figure 4 As shown, when removing part of the substrate layer 11, only part of the pad 131 is exposed. The bonding force between the unexposed part of the pad 131 and the substrate layer 11 can prevent the pad 131 from falling off.
[0056] In the above embodiments, in order to provide the support layer 16 on the same layer as the substrate layer 11, a portion of the substrate layer 11 needs to be removed. However, in other embodiments, to save costs and avoid waste, a portion of the substrate layer 11 may not be removed during the fabrication process. See also Figure 5 Before forming the buffer layer 12, a support layer 16 is formed on the same layer as the substrate layer 11. Then, the buffer layer 12, the first wiring layer 13, and the light-emitting layer 14 are formed in sequence, so that the support layer 16 and the buffer layer 12 constitute the insulating layer 17.
[0057] The buffer layer 12, the first wiring layer 13, and a portion of the light-emitting layer 14 are disposed on the support layer 16, and the first wiring layer 13 disposed on the support layer 16 includes pads 131. Then, vias 171 are formed in the insulating layer 17 to expose at least a portion of the pads 131, and finally, a second wiring layer 18 is formed that is electrically connected to the pads 131 through the vias 171. In this process, since a portion of the substrate layer 11 is not removed, the first wiring layer 13 and the light-emitting layer 14 do not lose their support, thus eliminating the need for a cover plate 15. However, to prevent bending of the various film layers during fabrication, a cover plate 15 may be formed.
[0058] At the same time Figure 5 In this embodiment, since it is not necessary to remove part of the substrate layer 11 after forming the first wiring layer 13, there is no risk of the pads 131 falling off. Therefore, in another embodiment, the buffer layer 12 may not be provided. (See reference...) Figure 6 First, a support layer 16 is formed on the same layer as the substrate layer 11. Then, a first trace layer 13 and a light-emitting layer 14 are formed sequentially. The support layer 16 constitutes an insulating layer 17. Parts of the first trace layer 13 and the light-emitting layer 14 are disposed on the support layer 16, and the first trace layer 13 disposed on the support layer 16 includes pads 131. Then, vias 171 are formed in the insulating layer 17 to expose at least a portion of the pads 131. Finally, a second trace layer 18 is formed that is electrically connected to the pads 131 through the vias 171, and a protective layer 19 protects the second trace layer 18. Figure 6 It can be seen that the final display panel 101 does not include the buffer layer 12.
[0059] Combination Figure 7 In the second embodiment of this application, the method for manufacturing the display panel includes:
[0060] (a2) A buffer layer 22 is formed on the first side 211 of the substrate layer 21, wherein the buffer layer 22 constitutes an insulating layer 27.
[0061] Step (a2) is the same as step (a1) in the above embodiments, and you can refer to the above embodiments for details.
[0062] (b2) A first trace layer 23 is formed on the side of the buffer layer 22 away from the substrate layer 21, wherein the first trace layer 23 includes pads 231.
[0063] Step (b2) is the same as step (b1) in the above embodiments, and you can refer to the above embodiments for details.
[0064] (c2) A light-emitting layer 24 is formed on the side of the first wiring layer 23 away from the substrate layer 21.
[0065] Step (c2) is the same as step (c1) in the above embodiments, and you can refer to the above embodiments for details.
[0066] (d2) A cover plate 25 is formed on the side of the light-emitting layer 24 away from the substrate layer 21.
[0067] Step (d2) is the same as step (d1) in the above embodiments, and you can refer to the above embodiments for details.
[0068] (e2) Remove part of the substrate layer 21 corresponding to the pad 231 to expose part of the buffer layer 22.
[0069] An opening 213 is formed at the position of the pad 231 on the substrate layer 21, exposing part of the buffer layer 22. At the same time, the part of the first trace layer 23 corresponding to the opening 213 is defined as the connection part 232.
[0070] Step (e2) is the same as step (e1) in the above embodiments, and can be found in the above embodiments for details, which will not be repeated here.
[0071] After going through steps (a2) to (e2) above, the display panel preform 20 is obtained.
[0072] (f2) A via 271 is formed on the insulating layer 27 to expose at least a portion of the pad 231.
[0073] At least a portion of the pad 231 is exposed in the via 271.
[0074] (g2) A second wiring layer 28 is formed on the second side 212 of the substrate layer 21, and the second wiring layer 28 is electrically connected to the pad 231 through the via 271. The second wiring layer 28 further extends from the side of the substrate layer 21, the surface of the buffer layer 22 away from the second wiring layer 28, and the via 271 to the pad 231.
[0075] Unlike the above implementation, the second wiring layer 28 needs to pass through the side of the substrate layer 21 and the surface of the buffer layer 22 away from the second wiring layer 28 to reach the pad 231.
[0076] (h2) A fill layer 26 is provided on the same layer as the substrate layer 21, and the orthographic projection of the fill layer 26 on the first wiring layer 23 covers the connection portion 232.
[0077] The material of the filling layer 26 can be either organic or inorganic, and there are no restrictions on this.
[0078] The filling layer 26 can be formed in the same layer as the substrate layer 21 by means of vapor deposition, electroplating, etc., or the filling layer 26 can be prepared in advance and then spliced together with the substrate layer 21.
[0079] To ensure flatness, the surface of the filler layer 26 facing away from the connector 232 is flush with the surface of the substrate layer 21 facing away from the first wiring layer 23. The shape and area of the filler layer 26 correspond to the shape and area of the connector 232. That is, the side of the filler layer 26 is attached to the side of the substrate layer 21, and the orthographic projection of the filler layer 26 on the first wiring layer 23 covers the connector 232. It should be noted that in other embodiments, the thickness of the filler layer 26 may be greater than the thickness of the substrate layer 21.
[0080] Alternatively, to prevent the filler layer 26 from squeezing the second wiring layer 28, a certain gap can be reserved between the side of the filler layer 26 and the side of the substrate layer 21.
[0081] In order to protect the second wiring layer 28 and prevent oxidation, corrosion and other phenomena from occurring on the exposed second wiring layer 28, a protective layer 29 can be provided on the side of the second wiring layer 28 away from the substrate layer 21 to cover the second wiring layer 28.
[0082] (i2) Remove cover plate 25.
[0083] After removing the cover plate 25, the display panel 201 is obtained.
[0084] In related technologies, in order to electrically connect the first wiring layer 23 and the second wiring layer 28, a second approach is to set wiring on the side of the substrate layer 21 and use the wiring to electrically connect the first wiring layer 23 and the second wiring layer 28. This approach will cause the wiring set on the side of the substrate layer 21 to fall off when splicing display panels due to the squeezing and friction of the two adjacent display panels, and the stability and reliability are not guaranteed.
[0085] In the fabrication process of the above embodiment, a portion of the substrate layer 21 corresponding to the pad 231 is removed, making the area of the substrate layer 21 smaller than the area of the first wiring layer 23. Vias 271 are formed on the insulating layer 27 to electrically connect the first wiring layer 23 and the second wiring layer 28. This eliminates the need for drilling holes in the substrate layer 21, preventing breakage. Furthermore, when the display panels are assembled, the wiring on the side of the substrate layer 21 is not squeezed by adjacent display panels, preventing wiring detachment and improving the yield rate of the display panels. Additionally, the filler layer 26 serves to protect the second wiring layer 28 and also provides support for the first wiring layer 23, the light-emitting layer 24, etc., ensuring the flatness of the display panel.
[0086] It should be noted that in other embodiments, when the display panel can be guaranteed to have good flatness under the support of the substrate layer 21, the filler layer 26 may not be provided.
[0087] See Figure 8 , Figure 8 This is a schematic diagram of the structure of a display panel according to an embodiment of the present application. The display panel 30 includes a substrate layer 31, a first wiring layer 32, a second wiring layer 33, and an insulating layer 34.
[0088] The substrate 31 has a first side 311 and a second side 312 disposed opposite to each other; a first wiring layer 32 is disposed on the first side 311 of the substrate 31, and a portion of the first wiring layer 32 extends outside the substrate 31 or forms a connection portion 321 at an opening of the substrate 31, the connection portion 321 including at least a portion of a pad 322; a second wiring layer 33 is disposed on the second side 312 of the substrate 31; an insulating layer 34 is disposed on the side of the first wiring layer 32 facing the substrate 31, and at least a portion of the orthographic projection on the first wiring layer 32 covers the connection portion 321, wherein the insulating layer 34 has a via 341 corresponding to the pad 322, and the second wiring layer 33 is electrically connected to the pad 322 through the via 341.
[0089] The insulating layer 34 includes a support layer 35 disposed on the same layer as the substrate layer 31. The orthographic projection of the support layer 35 on the first wiring layer 32 covers the connection portion 321, and the via 341 penetrates the support layer 35.
[0090] The thickness of the support layer 35 is the same as that of the substrate layer 31, and the shape and area of the support layer 35 correspond to the shape and area of the connecting part 321.
[0091] Optionally, the insulating layer 34 may also include a buffer layer 36. The buffer layer 36 is at least partially disposed between the support layer 35 and the connection portion 321. The via 341 further penetrates the buffer layer 36.
[0092] The display panel 30 also includes a light-emitting layer 37, which is disposed on the side of the first wiring layer 32 opposite to the substrate layer 31, and includes light-emitting units 371. The light-emitting units 371 are electrically connected to pads 322 through the first wiring layer 32.
[0093] The display panel 30 also includes a protective layer 38 disposed on the side of the second wiring layer 33 opposite to the light-emitting layer 37. At least a portion of the protective layer 38 is orthogonally projected onto the second wiring layer 33 to cover the second wiring layer 33, thereby protecting the second wiring layer 33.
[0094] The display panel 30 is a micro-LED display panel, and the substrate 31 is a glass plate.
[0095] See Figure 9 ,and Figure 8 The implementation method differs in that, in this embodiment, the display panel 30 does not include the buffer layer 36, and the support layer 35 constitutes the insulating layer 34.
[0096] The display panel 30 has the same structure as the display panel 101 in the above embodiments. For its preparation method and specific structure, please refer to the relevant content above, which will not be repeated here.
[0097] See Figure 10 , Figure 10 This is a schematic diagram of another embodiment of the display panel of this application. The display panel 40 includes a substrate layer 41, a first wiring layer 42, a second wiring layer 43, and an insulating layer 44.
[0098] The substrate 41 has a first side 411 and a second side 412 disposed opposite to each other; a first wiring layer 42 is disposed on the first side 411 of the substrate 41, and a portion of the first wiring layer 42 extends outside the substrate 41 or forms a connection portion 421 at an opening of the substrate 41, the connection portion 421 including at least a portion of a pad 422; a second wiring layer 43 is disposed on the second side 412 of the substrate 31; an insulating layer 44 is disposed on the side of the first wiring layer 42 facing the substrate 41, and at least a portion of the first wiring layer 42 is orthogonally projected to cover the connection portion 421, wherein the insulating layer 44 is provided with a via 441 corresponding to the pad 422, and the second wiring layer 43 is electrically connected to the pad 422 through the via 441.
[0099] The insulating layer 44 includes a buffer layer 45, which at least partially covers the connection portion 421 by its orthogonal projection on the first trace layer 42. A via 441 penetrates the buffer layer 45. The second trace layer 43 further extends from the side of the substrate layer 41, the surface of the buffer layer 45 away from the connection portion 421, and the via 441 to the pad 422.
[0100] The display panel 40 also includes a filling layer 46, which is disposed on the same layer as the substrate layer 41. The orthographic projection of the filling layer 46 on the first wiring layer 42 covers the connection portion 421.
[0101] The surface of the filler layer 46 facing away from the connector 421 is flush with the surface of the substrate layer 41 facing away from the first wiring layer 42, and the shape and area of the filler layer 46 are the same as the shape and area of the connector 421.
[0102] The display panel 40 also includes a light-emitting layer 47, which is disposed on the side of the first wiring layer 42 away from the substrate layer 41 and includes a light-emitting unit 471. The light-emitting unit 471 is electrically connected to the pad 422 through the first wiring layer 42.
[0103] The display panel 40 also includes a protective layer 48 disposed on the side of the second wiring layer 43 opposite to the light-emitting layer 47, and at least part of the orthogonal projection on the second wiring layer 43 covers the second wiring layer 43 to protect the second wiring layer 43.
[0104] The display panel 40 is a micro-LED display panel, and the substrate layer 41 is a glass plate.
[0105] The display panel 40 has the same structure as the display panel 201 in the above embodiment. For its preparation method and specific structure, please refer to the relevant content above, which will not be repeated here.
[0106] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A display panel, characterized in that, The display panel includes: A substrate layer having a first side and a second side disposed opposite to each other; A first wiring layer is disposed on a first side of the substrate layer. A portion of the first wiring layer extends outside the substrate layer and is provided with a connection portion, or the first wiring layer is provided with a connection portion at an opening in the substrate layer. The connection portion includes at least a portion of a pad. The second wiring layer is disposed on the second side of the substrate layer; An insulating layer is disposed on the side of the first trace layer facing the substrate layer. The orthographic projection of the insulating layer on the first trace layer at least partially covers the connection portion. The insulating layer is provided with vias corresponding to the pads, and the second trace layer is electrically connected to the pads through the vias.
2. The display panel according to claim 1, characterized in that, The insulating layer includes a support layer disposed on the same layer as the substrate layer. The orthogonal projection of the support layer on the first trace layer covers the connection portion, and the via penetrates the support layer. Preferably, the thickness of the support layer is the same as the thickness of the substrate layer, and the shape and area of the support layer correspond to the shape and area of the connecting portion.
3. The display panel according to claim 2, characterized in that, The insulating layer further includes: A buffer layer, at least partially disposed between the support layer and the connecting portion, wherein the through-hole further penetrates the buffer layer.
4. The display panel according to claim 1, characterized in that, The insulating layer includes a buffer layer, the buffer layer at least partially covering the connection portion in its orthogonal projection on the first trace layer, the via penetrating the buffer layer, and the second trace layer further extending from the side of the substrate layer, the surface of the buffer layer away from the connection portion, and the via to the pad.
5. The display panel according to claim 4, characterized in that, The display panel also includes: A filler layer is disposed on the same layer as the substrate layer, and the orthographic projection of the filler layer on the first trace layer covers the connection portion; Preferably, the surface of the filler layer facing away from the connector is flush with the surface of the substrate layer facing away from the first trace layer, and the shape and area of the filler layer correspond to the shape and area of the connector.
6. The display panel according to claim 1, characterized in that, The display panel also includes: A light-emitting layer is disposed on the side of the first wiring layer away from the substrate layer, and includes a light-emitting unit, wherein the light-emitting unit is electrically connected to the pad through the first wiring layer; Preferably, the display panel is a micro-LED display panel, and / or the substrate is a glass plate.
7. A method for manufacturing a display panel, characterized in that, The preparation method includes: A display panel preform is provided, the display panel preform comprising: a substrate layer having a first side and a second side disposed opposite to each other; a first wiring layer disposed on the first side of the substrate layer, wherein a portion of the first wiring layer extends beyond the substrate layer to form a connection portion, or the first wiring layer forms a connection portion at an opening in the substrate layer, the connection portion including at least a portion of a pad; and an insulating layer disposed on the side of the first wiring layer facing the substrate layer, wherein at least a portion of the orthographic projection on the first wiring layer covers the connection portion. Vias corresponding to the pads are formed on the insulating layer; A second trace layer is formed on the second side of the substrate layer, and the second trace layer is electrically connected to the pad through the via.
8. The method according to claim 7, characterized in that, The step of providing the display panel preform includes: A buffer layer is formed on the first side of the substrate layer; The first trace layer is formed on the side of the buffer layer opposite to the substrate layer, wherein the first trace layer includes the pads; Remove a portion of the substrate layer corresponding to the pads, exposing a portion of the buffer layer; A support layer is formed on the side of the exposed portion of the buffer layer away from the first trace layer, wherein the support layer and the buffer layer constitute the insulating layer.
9. The method according to claim 7, characterized in that, The step of providing the display panel preform includes: A support layer is formed in the same layer as the substrate layer, wherein the support layer constitutes the insulating layer; The first trace layer is formed on a first side of the substrate layer, wherein a portion of the first trace layer is disposed on the support layer, and the first trace layer disposed on the support layer includes the pads.
10. The method according to claim 8 or 9, characterized in that, The step of providing the display panel preform further includes: A light-emitting layer is formed on the side of the first wiring layer that is away from the substrate layer; A cover plate is formed on the side of the light-emitting layer opposite to the substrate layer; After forming the second wiring layer on the second side of the substrate, the method further includes: Remove the cover plate.