A method of suppressing negative capacitance finfet output current loss

Abstract

The application discloses a method for inhibiting output current loss of negative capacitance fin field effect transistor (NC-FinFET). The method changes the doping process of the source / drain extension region of the NC-FinFET, replaces the conventional uniform doping process technology with a Gaussian light doping process technology, thereby reducing the gate-drain coupling capacitance, improving the internal potential of the drain region, improving the output current of the device, and further inhibiting the short channel effect of the NC-FinFET, and improving the performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of FinFET (Fin Field-Effect Transistor) in novel semiconductor information devices, and specifically relates to a method for suppressing the output current loss of a negative capacitance FinFET (NC-FinFET) caused by the increase in the threshold voltage of the device due to the negative capacitance effect by using extended region Gaussian light doping technology. Background Technology

[0002] With the widespread application of technologies such as mobile internet, cloud computing, and artificial intelligence, the demand for higher performance and lower power consumption CMOS technology is constantly increasing. However, traditional metal-oxide-semiconductor transistors (MOSFETs) face problems such as a sharp increase in thermal effects and tunneling effects, and their speed and power consumption performance are approaching physical limits. In recent years, with the development of nanomaterials and two-dimensional materials, scientists have discovered ferroelectric materials with negative capacitance effects. When these ferroelectric materials are stacked on the gate of a traditional MOSFET, a new type of transistor, namely the negative capacitance field-effect transistor (NCFET), can be obtained.

[0003] Research shows that due to the negative capacitance effect, NCFETs can effectively improve the switching speed and current gain of transistors while reducing device power consumption. Currently, advanced FinFETs utilize a three-dimensional triple-gate structure to improve switching performance and reduce leakage power. Combining the NCFET structure with FinFET technology to create the negative capacitance fin field-effect transistor (NC-FinFET) is expected to further improve device performance and extend Moore's Law. NC-FinFETs have proven to possess both low power consumption and high performance, and are particularly promising for applications in the Industrial Internet of Things (IIoT) and wearable electronic devices.

[0004] However, similar to other NCFETs, NC-FinFETs also suffer from a decrease in output current due to a rise in threshold voltage. This current loss can severely impair device performance and have a very negative impact on device and circuit design. Therefore, finding effective methods to solve this problem is crucial.

[0005] Existing technologies show that practical processes employ lightly doped drain (LDD) and sidewall techniques to address the short-channel effect of FinFETs. The extended region of a FinFET refers to the area on both sides of the fin structure, also known as the source / drain extension region. This region aims to isolate the source / drain from the gate, thereby controlling the transistor's electrical characteristics; thus, the short-channel effect of FinFETs is well controlled. However, with the introduction of ferroelectric gate materials into NC-FinFETs, although the internal gate voltage amplification improves transistor performance, the negative capacitance effect also causes some unique phenomena. For example, the threshold voltage increases, leading to a higher voltage required for the transistor to turn on, resulting in decreased switching performance. Simultaneously, at lower gate voltages, as the drain voltage increases, the drain output current no longer tends to saturate but instead shows a decreasing trend. This phenomenon is called the negative differential resistance (NDR) effect of NC-FinFETs, which is also unique to NCFETs. This effect stems from the fact that a higher drain voltage is coupled to the gate voltage through the gate-drain capacitance, thereby reducing the internal potential inside the drain and resulting in output current loss of the device. Summary of the Invention

[0006] To address the issues of excessive threshold voltage and current loss in NC-FinFETs under high drain bias voltages, this invention proposes a method to compensate for the decrease in gate potential near the drain side of the NC-FinFET by reducing the gate-drain coupling capacitance. This reduces the threshold voltage required for device turn-on, thereby increasing the output current of the device under high drain bias voltages. Furthermore, this method is compatible with traditional NC-FinFET processes, requiring only changes to some doping steps and techniques, with virtually no change in cost.

[0007] The specific technical solution of this invention is as follows:

[0008] By changing the doping process of the source / drain extension regions of NC-FinFET and replacing the conventional uniform doping process with a Gaussian light doping process, the gate-drain coupling capacitance is reduced, the internal potential of the drain region is increased, the device output current is improved, and the short-channel effect of NC-FinFET can be further suppressed, thereby improving device performance.

[0009] Preferably, the source / drain extension regions are globally lightly Gaussian-doped, so that the entire extension region of the NC-FinFET is within the range of light Gaussian doping.

[0010] Preferably, the highest doping concentration is set at the source / drain extension region furthest from the channel, and the doping concentration is gradually reduced towards the channel region until it contacts the channel.

[0011] Preferably, the highest doping concentration of the Gaussian light doping is not higher than the uniform doping concentration at the source / drain end, and the lowest doping concentration is not lower than the uniform doping concentration of the channel.

[0012] The beneficial effects of this invention are:

[0013] This invention reduces the gate-drain coupling capacitance and increases the interfacial electric field between the gate and the substrate by changing the uniform doping process of the source / drain extension regions to a global Gaussian light doping process. This achieves the effect of compensating for the internal potential inside the drain by coupling to the gate voltage through the gate-drain capacitance under high drain bias voltage. Since the increase in the channel surface potential lowers the barrier between the channel and the source, making it easier for electrons to pass through, the threshold voltage required for the NC-FinFET to turn on decreases, thereby suppressing the decrease in output current. It also overcomes the defect of increased threshold voltage due to the negative capacitance effect, further improving the switching performance of the NC-FinFET.

[0014] Overall, this invention overcomes the current loss and threshold voltage rise caused by the inherent negative differential resistance effect of NC-FinFETs, thereby improving the overall performance of the device. Furthermore, this method is highly compatible with traditional NC-FinFET manufacturing processes without significantly increasing process complexity or manufacturing costs. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of an N-type negative capacitance fin field-effect transistor (NC-FinFET).

[0016] Figure 2 A schematic diagram of the Gaussian light doping process for the extended region. Detailed Implementation

[0017] The main principle of this invention is as follows: Due to the negative capacitance effect of ferroelectric materials coupled with the drain voltage, a negative gate charge is induced in the edge field inside the channel, leading to an increase in the channel barrier height and making it difficult for electrons to transition. Compared to FinFETs, NC-FinFETs have a higher threshold voltage. However, performing a Gaussian light doping process in the source / drain extension region can reduce the gate-drain coupling capacitance, thereby increasing the channel potential and lowering the barrier height between the source and the channel. This reduces the threshold voltage required for device turn-on and improves the switching performance of the device. Furthermore, the device current loss caused by the drain voltage coupled to the internal gate voltage through the gate-drain capacitance is a unique NDR phenomenon of NC-FinFETs.

[0018] This embodiment demonstrates... Figure 1The NC-FinFET shown here uses a modified doping process in its source / drain extension regions, replacing conventional uniform doping with light Gaussian doping, which reduces the gate-drain coupling capacitance. This results in a higher drain voltage coupled to the gate voltage, reducing internal potential loss on the drain side. The increased channel potential lowers the barrier height between the source and the channel, allowing electrons to pass through more easily. Consequently, the threshold voltage required for transistor turn-on is lowered, suppressing the decrease in drain current, i.e., suppressing the NDR effect, and thus reducing output current loss.

[0019] The specific technical solution of this embodiment can be found in [link to embodiment]. Figure 2 The transistor structure includes: a channel region, a gate oxide layer, a gate ferroelectric layer, a gate metal layer, a substrate, a source, a drain, a source extension region, and a drain extension region.

[0020] The substrate has a bulk silicon structure, and the material is an intrinsic silicon semiconductor doped with boron to form a P-type substrate. The gate oxide layer is a high-k material, HfO2. The gate ferroelectric layer is a doped hafnium-based oxide, Zr-HfO2. The gate metal layer is titanium nitride (Ti). i The source / drain material is polycrystalline silicon doped with phosphorus to form an N-type dopant. The source / drain extension region material is polycrystalline silicon doped with phosphorus to form an N-type dopant.

[0021] The specific process conditions are shown in another embodiment as follows:

[0022] The main process steps of traditional NC-FinFET are as follows:

[0023] 1. SOI substrate preparation: First, prepare a thin-film silicon substrate by forming a silicon oxide (SiO2) film on its surface, and then deposit a silicon film with a thickness of tens to hundreds of nanometers on the silicon oxide.

[0024] 2. Fin Formation: The shape of the Fin is defined on the surface of the silicon layer using photolithography, and then the silicon layer is etched into the shape of the Fin using dry etching technology.

[0025] 3. Doping: Each Fin and the surrounding area are doped using an ion implanter to make the Fin a P-type or N-type material. The doping concentration is controlled within different ranges according to requirements.

[0026] 4. Silicon epitaxial growth: On the doped silicon surface, a tiny source and drain region of a silicon transistor is grown using techniques such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). This process is called epitaxial growth.

[0027] 5. Metal gate fabrication: A metal T layer is deposited on the silicon layer surface around Fin and in the source / drain regions. i N.

[0028] 6. Connection: A silicon dioxide (SiO2) thin film is deposited on the transistor, and then the gate is exposed using photolithography. Metal contacts are formed on the source and drain regions, and finally a FinFET transistor is formed.

[0029] This embodiment modifies one doping process step, changing the original source / drain N-type uniform doping to an N-type Gaussian light doping process in the extended region after Fin formation. It can be seen that this manufacturing process is compatible with the traditional NC-FinFET manufacturing process, requiring no addition or reduction of manufacturing steps, only a certain process adjustment in the doping stage. The specific doping implantation details are as follows:

[0030] The source / drain extension region near the channel has the lowest implanted ion concentration, while the region further away from the channel has the highest. However, the highest ion concentration here cannot exceed the implanted ion concentration at the source / drain, and the lowest ion concentration cannot be lower than the implanted ion concentration at the channel. The ion concentration exhibits a Gaussian decreasing distribution from top to bottom (with the peak value at the top). Simultaneously, the ion implantation depth of the entire source / drain extension region cannot exceed the height of the extension region, and the ion implantation width cannot exceed the length of the source / drain extension region. In other words, the entire Gaussian ion implantation cannot exceed the entire range of the source / drain extension region.

[0031] In summary, the Gaussian light doping process in the source / drain extension region proposed in this embodiment reduces the gate-drain coupling capacitance, compensates for some of the channel internal potential losses, and thus increases the channel output current, naturally suppressing the NDR phenomenon. This makes NC-FinFET a strong competitor for ultra-low power devices in the post-Moore era.

[0032] Those skilled in the art should recognize that the above implementation steps and solutions are only used to illustrate and explain the present invention, and are not intended to limit the present invention. Any changes or modifications to the above implementation steps and solutions that are within the scope of the present invention will fall within the protection scope of the present invention.

Claims

1. A method for suppressing output current loss in a negative capacitance finned transistor, characterized in that: The doping process of the source / drain extension region of NC-FinFET is changed, and Gaussian light doping technology is used instead of conventional uniform doping technology to reduce the gate-drain coupling capacitance and increase the internal potential of the drain region. The source / drain extension regions are globally lightly Gaussian-doped, so that the entire extension region of the NC-FinFET is within the range of light Gaussian doping.

2. The method according to claim 1, characterized in that: The highest doping concentration is set at the source / drain extension region furthest from the channel, and the doping concentration is gradually reduced towards the channel region until it contacts the channel.

3. The method according to claim 2, characterized in that: The highest doping concentration of Gaussian light doping is not higher than the uniform doping concentration at the source / drain, and the lowest doping concentration is not lower than the uniform doping concentration at the channel.

Images