A field-effect transistor with three-valued logic behavior

Abstract

The present invention discloses a field effect transistor with three-valued logic behavior, comprising a source region, a channel region, a drain region, a gate dielectric layer, a substrate layer, a gate oxide induction layer, a metal layer and a spacer layer. The channel region is an undoped channel region, the drain region is an undoped drain region, the metal layer comprises a first metal block, a second metal block and a third metal block arranged in a spaced order from left to right, the spacing between the first metal block and the second metal block is 12nm, and the spacing between the second metal block and the third metal block is 10nm. The first metal block is the main control gate of the field effect transistor, the second metal block and the third metal block serve as two induction gates of the field effect transistor, and the spacer layer is used to isolate the first metal block from the second metal block and the third metal block. The advantage is that when constructing a multi-valued logic unit, no additional passive devices need to be introduced, and the multi-valued logic unit is insensitive to doping fluctuations and process fluctuations, thereby improving the performance stability of the multi-valued logic unit.

Description

Technical Field

[0001] The present invention relates to a field effect transistor, in particular to a field effect transistor with three-valued logic behavior. Background Art

[0002] The use of multi-valued logic technology can transmit more information on a given data path and store more information in the same storage space. Therefore, multi-valued logic technology can overcome the power consumption problem caused by the surge in information density from the perspective of circuit architecture. The use of three-valued logic in integrated circuit design has many advantages over traditional binary Boolean logic. For example, due to the higher expressive power of three-valued logic, the circuit system based on three-valued logic can reduce the number of transistors in the chip and have shorter and simpler interconnects. Currently, the common way to implement three-valued logic behavior is to use multi-threshold transistor technology, but using this technology to build three-valued logic circuit units often requires additional off-chip resistors or 0.5V. DD Voltage sources also require more transistors. The industry has also leveraged the negative differential resistance or transconductance characteristics of emerging semiconductor materials to implement three-valued logic transistors, but these also face issues such as electrical characteristic hysteresis and non-full-swing outputs. All of the aforementioned approaches achieve three-valued logic behavior by introducing additional passive components on top of transistors. However, the problems caused by these additional passive components essentially negate the advantages of three-valued logic technology.

[0003] Currently, a CMOS with three-valued logic behavior (Ternary-CMOS: T-CMOS) is achieved by applying an additional heavy doping process to the substrate of conventional CMOS or GAA CMOS. T-CMOS introduces a carrier-to-band tunneling conduction mechanism through the PN junction formed by the highly doped substrate / drain region, utilizing the leakage current of the T-CMOS substrate to form a third output level. Using T-CMOS to construct multi-valued logic cells eliminates the need for additional passive components, thus avoiding the problems caused by the introduction of additional passive components. However, constructing multi-valued logic cells using T-CMOS requires perfect matching of the current characteristics of the N-type T-CMOS and P-type T-CMOS, particularly the inter-band tunneling current responsible for forming the third output level. This leakage current, acting as a highly sensitive substrate doping fluctuation and drain voltage, can lead to fluctuations in the T-CMOS threshold, resulting in mismatches between the current characteristics of the N-type T-CMOS and P-type T-CMOS, and degradation of the noise margin of the third output voltage, leading to unstable performance of the constructed multi-valued logic cells.

[0004] Therefore, the present invention proposes a field effect transistor having a three-valued logic behavior that is insensitive to doping fluctuations and process fluctuations and does not require additional passive devices. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a field effect transistor with three-valued logic behavior that does not require the introduction of additional passive devices when constructing a multi-valued logic unit, is insensitive to doping fluctuations and process fluctuations, and can improve the performance stability of the multi-valued logic unit.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a field effect transistor with three-valued logic behavior, including a main structure, a gate dielectric layer and a substrate layer, the main structure including a source region, a channel region and a drain region distributed from left to right on the substrate and connected in sequence, the channel region is an undoped channel region, which is implemented by indium arsenide (InAs) material, the drain region is an undoped drain region, which is implemented by indium aluminum arsenide (InAlAs) material, the gate dielectric layer is stacked above the source region and extends above the channel region, the field effect transistor also includes a gate oxide induction layer, a metal layer and a spacer layer, the gate oxide induction layer is stacked above the drain region, extends above the channel region and is connected to the gate dielectric layer, the metal layer includes a first metal block, a second metal block and a third metal block arranged in sequence from left to right, the first metal block is stacked above the gate dielectric layer, the second metal block is stacked above the gate oxide induction layer, and the third metal block is stacked above the gate oxide induction layer. Three metal blocks are stacked above the gate oxide induction layer. The spacing between the first metal block and the second metal block is 12nm, and the spacing between the second metal block and the third metal block is 10nm. The first metal block is the main control gate of the field effect transistor, and the second metal block and the third metal block serve as two induction gates of the field effect transistor. The first metal block is used to access the gate voltage. The second metal block and the third metal block are used to generate a tunneling junction at the interface between the channel region and the drain region on the one hand, and to achieve electrostatic doping of the channel region and the drain region under the induction of the gate oxide induction layer on the other hand, so that the channel region and the drain region do not need chemical doping. The spacer layer is used to isolate the first metal block from the second metal block and the third metal block to prevent the gate voltage accessed by the first metal block from interfering with the second metal block and the third metal block.

[0007] When the field effect transistor is an N-type device, the gate work function of the first metal block is 5.57eV, the gate work function of the second metal block is 4.60eV, and the gate work function of the third metal block is 4.34eV. When the field effect transistor is a P-type device, the gate work function of the first metal block is 4.47eV, the gate work function of the second metal block is 4.40eV, and the gate work function of the third metal block is 5.90eV.

[0008] The material of the source region is NiAl, the material of the substrate layer is sapphire, the material of the spacer layer is silicon nitride, the material of the gate oxide induction layer is silicon dioxide, the material of the gate dielectric layer is aluminum oxide, and the materials of the first metal block, the second metal block and the third metal block are polysilicon.

[0009] The source region, the channel region and the drain region are all rectangular parallelepiped structures, the length directions of the source region, the channel region and the drain region are all along the left-right direction, the width directions are all along the front-back direction, and the thickness directions are all along the up-down direction. The front ends of the source region, the channel region and the drain region are located in the same plane, the rear ends of the source region, the channel region and the drain region are located in the same plane, the upper ends of the source region, the channel region and the drain region are located in the same plane, the lower ends of the source region, the channel region and the drain region are located in the same plane, and the right end face of the source region is fixedly connected to the left end face of the channel region. The right end face of the channel region is fixedly connected to the left end face of the drain region and is in a fitted state; the substrate layer is a rectangular parallelepiped structure, and the substrate layer is stacked below the source region, the channel region and the drain region. The front end face of the substrate layer is located in front of the plane where the front end face of the source region is located, and the rear end face of the substrate layer is located on the rear side of the plane where the rear end face of the source region is located. The left end face of the substrate layer is located on the left side of the plane where the left end face of the source region is located, and the right end face of the substrate layer is located on the right side of the plane where the right end face of the drain region is located. The upper end face of the substrate layer is respectively connected to the source region, the The channel region and the lower end face of the drain region are fixedly connected; the gate dielectric layer is a rectangular parallelepiped structure, the left end face of the gate dielectric layer and the left end face of the source region are located in the same plane, the front end face of the gate dielectric layer and the front end face of the source region are located in the same plane, the rear end face of the gate dielectric layer and the rear end face of the source region are located in the same plane, the right end face of the gate dielectric layer is located between the plane where the left end face of the channel region and the plane where the right end face of the channel region are located, and the lower end face of the gate dielectric layer is fixedly connected to the upper end face of the source region and the upper end face of the channel region respectively; the gate oxide induction layer is a rectangular parallelepiped structure, the gate oxide induction layer The front end surface of the conductive layer and the front end surface of the gate dielectric layer are located in the same plane, the rear end surface of the gate oxide inducing layer and the rear end surface of the gate dielectric layer are located in the same plane, the upper end surface of the gate oxide inducing layer and the upper end surface of the gate dielectric layer are located in the same plane, the lower end surface of the gate oxide inducing layer and the lower end surface of the gate dielectric layer are located in the same plane, the right end surface of the gate oxide inducing layer and the right end surface of the drain region are located in the same plane, the lower end surface of the gate oxide inducing layer is fixedly connected to the upper end surface of the drain region and the upper end surface of the channel region respectively, and the left end surface of the gate oxide inducing layer is fixedly connected to the right end surface of the gate dielectric layer and is in a bonded state;The first metal block, the second metal block and the third metal block are all rectangular parallelepiped structures. The left end face of the first metal block and the left end face of the gate dielectric layer are located in the same plane, the right end face of the first metal block and the right end face of the gate dielectric layer are located in the same plane, the front end face of the first metal block and the front end face of the gate dielectric layer are located in the same plane, the rear end face of the first metal block and the rear end face of the gate dielectric layer are located in the same plane, the lower end face of the first metal block is fixedly connected to the upper end face of the gate dielectric layer, the front end face of the second metal block and the front end face of the first metal block are located in the same plane, the rear end face of the second metal block and the rear end face of the first metal block are located in the same plane, and the upper end face of the second metal block and the upper end face of the first metal block are located in the same plane. The lower end surface of the second metal block is coplanar with the lower end surface of the first metal block, the lower end surface of the second metal block is fixedly connected to the upper end surface of the gate oxide induction layer, the front end surface of the third metal block is coplanar with the front end surface of the first metal block, the rear end surface of the third metal block is coplanar with the rear end surface of the first metal block, the upper end surface of the third metal block is coplanar with the upper end surface of the first metal block, the lower end surface of the third metal block is coplanar with the lower end surface of the first metal block, the lower end surface of the third metal block is fixedly connected to the upper end surface of the gate oxide induction layer, the left end surface of the third metal block is coplanar with the left end surface of the drain region, and the right end surface of the third metal block is coplanar with the right end surface of the drain region.

[0010] The spacing layer includes an integrally formed first spacing block, a second spacing block and a third spacing block, the second spacing block and the third spacing block are spaced apart from each other on the left and right sides, the second spacing block is located on the left side of the third spacing block, the first spacing block is stacked above the second spacing block and the third spacing block, the front end faces of the first spacing block, the second spacing block and the third spacing block are located in the same plane, the rear end faces of the first spacing block, the second spacing block and the third spacing block are located in the same plane, the lower end faces of the second spacing block and the third spacing block are located in the same plane, the left end face of the first spacing block layer is located to the left of the plane where the left end face of the second spacing block is located or is flush with the left end face of the second spacing block, the right end face of the first spacing block layer is located to the right of the plane where the right end face of the third spacing block is located or is flush with the third spacing block The right end surface of the second spacer block is flush with the upper and lower surfaces, the second spacer block is embedded between the first metal block and the second metal block, the left end surface of the second spacer block is in contact with the right end surface of the first metal block, the right end surface of the second spacer block is in contact with the left end surface of the second metal block, the lower end surface of the second spacer block and the lower end surface of the second metal block are located in the same plane, the upper end surface of the second spacer block and the upper end surface of the second metal block are located in the same plane, the front end surface of the second spacer block and the front end surface of the second metal block are located in the same plane, the rear end surface of the second spacer block and the rear end surface of the second metal block are located in the same plane, the third spacer block is embedded between the second metal block and the third metal block, the left end surface of the third spacer block is in contact with the right end surface of the second metal block, and the right end surface of the third spacer block is in contact with the left end surface of the third metal block.

[0011] The source region has a length of 20 nm and a width of 500 nm, the channel region has a length of 50 nm and a width of 500 nm, and the drain region has a length of 20 nm and a width of 500 nm; the gate dielectric layer has a length of 28 nm in the left-right direction and a thickness of 3 nm in the top-bottom direction, and the distance between the right end surface of the gate dielectric layer and the plane where the left end surface of the channel region is located is 8 nm; the gate oxide induction layer has a length of 62 nm in the left-right direction and a thickness of 3 nm in the top-bottom direction; the first metal block has a length of 28 nm in the left-right direction and a thickness of 5 nm in the top-bottom direction, and the second metal block and the third metal block have a length of 20 nm in the left-right direction and a thickness of 5 nm in the top-bottom direction.

[0012] Compared with the prior art, the advantage of the present invention is that the intrinsic doping of the channel region and the N+ electrostatic doping of the drain region can be induced by the second metal block, the third metal block and the gate oxide induction layer, so that the channel region and the drain region of the field effect transistor with three-valued logic behavior of the present invention do not need ion doping, the channel region adopts an undoped channel region, and the drain region adopts an undoped drain region, which alleviates the influence of the ion doping fluctuation of the doped channel region and the doped drain region on the inter-band tunneling current in the traditional device, reduces the risk of current mismatch between the N-type device and the P-type device implemented by the field effect transistor with three-valued logic behavior of the present invention, and improves the stability of the three-valued logic unit. At the same time, the second metal block and the third metal block do not need to be connected to any input bias and passive devices (resistors, inductors or capacitors, etc.). The three-valued logic behavior is realized, so no additional passive devices are required when constructing a three-valued logic unit (such as a three-valued inverter). The spacing between the second metal block and the third metal block can provide a sufficient tunneling distance for the N-type device and the P-type device implemented by the field-effect transistor with three-valued logic behavior of the present invention, thereby releasing the process limitation of the spacing between the second metal block and the third metal block. In addition, the first metal block extends from the source region to above the channel region, and its left-right dimension is larger than the left-right dimension of the source region, which can realize a sufficiently large on-current component, making it much larger than the tunneling current, thereby ensuring product performance. Therefore, when constructing a multi-valued logic unit, the present invention does not require the introduction of additional passive devices, is insensitive to doping fluctuations and process fluctuations, and can improve the performance stability of the multi-valued logic unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A front view of a field effect transistor having three-valued logic behavior according to the present invention;

[0014] Figure 2 A simulation diagram of current characteristics of the field effect transistor with three-valued logic behavior of the present invention when implementing an N-type device and a P-type device;

[0015] Figure 3 This is a diagram showing the structure and voltage transfer characteristics of a three-valued inverter implemented by a field effect transistor with three-valued logic behavior according to the present invention. DETAILED DESCRIPTION

[0016] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0017] Example 1: Figure 1As shown, a field effect transistor with three-valued logic behavior includes a main structure, a gate dielectric layer 1 and a substrate layer 2. The main structure includes a source region 3, a channel region 4 and a drain region 5 distributed on the substrate from left to right and connected in sequence. The channel region 4 is an undoped channel region 4 and is implemented using indium arsenide (InAs) material. The drain region 5 is an undoped drain region 5 and is implemented using indium aluminum arsenide (InAlAs) material. The gate dielectric layer 1 is stacked above the source region 3 and extends above the channel region 4. The field effect transistor also includes a gate oxide induction layer 6, a metal layer and a spacer layer. The gate oxide induction layer 6 is stacked above the drain region 5 and extends above the channel region 4 to connect to the gate dielectric layer 1. The metal layer includes a first metal block 7, a second metal block 8 and a third metal block 9 arranged in sequence from left to right. The first metal block 7 is stacked above the gate dielectric layer 1, and the second metal block 8 is stacked on the gate oxide induction layer 6. Above, the third metal block 9 is stacked above the gate oxide induction layer 6. The spacing between the first metal block 7 and the second metal block 8 is 12nm, and the spacing between the second metal block 8 and the third metal block 9 is 10nm. The first metal block 7 is the main control gate of the field effect transistor, and the second metal block 8 and the third metal block 9 serve as two induction gates of the field effect transistor. The first metal block 7 is used to access the gate voltage. The second metal block 8 and the third metal block 9 are used to generate a tunnel junction at the connection interface between the channel region 4 and the drain region 5 on the one hand, and to realize electrostatic doping of the channel region 4 and the drain region 5 under the induction of the gate oxide induction layer 6 on the other hand, so that the channel region 4 and the drain region 5 do not need chemical doping. The spacer layer is used to isolate the first metal block 7 from the second metal block 8 and the third metal block 9 to prevent the gate voltage accessed by the first metal block 7 from interfering with the second metal block 8 and the third metal block 9.

[0018] In this embodiment, the gate work function of the first metal block 7 is 5.57 eV, the gate work function of the second metal block 8 is 4.60 eV, the gate work function of the third metal block 9 is 4.34 eV, and the field effect transistor is an N-type field effect transistor.

[0019] In this embodiment, the material of the source region 3 is NiAl alloy, the material of the substrate layer 2 is sapphire material, the material of the spacer layer is silicon nitride, the material of the gate oxide induction layer 6 is silicon dioxide, the material of the gate dielectric layer 1 is aluminum oxide, and the material of the first metal block 7, the second metal block 8 and the third metal block 9 is polycrystalline silicon.

[0020] In this embodiment, the source region 3, the channel region 4 and the drain region 5 are all rectangular parallelepiped structures. The length directions of the source region 3, the channel region 4 and the drain region 5 are all along the left-right direction, the width directions are all along the front-back direction, and the thickness directions are all along the up-down direction. The front ends of the source region 3, the channel region 4 and the drain region 5 are located in the same plane, the rear ends of the source region 3, the channel region 4 and the drain region 5 are located in the same plane, the upper ends of the source region 3, the channel region 4 and the drain region 5 are located in the same plane, the lower ends of the source region 3, the channel region 4 and the drain region 5 are located in the same plane, and the right end face of the source region 3 is fixedly connected to the left end face of the channel region 4. The right end face of the channel region 4 is fixedly connected to the left end face of the drain region 5 and is in a fitted state; the substrate layer 2 is a rectangular parallelepiped structure, and the substrate layer 2 is stacked below the source region 3, the channel region 4 and the drain region 5. The front end face of the substrate layer 2 is located in front of the plane where the front end face of the source region 3 is located, and the rear end face of the substrate layer 2 is located on the rear side of the plane where the rear end face of the source region 3 is located. The left end face of the substrate layer 2 is located on the left side of the plane where the left end face of the source region 3 is located, and the right end face of the substrate layer 2 is located on the right side of the plane where the right end face of the drain region 5 is located. The upper end face of the substrate layer 2 is respectively connected to the source region 3, the channel region 4 and The lower end face of the drain region 5 is fixedly connected; the gate dielectric layer 1 is a rectangular parallelepiped structure, the left end face of the gate dielectric layer 1 and the left end face of the source region 3 are located in the same plane, the front end face of the gate dielectric layer 1 and the front end face of the source region 3 are located in the same plane, the rear end face of the gate dielectric layer 1 and the rear end face of the source region 3 are located in the same plane, the right end face of the gate dielectric layer 1 is located between the plane where the left end face of the channel region 4 is located and the plane where the right end face of the channel region 4 is located, and the lower end face of the gate dielectric layer 1 is fixedly connected to the upper end face of the source region 3 and the upper end face of the channel region 4 respectively; the gate oxide induction layer 6 is a rectangular parallelepiped structure, the front end face of the gate oxide induction layer 6 The end face is located in the same plane as the front face of the gate dielectric layer 1, the rear face of the gate oxide inducing layer 6 is located in the same plane as the rear face of the gate dielectric layer 1, the upper end face of the gate oxide inducing layer 6 is located in the same plane as the upper end face of the gate dielectric layer 1, the lower end face of the gate oxide inducing layer 6 is located in the same plane as the lower end face of the gate dielectric layer 1, the right end face of the gate oxide inducing layer 6 is located in the same plane as the right end face of the drain region 5, the lower end face of the gate oxide inducing layer 6 is fixedly connected to the upper end face of the drain region 5 and the upper end face of the channel region 4, respectively, and the left end face of the gate oxide inducing layer 6 is fixedly connected to the right end face of the gate dielectric layer 1 and is in a bonded state;The first metal block 7, the second metal block 8 and the third metal block 9 are all rectangular parallelepiped structures. The left end face of the first metal block 7 is in the same plane as the left end face of the gate dielectric layer 1, the right end face of the first metal block 7 is in the same plane as the right end face of the gate dielectric layer 1, the front end face of the first metal block 7 is in the same plane as the front end face of the gate dielectric layer 1, the rear end face of the first metal block 7 is in the same plane as the rear end face of the gate dielectric layer 1, the lower end face of the first metal block 7 is fixedly connected to the upper end face of the gate dielectric layer 1, the front end face of the second metal block 8 is in the same plane as the front end face of the first metal block 7, the rear end face of the second metal block 8 is in the same plane as the rear end face of the first metal block 7, and the upper end face of the second metal block 8 is in the same plane as the upper end face of the first metal block 7. The lower end surface of the second metal block 8 is coplanar with the lower end surface of the first metal block 7, the lower end surface of the second metal block 8 is fixedly connected to the upper end surface of the gate oxide induction layer 6, the front end surface of the third metal block 9 is coplanar with the front end surface of the first metal block 7, the rear end surface of the third metal block 9 is coplanar with the rear end surface of the first metal block 7, the upper end surface of the third metal block 9 is coplanar with the upper end surface of the first metal block 7, the lower end surface of the third metal block 9 is coplanar with the lower end surface of the first metal block 7, the lower end surface of the third metal block 9 is fixedly connected to the upper end surface of the gate oxide induction layer 6, the left end surface of the third metal block 9 is coplanar with the left end surface of the drain region 5, and the right end surface of the third metal block 9 is coplanar with the right end surface of the drain region 5.

[0021] In this embodiment, the spacing layer includes an integrally formed first spacing block 10, a second spacing block 11 and a third spacing block 12, the second spacing block 11 and the third spacing block 12 are spaced apart from each other on the left and right sides, the second spacing block 11 is located on the left side of the third spacing block 12, the first spacing block 10 is stacked above the second spacing block 11 and the third spacing block 12, the front end faces of the first spacing block 10, the second spacing block 11 and the third spacing block 12 are located in the same plane, the rear end faces of the first spacing block 10, the second spacing block 11 and the third spacing block 12 are located in the same plane, the lower end faces of the second spacing block 11 and the third spacing block 12 are located in the same plane, the left end face of the first spacing block 10 layer is located on the left side of the plane where the left end face of the second spacing block 11 is located or is flush with the left end face of the second spacing block 11, and the right end face of the first spacing block 10 layer is located on the right side of the plane where the right end face of the third spacing block 12 is located. The side or is flush with the right end face of the third spacer block 12, the second spacer block 11 is embedded between the first metal block 7 and the second metal block 8, the left end face of the second spacer block 11 is in contact with the right end face of the first metal block 7, the right end face of the second spacer block 11 is in contact with the left end face of the second metal block 8, the lower end face of the second spacer block 11 and the lower end face of the second metal block 8 are located in the same plane, the upper end face of the second spacer block 11 and the upper end face of the second metal block 8 are located in the same plane, the front end face of the second spacer block 11 and the front end face of the second metal block 8 are located in the same plane, the rear end face of the second spacer block 11 and the rear end face of the second metal block 8 are located in the same plane, the third spacer block 12 is embedded between the second metal block 8 and the third metal block 9, the left end face of the third spacer block 12 is in contact with the right end face of the second metal block 8, and the right end face of the third spacer block 12 is in contact with the left end face of the third metal block 9.

[0022] In this embodiment, the source region 3 has a length of 20 nm and a width of 500 nm, the channel region 4 has a length of 50 nm and a width of 500 nm, and the drain region 5 has a length of 20 nm and a width of 500 nm; the gate dielectric layer 1 has a length of 28 nm in the left-right direction and a thickness of 3 nm in the top-bottom direction, and the distance between the right end surface of the gate dielectric layer 1 and the plane where the left end surface of the channel region 4 is located is 8 nm; the gate oxide induction layer 6 has a length of 62 nm in the left-right direction and a thickness of 3 nm in the top-bottom direction; the first metal block 7 has a length of 28 nm in the left-right direction and a thickness of 5 nm in the top-bottom direction; the second metal block 8 and the third metal block 9 have a length of 20 nm in the left-right direction and a thickness of 5 nm in the top-bottom direction.

[0023] In the N-type field effect transistor of Example 1 and the P-type field effect transistor of Example 2, due to the effects of the second metal block 8, the third metal block 9 and the gate oxide induction layer 6, the channel region 4 is intrinsically doped and the drain region 5 is N+ doped. In this case, a tunnel junction is formed at the connection interface between the channel region 4 and the drain region 5 to generate a tunneling current. Since the second metal block 8 and the third metal block 9 are spaced apart and are not connected, and there is no need to connect any bias or passive devices, the first metal block 7 and the second metal block 8 have an isolation layer as an isolation material. Therefore, the gate voltage connected to the first metal block 7 is around half of the power supply voltage connected to the N-type field effect transistor or the P-type field effect transistor. A tunneling current that is not related to the gate voltage can be generated at the connection interface between the channel region 4 and the drain region 5, and at the same time, The 10nm spacing set between the second metal block 8 and the third metal block 9 can provide a wide tunneling distance for the N-type field effect transistor and the P-type field effect transistor, thereby releasing the process limitation of the spacing between the second metal block 8 and the third metal 9. The source region 3 is made of metal instead of semiconductor material, so the Schottky barrier at the connection interface between the source region 3 and the channel region 4 can be modulated by the gate voltage and a Schottky tunneling current can be generated. Since the length of the first metal block 7 along the left and right directions is greater than the length of the source region 3 along the left and right directions, a Schottky tunneling current greater than the tunneling current can be achieved. The N-type field effect transistor of Example 1 and the P-type field effect transistor of Example 2 have opposite polarities but the same principle, and both have better symmetry. When the gate voltage is equal to about half the power supply voltage, since the currents of the N-type field effect transistor and the P-type field effect transistor are equal, the equivalent resistances of the two are also equal, and they have good current matching.

[0024] The N-type field effect transistor and the P-type field effect transistor with three-valued logic behavior of the present invention are simulated in the Slivaco TCAD three-dimensional simulation environment. In the simulation, the drain voltage of the N-type field effect transistor is fixed at 0.55V and 1.1V respectively, the drain voltage of the P-type field effect transistor is fixed at 0.55V and 0V respectively, the source of the N-type field effect transistor is grounded at 0V, and the source of the P-type field effect transistor is connected to the power supply at 1.1V. The voltage of the first metal block 7 of the N-type field effect transistor and the P-type field effect transistor is scanned, and the scanning voltage is increased from 0V to 1.1V. The current characteristic simulation diagram of the N-type field effect transistor and the P-type field effect transistor is shown in FIG. Figure 2 As shown, analysis Figure 2It can be seen that the N-type field effect transistor and the P-type field effect transistor have symmetrical transfer characteristic curves. When the drain voltage of the N-type field effect transistor and the P-type field effect transistor is equal to half the power supply voltage (0.55V), the drain current of the N-type field effect transistor and the P-type field effect transistor is equal. At this time, the current characteristic curves of the two overlap in part, and the equivalent resistance of the N-type field effect transistor and the P-type field effect transistor is also equal. The increase in the drain voltage of the N-type field effect transistor and the decrease in the drain voltage of the P-type field effect transistor have little effect on the current of the overlapping part. If the power supply voltage is divided equally by using these two N-type field effect transistors and P-type field effect transistors with equal equivalent resistance, an output voltage of 0.55V (i.e., the third output level) can be achieved.

[0025] To verify the performance of the present invention, the Figure 3 The connection method of the N-type field effect transistor N1 and the P-type field effect transistor P1 in the present invention is obtained, and a three-value inverter circuit structure of the field effect transistor with three-value logic behavior based on the present invention is obtained, wherein the input port of the three-value inverter is the gate connection terminal of the N-type field effect transistor N1 and the P-type field effect transistor P1, the output port is the drain connection terminal of the N-type field effect transistor N1 and the P-type field effect transistor P1, the power supply is connected to the source of the P-type field effect transistor P1, the power supply voltage is input, and the ground is connected to the source of the N-type field effect transistor N1. Figure 3 The black solid curve in the middle describes the voltage transfer characteristics of the ternary inverter. Compared to the voltage transfer characteristics of ordinary binary inverters, the voltage transfer characteristics of the ternary inverter can output a stable intermediate voltage level around half the input power supply voltage. The detailed operating principle is as follows: When the power supply voltage of the ternary inverter transitions from 0V to 0.35V, as Figure 3As shown in region I, P-type field-effect transistor P1 is always in a fully on state, while N1 is in a half-on state. N-type field-effect transistor N1 is in a high-impedance state, and the power supply voltage is connected to the output port of the ternary inverter through P-type field-effect transistor P1, resulting in an output voltage of 1.1V at the output port of the ternary inverter. After the power supply voltage transitions to region II near 0.5VDD (VDD = 1.1V), due to the increase in power supply voltage, both N-type field-effect transistor N1 and P-type field-effect transistor P1 are in a half-on state. The drain currents of N-type field-effect transistor N1 and P-type field-effect transistor P1 dominate and the current magnitudes are matched. Therefore, the power supply voltage forms a voltage divider network through a high-resistance path, outputting a stable intermediate voltage level (0.55V). If the power supply voltage continues to rise to region III, N-type field-effect transistor N1 becomes fully on, and the ground line is connected to the output port of the ternary inverter through P-type field-effect transistor P1, causing the output voltage of the ternary inverter output port to drop to 0V. Therefore, it can be seen that the three-value inverter implemented based on the field effect transistor with three-value logic behavior of the present invention can output three logic levels (0V, 0.55V, 1.1V), and the output levels are stable.

Claims

1. A field effect transistor with three-valued logic behavior, comprising a main structure, a gate dielectric layer, and a substrate layer, wherein the main structure comprises a source region, a channel region, and a drain region distributed from left to right on the substrate and connected in sequence, characterized in that The material of the source region is NiAl, the channel region is an undoped channel region, which is implemented by indium arsenide (InAs) material, the drain region is an undoped drain region, which is implemented by indium aluminum arsenide (InAlAs) material, the gate dielectric layer is stacked above the source region and extends above the channel region, the field effect transistor further comprises a gate oxide induction layer, a metal layer and a spacer layer, the gate oxide induction layer is stacked above the drain region, and extends above the channel region to connect to the gate dielectric layer, the metal layer comprises a first metal block, a second metal block and a third metal block arranged in order from left to right, the first metal block is stacked above the gate dielectric layer, the second metal block is stacked above the gate oxide induction layer, the third metal block is stacked above the gate oxide induction layer, and the spacer between the first metal block and the second metal block is The spacing is 12nm, the spacing between the second metal block and the third metal block is 10nm, the first metal block is the main control gate of the field effect transistor, the second metal block and the third metal block serve as two induction gates of the field effect transistor, the first metal block is used to access the gate voltage, the second metal block and the third metal block are used to generate a tunnel junction at the connection interface between the channel region and the drain region on the one hand, and to realize electrostatic doping of the channel region and the drain region under the induction of the gate oxide induction layer on the other hand, so that the channel region and the drain region do not need chemical doping, and the spacer layer is used to isolate the first metal block from the second metal block and the third metal block to prevent the gate voltage accessed by the first metal block from interfering with the second metal block and the third metal block.

2. A field effect transistor with three-valued logic behavior according to claim 1, characterized in that When the field effect transistor is an N-type device, the gate work function of the first metal block is 5.57eV, the gate work function of the second metal block is 4.60eV, and the gate work function of the third metal block is 4.34eV. When the field effect transistor is a P-type device, the gate work function of the first metal block is 4.47eV, the gate work function of the second metal block is 4.40eV, and the gate work function of the third metal block is 5.90eV.

3. A field effect transistor with three-valued logic behavior according to claim 1, characterized in that The material of the substrate layer is sapphire, the material of the spacer layer is silicon nitride, the material of the gate oxide induction layer is silicon dioxide, the material of the gate dielectric layer is aluminum oxide, and the materials of the first metal block, the second metal block and the third metal block are polysilicon.

4. A field effect transistor with three-valued logic behavior according to claim 1, characterized in that The source region, the channel region and the drain region are all rectangular parallelepiped structures, the length directions of the source region, the channel region and the drain region are all along the left-right direction, the width directions are all along the front-back direction, and the thickness directions are all along the up-down direction. The front ends of the source region, the channel region and the drain region are located in the same plane, the rear ends of the source region, the channel region and the drain region are located in the same plane, the upper ends of the source region, the channel region and the drain region are located in the same plane, the lower ends of the source region, the channel region and the drain region are located in the same plane, and the right end face of the source region is fixedly connected to the left end face of the channel region. The right end face of the channel region is fixedly connected to the left end face of the drain region and is in a fitted state; the substrate layer is a rectangular parallelepiped structure, and the substrate layer is stacked below the source region, the channel region and the drain region. The front end face of the substrate layer is located in front of the plane where the front end face of the source region is located, and the rear end face of the substrate layer is located on the rear side of the plane where the rear end face of the source region is located. The left end face of the substrate layer is located on the left side of the plane where the left end face of the source region is located, and the right end face of the substrate layer is located on the right side of the plane where the right end face of the drain region is located. The upper end face of the substrate layer is respectively connected to the source region, the The channel region and the lower end face of the drain region are fixedly connected; the gate dielectric layer is a rectangular parallelepiped structure, the left end face of the gate dielectric layer and the left end face of the source region are located in the same plane, the front end face of the gate dielectric layer and the front end face of the source region are located in the same plane, the rear end face of the gate dielectric layer and the rear end face of the source region are located in the same plane, the right end face of the gate dielectric layer is located between the plane where the left end face of the channel region and the plane where the right end face of the channel region are located, and the lower end face of the gate dielectric layer is fixedly connected to the upper end face of the source region and the upper end face of the channel region respectively; the gate oxide induction layer is a rectangular parallelepiped structure, the gate oxide induction layer The front end surface of the conductive layer and the front end surface of the gate dielectric layer are located in the same plane, the rear end surface of the gate oxide inducing layer and the rear end surface of the gate dielectric layer are located in the same plane, the upper end surface of the gate oxide inducing layer and the upper end surface of the gate dielectric layer are located in the same plane, the lower end surface of the gate oxide inducing layer and the lower end surface of the gate dielectric layer are located in the same plane, the right end surface of the gate oxide inducing layer and the right end surface of the drain region are located in the same plane, the lower end surface of the gate oxide inducing layer is fixedly connected to the upper end surface of the drain region and the upper end surface of the channel region respectively, and the left end surface of the gate oxide inducing layer is fixedly connected to the right end surface of the gate dielectric layer and is in a bonded state;The first metal block, the second metal block and the third metal block are all rectangular parallelepiped structures. The left end face of the first metal block and the left end face of the gate dielectric layer are located in the same plane, the right end face of the first metal block and the right end face of the gate dielectric layer are located in the same plane, the front end face of the first metal block and the front end face of the gate dielectric layer are located in the same plane, the rear end face of the first metal block and the rear end face of the gate dielectric layer are located in the same plane, the lower end face of the first metal block is fixedly connected to the upper end face of the gate dielectric layer, the front end face of the second metal block and the front end face of the first metal block are located in the same plane, the rear end face of the second metal block and the rear end face of the first metal block are located in the same plane, and the upper end face of the second metal block and the upper end face of the first metal block are located in the same plane. The lower end surface of the second metal block is coplanar with the lower end surface of the first metal block, the lower end surface of the second metal block is fixedly connected to the upper end surface of the gate oxide induction layer, the front end surface of the third metal block is coplanar with the front end surface of the first metal block, the rear end surface of the third metal block is coplanar with the rear end surface of the first metal block, the upper end surface of the third metal block is coplanar with the upper end surface of the first metal block, the lower end surface of the third metal block is coplanar with the lower end surface of the first metal block, the lower end surface of the third metal block is fixedly connected to the upper end surface of the gate oxide induction layer, the left end surface of the third metal block is coplanar with the left end surface of the drain region, and the right end surface of the third metal block is coplanar with the right end surface of the drain region.

5. A field effect transistor with three-valued logic behavior according to claim 4, characterized in that The spacing layer includes an integrally formed first spacing block, a second spacing block and a third spacing block, the second spacing block and the third spacing block are spaced apart from each other on the left and right sides, the second spacing block is located on the left side of the third spacing block, the first spacing block is stacked above the second spacing block and the third spacing block, the front end faces of the first spacing block, the second spacing block and the third spacing block are located in the same plane, the rear end faces of the first spacing block, the second spacing block and the third spacing block are located in the same plane, the lower end faces of the second spacing block and the third spacing block are located in the same plane, the left end face of the first spacing block layer is located to the left of the plane where the left end face of the second spacing block is located or is flush with the left end face of the second spacing block, the right end face of the first spacing block layer is located to the right of the plane where the right end face of the third spacing block is located or is flush with the third spacing block The right end surface of the second spacer block is flush with the upper and lower surfaces, the second spacer block is embedded between the first metal block and the second metal block, the left end surface of the second spacer block is in contact with the right end surface of the first metal block, the right end surface of the second spacer block is in contact with the left end surface of the second metal block, the lower end surface of the second spacer block and the lower end surface of the second metal block are located in the same plane, the upper end surface of the second spacer block and the upper end surface of the second metal block are located in the same plane, the front end surface of the second spacer block and the front end surface of the second metal block are located in the same plane, the rear end surface of the second spacer block and the rear end surface of the second metal block are located in the same plane, the third spacer block is embedded between the second metal block and the third metal block, the left end surface of the third spacer block is in contact with the right end surface of the second metal block, and the right end surface of the third spacer block is in contact with the left end surface of the third metal block.

6. The field effect transistor having three-valued logic behavior according to claim 5, characterized in that The source region has a length of 20 nm and a width of 500 nm, the channel region has a length of 50 nm and a width of 500 nm, and the drain region has a length of 20 nm and a width of 500 nm; the gate dielectric layer has a length of 28 nm in the left-right direction and a thickness of 3 nm in the top-bottom direction, and the distance between the right end surface of the gate dielectric layer and the plane where the left end surface of the channel region is located is 8 nm; the gate oxide induction layer has a length of 62 nm in the left-right direction and a thickness of 3 nm in the top-bottom direction; the first metal block has a length of 28 nm in the left-right direction and a thickness of 5 nm in the top-bottom direction, and the second and third metal blocks have a length of 20 nm in the left-right direction and a thickness of 5 nm in the top-bottom direction.

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