An enhanced gallium oxide power device with a reverse conduction function

Abstract

The application belongs to the technical field of power semiconductors, and relates to an enhanced gallium oxide power device with reverse conduction function. The application proposes a lateral enhancement gallium oxide field effect transistor with high threshold voltage and excellent reverse conduction function, aiming at the problems of difficult P-type doping of gallium oxide material, difficulty in realizing enhancement, large reverse conduction voltage, small current and the like. A depletion region generated by a PN heterojunction formed by a gallium oxide channel and a P-type oxide semiconductor pinches off a fin-shaped gallium oxide channel, so that the device realizes enhancement and has excellent characteristics such as high voltage resistance and low leakage current; when the gate voltage is higher than the threshold voltage, the fin-shaped channel depletion region shrinks and forms an electron accumulation layer under the gate, so that the device is turned on. The gallium oxide power device of the application has the advantages of high threshold voltage, low reverse conduction voltage and large reverse conduction current, high voltage resistance, low on-resistance and easy integration.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and relates to an enhanced gallium oxide power device with reverse conduction function. BACKGROUND

[0002] As a new wide-bandgap semiconductor material, gallium oxide has an ultra-large band gap of 4.9 eV and a high critical breakdown field strength of 8 MV / cm, and its Baliga figure of merit is 4 times that of GaN, 10 times that of 4H-SiC and 3444 times that of Si, so it is considered to be an optimal material for the next generation of high-voltage, high-power and low-loss devices, and has broad prospects in high power density, high conversion efficiency and high power application fields.

[0003] At present, effective P-type doping of gallium oxide material has not been achieved, so that the gallium oxide power device is difficult to realize the enhancement type or high threshold voltage, thereby easily leading to device mis-opening, system failure and other serious reliability problems. Moreover, the integration of the gallium oxide power device with the freewheeling diode usually leads to problems such as large reverse conduction voltage and small reverse conduction current, and needs to be packaged into a module with an independent freewheeling diode to realize the reverse freewheeling function, thereby increasing the complexity of the circuit and the module area and increasing the cost. At present, the gallium oxide enhancement type power device is usually realized by using technical means such as recessed gate, ferroelectric dielectric or Fin structure, and it is difficult to have both the enhancement type and excellent reverse conduction function. SUMMARY

[0004] The application proposes an enhanced gallium oxide power device with reverse conduction function, which can have both the enhancement type and reverse conduction function and is easy to integrate.

[0005] The technical scheme of the application is as follows:

[0006] An enhanced gallium oxide power device with reverse conducting function, from bottom to top, is a gallium oxide substrate layer 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3; the gallium oxide epitaxial layer 3 has a source region 4 and a drain region 5 at both ends; the upper surface of the source region 4 leads out a source electrode, and the upper surface of the drain region 5 leads out a drain electrode; a fin-shaped channel region 6 is formed in the gallium oxide epitaxial layer 3, in the lateral direction of the device, one side of the fin-shaped channel region 6 is in contact with the source region 4, and the other side is spaced apart from the drain region; in the longitudinal direction of the device, the fin-shaped channel region 6 is composed of a plurality of P-type oxide semiconductor layers 61 arranged intermittently and the gallium oxide epitaxial layer 3 therebetween, and a metal 62 surrounded by the P-type oxide semiconductor layers 61, a gate structure is formed between the upper surfaces of adjacent P-type oxide semiconductor layers 61, including a gate dielectric layer 63 and a gate metal 64, the gate dielectric layer 63 covers the upper surface of the gallium oxide epitaxial layer 3 between adjacent P-type oxide semiconductor layers 61, and the gate metal 64 is further covered on the upper surface of the gate dielectric layer 63, and the gate electrode is led out on the upper surface of the gate metal 64; the upper surface of the metal 62 is flush with the upper surface of the P-type oxide semiconductor layer 61, and the metal 62 does not contact the gate dielectric layer 63, and the upper surface of the metal 62 is connected to the source electrode; wherein the P-type oxide semiconductor layer 61 is in contact with the gallium oxide epitaxial layer 3 and the source region 4 to form a heterojunction.

[0007] The beneficial effects of the present application are that by introducing a P-type oxide semiconductor capable of forming a PN heterojunction with N-type gallium oxide, both enhancement and excellent reverse conducting functions are achieved.

[0008] Further, the doping concentration of the epitaxial layer 3 between the gate region and the drain region 5 gradually increases from the side close to the gate region to the side close to the drain region 5. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 It is a three-dimensional structure schematic diagram of embodiment 1 of the present application;

[0010] Figure 2 It is a structure schematic diagram of embodiment 1 of the present application with auxiliary lines;

[0011] Figure 3 It is a sectional view along the A1A2 line in embodiment 1;

[0012] Figure 4 It is a sectional view along the B1B2 line in embodiment 1;

[0013] Figure 5 It is a sectional view along the C1C2 line in embodiment 1;

[0014] Figure 6 It is a top view of embodiment 1;

[0015] Figure 7 It is a structure schematic diagram of embodiment 2 of the present application. Detailed Implementation

[0016] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0017] The three-dimensional coordinate system shown in the figure corresponds to the following relationship in the description of this invention: the horizontal direction corresponds to the x-axis direction, the vertical direction corresponds to the y-axis direction, and the longitudinal direction corresponds to the z-axis direction.

[0018] Example 1:

[0019] like Figures 1-6 As shown, in this example, from bottom to top, there is a gallium oxide substrate layer 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3; the gallium oxide epitaxial layer 3 has a source region 4 and a drain region 5 at both ends; the source electrode is led out from the upper surface of the source region 4, and the drain electrode is led out from the upper surface of the drain region 5; the characteristic is that a fin-shaped channel region 6 is formed in the gallium oxide epitaxial layer 3, and in the lateral direction of the device, one side of the fin-shaped channel region 6 contacts the source region 4, and the other side is spaced from the drain region; in the longitudinal direction of the device, the fin-shaped channel region 6 consists of a plurality of discontinuously arranged P-type oxide semiconductor layers 61 and the gallium oxide epitaxial layer 3 between them, and a metal 62 surrounded by the P-type oxide semiconductor layers 61. A gate structure is formed between the upper surfaces of adjacent P-type oxide semiconductor layers 61, including a gate dielectric layer 63 and a gate metal 64. The gate dielectric layer 63 covers the upper surface of the gallium oxide epitaxial layer 3 between adjacent P-type oxide semiconductor layers 61. The gate metal 64 is also covered on the upper surface of the gate dielectric layer 63, and a gate is led out from the upper surface of the gate metal 64. The upper surface of the metal 62 is flush with the upper surface of the P-type oxide semiconductor layer 61, and the metal 62 does not contact the gate dielectric layer 63. The lead-out terminal on the upper surface of the metal 62 is connected to the source. The P-type oxide semiconductor layer 61 is in contact with the gallium oxide epitaxial layer 3 and the source region 4 to form a heterojunction.

[0020] The working principle of this example is as follows:

[0021] This invention proposes an enhancement-mode gallium oxide power device with reverse conduction capability. By introducing a P-type oxide semiconductor to form a PN heterojunction with N-type gallium oxide, a finned channel region is created. In the forward blocking state, with a gate voltage of 0V, the depletion effect of the P-type oxide semiconductor clamps the finned channel, and further depletes channel electrons in the upper part of the finned channel region through the metal work function difference, thereby achieving enhancement mode and low leakage current. In the forward conducting state, with a gate voltage higher than the threshold voltage, the depletion region of the finned conductive channel shrinks and forms an electron accumulation layer under the gate, turning on the finned conductive channel. Simultaneously, the P-type oxide semiconductor is segmented along the longitudinal direction of the device, allowing the formation of multiple finned channel units, facilitating the fabrication of high-current and high-power devices. In the reverse conduction state, as the source-drain voltage increases, the depletion regions of the P-type oxide semiconductor and the N-type gallium oxide shrink, opening the fin-shaped conductive channel. Current flows from the source through the channel to the drain, resulting in a small reverse conduction voltage. When the source-drain voltage further increases, the PN heterojunction formed by the P-type oxide semiconductor and the N-type gallium oxide conducts, and current flows from the P-type oxide semiconductor along the gallium oxide epitaxial layer to the drain, further enhancing the reverse current capability. Therefore, the gallium oxide power device of this invention combines high threshold voltage and excellent reverse conduction capability with the advantages of high withstand voltage, low on-resistance, and ease of integration.

[0022] Example 2:

[0023] like Figure 7 As shown, the difference between this embodiment and Embodiment 1 is that the doping concentration of the epitaxial layer 3 between the finned channel region 6 and the drain region 5 gradually increases from the side closer to the gate region to the side closer to the drain region 5. The linearly varying doping concentration can modulate the electric field distribution between the gate and drain, thereby improving the breakdown voltage of the device.

Claims

1. An enhanced gallium oxide power device with reverse conduction function, comprising, from bottom to top, a gallium oxide substrate layer (1), a gallium oxide buffer layer (2), and a gallium oxide epitaxial layer (3); the gallium oxide epitaxial layer (3) has a source region (4) and a drain region (5) at both ends; a source electrode is led out from the upper surface of the source region (4), and a drain electrode is led out from the upper surface of the drain region (5); characterized in that, A finned channel region (6) is formed in the gallium oxide epitaxial layer (3). In the lateral direction of the device, one side of the finned channel region (6) is in contact with the source region (4), and the other side is spaced from the drain region. In the longitudinal direction of the device, the finned channel region (6) is composed of a plurality of discontinuously arranged P-type oxide semiconductor layers (61) and the gallium oxide epitaxial layer (3) between them, as well as a metal (62) surrounded by the P-type oxide semiconductor layers (61). A gate structure is formed between the upper surfaces of adjacent P-type oxide semiconductor layers (61), including a gate dielectric. The gate dielectric layer (63) and gate metal (64) are respectively. The gate dielectric layer (63) covers the upper surface of the gallium oxide epitaxial layer (3) between the adjacent P-type oxide semiconductor layers (61). The gate metal (64) is also covered on the upper surface of the gate dielectric layer (63). The gate is led out from the upper surface of the gate metal (64). The upper surface of the metal (62) is flush with the upper surface of the P-type oxide semiconductor layer (61), and the metal (62) does not contact the gate dielectric layer (63). The lead-out end of the upper surface of the metal (62) is connected to the source. The P-type oxide semiconductor layer (61) is in contact with the gallium oxide epitaxial layer (3) and the source region (4) to form a heterojunction.

2. The enhanced gallium oxide power device with reverse conduction function according to claim 1, characterized in that, The material used for the P-type oxide semiconductor layer (61) is P-type NiO or P-type Cu2O.

3. The enhanced gallium oxide power device with reverse conduction function according to claim 1, characterized in that, The doping concentration of the gallium oxide epitaxial layer (3) between the fin channel region (6) and the drain region (5) gradually increases from the side closer to the fin channel region (6) to the side closer to the drain region (5).

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