An LDMOS power device, a manufacturing method thereof and an electronic device

Abstract

This invention provides an LDMOS power device, its manufacturing method, and an electronic device, relating to the field of semiconductor technology. The device includes: a semiconductor substrate; a drift region disposed in the semiconductor substrate; a body region disposed in the semiconductor substrate and spaced apart from the drift region; a field oxide layer disposed within the drift region, wherein the field oxide layer includes a field oxide region and a beak region located at one end of the field oxide region, the beak region being closer to the body region and the field oxide region being farther from the body region; a gate structure covering a portion of the field oxide layer and extending outward from the field oxide layer to a surface covering a portion of the body region, wherein the gate structure includes a gate layer, the gate layer including a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region, the first gate layer being an undoped gate layer, and at least a portion of the second gate layer being a doped gate layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOS power device, its manufacturing method, and an electronic device thereof. Background Technology

[0002] With the rapid development of the semiconductor industry, PIC (Power Integrated Circuit) is increasingly used in various fields, such as motor control, flat panel display drive control, and computer peripheral drive control. Among the power devices used in PIC circuits, DMOS (Double Diffused MOSFET) has received widespread attention due to its high operating voltage, simple process, and easy compatibility with low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits.

[0003] There are two main types of DMOS: vertical double-diffused MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS). LDMOS is widely used in the industry because it is more compatible with CMOS processes.

[0004] LDMOS devices, as a crucial component of power devices, have broad application prospects. LDMOS technologies typically grow a field oxide layer on the drift region; however, current fabrication processes inevitably result in bird-beak-like structures at both ends of the field oxide layer. To prevent damage to this bird-beak structure during subsequent processing and to avoid the abrupt termination of the electric field at the bird-beak structure, the gate (e.g., doped polysilicon) covers the bird-beak and extends partially into the field oxide layer. The doped polysilicon extending into the field oxide layer, the field oxide layer, and the drain form an additional MOS capacitance, thus increasing the Miller capacitance C. GD The presence of Miller capacitance delays the turn-on of field-effect transistors, increasing the power consumption of the device.

[0005] Therefore, in order to solve the above-mentioned technical problems, it is necessary to provide a new LDMOS power device and its manufacturing method. Summary of the Invention

[0006] The Summary of the Invention introduces a series of simplified concepts, which will be described in detail by way of example in the Detailed Description section. The Summary of the Invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the shortcomings of related technologies, this invention provides an LDMOS power device, comprising:

[0008] Semiconductor substrate;

[0009] A drift region is disposed in the semiconductor substrate;

[0010] The body region is disposed in the semiconductor substrate and spaced apart from the drift region;

[0011] A field oxide layer is disposed within the drift region, wherein the field oxide layer includes a field oxygen region and a beak region located at one end of the field oxygen region, the beak region being close to the body region and the field oxygen region being far from the body region;

[0012] A gate structure covering a portion of the field oxide layer and a portion of the body region, wherein the gate structure includes a gate layer, the gate layer including a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region, the first gate layer being an undoped gate layer, and at least a portion of the second gate layer being a doped gate layer.

[0013] For example, it also includes a source and a drain, respectively disposed in semiconductor substrates on both sides of the gate structure, wherein the drain is disposed in the drift region and has a gap between it and the gate structure, and the source is disposed in the body region.

[0014] For example, the drift region has a first conductivity type, the body region has a second conductivity type, the source and the drain have the first conductivity type, and the second gate layer has the same conductivity type as the source and the drain.

[0015] For example, it also includes: a body end, disposed in the body region and connected to the source electrode.

[0016] For example, the gate structure further includes a gate dielectric layer disposed on the surface of a semiconductor substrate beneath the polysilicon, the gate layer comprising a polysilicon layer.

[0017] In another aspect, the present invention provides a method for manufacturing an LDMOS power device, the method comprising:

[0018] A semiconductor substrate is provided in which a drift region and a body region are formed, the body region being spaced apart from the drift region, and a field oxide layer is formed in the drift region. The field oxide layer includes a field oxide region and a beak region located at one end of the field oxide region, the beak region being close to the body region and the field oxide region being far away from the body region.

[0019] A gate structure is formed, covering a portion of the surface of the field oxide layer and extending outward from the field oxide layer to cover a portion of the surface of the body region. The gate structure includes a gate layer, which includes a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region.

[0020] At least a portion of the second gate layer is doped such that at least a portion of the second gate layer is formed as a doped gate layer, while the first gate layer is an undoped gate layer.

[0021] For example, before forming the first drift region, the method further includes the step of forming a second drift region in the semiconductor substrate, wherein the top surface of the second drift region is positioned close to the bottom surface of the first drift region to be formed, and the second drift region has a first conductivity type.

[0022] For example, the doping of at least a portion of the second gate layer includes:

[0023] A patterned mask layer is formed on the surface of the semiconductor substrate, the surface of the field oxide layer, and the surface of the gate structure. The patterned mask layer exposes at least a portion of the surface of the second gate layer, the surface of the drain region in the drift region for forming the drain, and the surface of the source region in the body region for forming the source.

[0024] Using the mask layer as a mask, the second gate layer, the drain region, and the source region are heavily doped with ions, so that at least a portion of the second gate layer is formed as a doped gate layer and the drain and source are formed;

[0025] Remove the mask layer.

[0026] For example, the drift region has a first conductivity type, the body region has a second conductivity type, the source and the drain have a first conductivity type, and the doped gate layer has the same conductivity type as the source and the drain.

[0027] For example, after the step of doping at least a portion of the second gate layer, the method further includes:

[0028] The body terminal is formed by heavily doped ion implantation into the body lead-out region within the body region, which is used to form the body terminal, wherein the body terminal has a conductivity type opposite to that of the drift region.

[0029] In another aspect, the present invention provides an electronic device comprising the aforementioned LDMOS power device.

[0030] The LDMOS power device of the present invention includes a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region. The first gate layer is an undoped gate layer, and at least a portion of the second gate layer is a doped gate layer. This avoids the formation of additional MOS capacitance, thereby reducing the Miller capacitance of the device, shortening the Miller plateau caused by the Miller effect, optimizing the power consumption of the power device, and thus improving the overall performance of the semiconductor device.

[0031] The manufacturing method of the present invention, since it ultimately produces the aforementioned semiconductor device, also possesses the advantages described above. The electronic device of the present invention, since it employs the aforementioned semiconductor device, also possesses the advantages described above. Attached Figure Description

[0032] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0033] In the attached image:

[0034] Figure 1 This is a cross-sectional view of an LDMOS power device structure in the prior art;

[0035] Figure 2A-2C A schematic diagram of the structure of the device obtained by the relevant steps of the manufacturing method of the LDMOS power device according to one embodiment of the present invention is shown;

[0036] Figure 3 This is a process flow diagram of a method for manufacturing an LDMOS power device according to an embodiment of the present invention. Detailed Implementation

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0038] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0043] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0044] Related technologies such as LDMOS Figure 1 As shown. Among them, Figure 1 The LDMOS shown includes a semiconductor substrate 100, a drift region 101 and a body region 102 located within the semiconductor substrate 100, a drain 105 and a field oxide layer 103 located within the drift region 101, a source 107 and a body terminal 108 located within the body region 102, and a gate structure 104 located on the semiconductor substrate 100 covering a portion of the field oxide layer and extending outward from the field oxide layer 103 to the surface covering a portion of the body region 102.

[0045] exist Figure 1In the LDMOS shown, a field oxide layer 103 is grown on the drift region 101. However, due to limitations of the current fabrication process, a bird's beak-like structure inevitably forms at both ends of the field oxide layer. To avoid damage to the bird's beak structure during subsequent processing and to prevent the electric field from abruptly stopping at the bird's beak structure, the gate (e.g., doped polysilicon) covers the bird's beak and extends partially into the field oxide layer. The doped polysilicon, the field oxide layer, and the drain extending into the field oxide layer form an additional MOS capacitance, thus increasing the Miller capacitance C. GD The presence of Miller capacitance delays the turn-on of field-effect transistors, increasing the power consumption of the device.

[0046] Example 1

[0047] To address the aforementioned technical problems, this invention provides an LDMOS power device, such as... Figure 2C As shown, it includes:

[0048] Semiconductor substrate;

[0049] A drift region is disposed in the semiconductor substrate;

[0050] The body region is disposed in the semiconductor substrate and spaced apart from the drift region;

[0051] A field oxide layer is disposed within the drift region, wherein the field oxide layer includes a field oxygen region and a beak region located at one end of the field oxygen region, the beak region being close to the body region and the field oxygen region being far from the body region;

[0052] A gate structure covering a portion of the field oxide layer and a portion of the body region, wherein the gate structure includes a gate layer, the gate layer including a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region, the first gate layer being an undoped gate layer, and at least a portion of the second gate layer being a doped gate layer.

[0053] The device described in this application can avoid the formation of additional MOS capacitors, thereby reducing the Miller capacitance of the device, shortening the Miller plateau caused by the Miller effect, optimizing the power consumption of the power device, and thus improving the overall performance of the semiconductor device.

[0054] The following is for reference. Figure 2C The LDMOS power device of the present invention will be described in detail, wherein... Figure 2C A schematic diagram of the structure of an LDMOS power device according to one embodiment of the present invention is shown.

[0055] As an example, the LDMOS device of the present invention includes a semiconductor substrate 200.

[0056] Specifically, the semiconductor substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the semiconductor substrate 200 is made of single-crystal silicon.

[0057] For example, the semiconductor substrate 200 may be a P-type substrate or an N-type substrate.

[0058] The LDMOS device of the present invention further includes a drift region 201 and a body region 202. The drift region 201 is disposed in the semiconductor substrate 200, and the body region 202 is disposed in the semiconductor substrate 200 and spaced apart from the drift region 201. The drift region 201 has a first conductivity type, and the body region 202 has a second conductivity type.

[0059] For example, the drift region 201 is an N-type drift region and the body region 202 is a P-type body region. Alternatively, the drift region 201 can also be a P-type drift region and the body region 202 can be an N-type body region. The specific settings can be reasonably configured according to the actual device type. For an N-type LDMOS device, the drift region 201 is an N-type drift region and the body region 202 is a P-type body region.

[0060] It is worth mentioning that, in this article, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0061] Generally, the doping concentration in the drift region is low, lower than that in the source and drain. This is equivalent to forming a high-resistivity layer between the source and drain, which can improve the breakdown voltage and reduce the parasitic capacitance between the source and drain, thus improving frequency characteristics.

[0062] The LDMOS device further includes a field oxide layer 203 disposed within the drift region 201. The field oxide layer 203 includes a field oxide region and a beak region located at one end of the field oxide region. The beak region is close to the body region 202, and the field oxide region is far from the body region 202. In some embodiments, the field oxide layer 203 further includes another beak region located at the other end of the field oxide region, far from the body region 202. This beak region is typically not covered by the gate layer.

[0063] The LDMOS device also includes a gate structure 204 that covers a portion of the field oxide layer 203 and extends from the surface of the field oxide layer 203 to cover a portion of the body region 202. The gate structure 204 includes a gate layer comprising a first gate layer 2041 located on the field oxide region and a second gate layer 2042 located on the body region 202 and the beak region. The first gate layer 2041 is undoped, and at least a portion of the second gate layer 2042 is doped. By making the first gate layer 2041 on the field oxide region undoped, it is made substantially dielectric, thus preventing it from forming a MOS capacitance with the field oxide region and the drain below it. This reduces the Miller capacitance of the device, shortens the Miller plateau caused by the Miller effect, optimizes the power consumption of the power device, and improves the overall performance of the semiconductor device. It also acts as a floating field ring to improve the electric field. Furthermore, since the second gate layer located on the body region 202 and the beak region is a doped gate layer, such as a heavily doped gate layer, the damage to the beak structure (i.e. the beak region) during subsequent processing and the abrupt cessation of the electric field at the beak structure are avoided. At the same time, the second gate layer covering the body region 202 is a doped gate layer, such as a heavily doped gate layer, and the body region 202 covered by the gate structure 204 serves as the channel region of the LDMOS device.

[0064] Optionally, the gate layer may be composed of polysilicon material, but metals, metal nitrides, metal silicides, or similar compounds may also be used as the gate layer material. For example, in the embodiments of this application, the gate layer may include a polysilicon layer, in which case the first gate layer is an undoped polysilicon layer, and the second gate layer is a doped polysilicon layer.

[0065] Optionally, the second gate layer may have the same conductivity type as the source 207, drain 205, and drift region. Ion implantation is performed on the second gate layer simultaneously with ion implantation on the regions corresponding to the source and drain. The doping ions in the second gate layer differ depending on the conductivity type. For example, for N-type conductivity, the doping ions include P and / or As, while for P-type conductivity, the doping ions include boron (B).

[0066] Exemplarily, the gate structure 204 includes a gate dielectric layer located on the surface of the semiconductor substrate 200, and the aforementioned gate layer located on the gate dielectric layer 210. Specifically, for example, the gate dielectric layer 210 is disposed directly below the second gate layer 2042 and covers a portion of the substrate 200. It is worth mentioning that when the gate dielectric layer 210, for example, is formed using a thermal oxidation process, oxide can be formed on the entire substrate surface. In addition to the oxide layer below the gate layer serving as the gate dielectric layer, the oxide layers on the source and drain regions can also reduce lattice damage to the semiconductor substrate surface caused by ion implantation when the source and drain are formed by ion implantation.

[0067] The gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant electrolyte material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0068] In some embodiments, the LDMOS device of this application further includes a source 207 and a drain 205, which are formed in the semiconductor substrate 200 on both sides of the gate structure 204, wherein the drain 205 is located in the drift region 201 and the source 207 is located in the body region 202.

[0069] The source 207 and drain 205 have the same conductivity type as the drift region 201. For example, if the drift region 201 is an N-type drift region, then the source and drain are N-type source and drain.

[0070] In this embodiment, the impurity doping concentration of the drain 205 is greater than that of the drift region 201. For example, the drift region 201 is a lightly doped N-type drift region, while the drain 205 can be a heavily doped N-type doped region.

[0071] For example, a predetermined distance is spaced between the drain 205 and the gate structure 204.

[0072] The LDMOS device further includes a body terminal 208 disposed in the body region 202 and connected to the source 207. For example, one side of the body terminal 208 contacts one side of the source 207. Optionally, the body terminal 208 may have the same conductivity type as the body region 202. For example, the body terminal 208 is formed by heavily doping the predetermined region in the body region 202 where the body terminal is to be formed, that is, the doping dose of the body terminal 208 is higher than that of the body region 202. For example, if the body region 202 is lightly doped, then the body terminal 208 is heavily doped. The contact between the body terminal 208 and the source 207 can short-circuit them, thereby preventing the formation of a parasitic transistor such as a PNP transistor by the body region 202, the body terminal 208, and the source 207. This allows the body terminal 208 and the source 207 to be electrically connected at the same potential, which is beneficial for improving the response speed of the device.

[0073] It is worth mentioning that a complete LDMOS device also includes other components and elements, which will not be described in detail here.

[0074] In summary, the LDMOS device of the present invention selectively implants the gate layer of the deposited gate structure during source and drain heavy doping, that is, it heavily dops the gate layer on the bird's beak region covering the channel (i.e., the capping region) and the field oxide layer to form a heavily doped gate layer, while not doping the gate layer on the field oxide region covering the field oxide layer. This avoids the formation of additional MOS capacitance by the gate layer, field oxide region and drain on the field oxide region, thereby reducing the Miller capacitance of the device, shortening the Miller plateau caused by the Miller effect, optimizing the power consumption of the power device, and thus improving the overall performance of the LDMOS device.

[0075] Example 2

[0076] The present invention also provides a method for manufacturing the LDMOS device in the aforementioned embodiment one, such as... Figure 3 As shown, the manufacturing method mainly includes the following steps:

[0077] Step S1: Provide a semiconductor substrate, in which a drift region and a body region are formed, the body region and the drift region are spaced apart, a field oxide layer is formed in the drift region, the field oxide layer includes a field oxide region and a bird's beak region located at one end of the field oxide region, the bird's beak region is close to the body region, and the field oxide region is far away from the body region;

[0078] Step S2, forming a gate structure that covers a portion of the surface of the field oxide layer and extends outward from the field oxide layer to cover a portion of the surface of the body region. The gate structure includes a gate layer, which includes a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region.

[0079] Step S3: At least a portion of the second gate layer is doped so that at least a portion of the second gate layer is formed as a doped gate layer, while the first gate layer is an undoped gate layer.

[0080] The LDMOS device prepared by the manufacturing method of the present invention selectively implants the gate layer of the deposited gate structure during source and drain heavy doping. Specifically, it heavily dops the gate layer on the bird's beak region covering the channel (i.e., the capping region) and the field oxide layer, forming a heavily doped gate layer, while leaving the gate layer on the field oxide region undoped. This avoids the formation of additional MOS capacitance by the gate layer, field oxide region, and drain on the field oxide region, thereby reducing the Miller capacitance of the device, shortening the Miller plateau caused by the Miller effect, optimizing the power consumption of the power device, and ultimately improving the overall performance of the LDMOS device. (Refer to the following...) Figures 2A to 2C The manufacturing method of the LDMOS device of the present invention will be described in detail.

[0081] First, such as Figure 2A As shown, a semiconductor substrate 200 is provided, in which a drift region 201 is formed, the drift region 201 having a first conductivity type.

[0082] Specifically, the semiconductor substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the semiconductor substrate 200 is made of single-crystal silicon.

[0083] For example, the semiconductor substrate 200 may be a P-type substrate or an N-type substrate.

[0084] A drift region 201 is formed in the semiconductor substrate 200. The drift region 201 has a first conductivity type. For example, the drift region 201 is an N-type drift region, such as a lightly doped N-type drift region. Alternatively, the drift region 201 can also be a P-type drift region, such as a lightly doped P-type drift region. The specific settings can be reasonably configured according to the type of the actual device. For an N-type LDMOS device, the drift region 201 is an N-type drift region.

[0085] Subsequently, a body region 202 is formed in the semiconductor substrate 200, the body region 202 being spaced apart from the drift region 201 and having a second conductivity type.

[0086] In this embodiment, the drift region 201 is an N-type drift region, preferably a lightly doped N-type drift region, and the body region 202 is a P-type body region.

[0087] For example, the body region 202 is formed by ion implantation. The body region 202 has a conductivity type opposite to that of the drift region 201. For example, the drift region 201 is an N-type drift region, and the body region is a P-type body region. The specific type of dopant ions implanted is reasonably selected according to the actual device process, and will not be elaborated here.

[0088] The body region 202 and the drift region 201 are located on opposite sides of the semiconductor substrate. The channel region has the same conductivity type as the body region, but the doping concentration of impurities in the channel region is lower than that in the body region 202.

[0089] The depth of ion implantation can be controlled by adjusting the ion implantation energy. After ion implantation, an annealing process can be performed to activate the doped ions in each drift region. The annealing process uses rapid thermal annealing (RTA) or other suitable annealing methods.

[0090] A field oxide layer 203 is formed in the semiconductor substrate 200. The field oxide layer 203 is located in the drift region 201. The field oxide layer 203 includes a field oxide region and a beak region located at one end of the field oxide region. The beak region is close to the body region 202, and the field oxide region is far away from the body region 202.

[0091] The field oxide layer 203 can be formed using any suitable method known to those skilled in the art. For example, a mask layer, such as silicon nitride, can be formed on the surface of the semiconductor substrate 200. The mask layer is patterned so that openings are formed in the mask layer at positions corresponding to the areas in the drift region where the field oxide layer 203 is to be formed. Then, thermal oxidation is performed to form the field oxide layer 203 in the drift region. The portion of the field oxide layer 203 covered by the mask layer is formed into a bird's beak shape, and the bird's beak-shaped structure in the adjacent body region is also the bird's beak region. The mask layer is then removed.

[0092] Then, continue as Figure 2A As shown, a gate structure 204 is formed, covering a portion of the surface of the field oxide layer and extending outward from the field oxide layer to cover a portion of the surface of the body region. The gate structure includes a gate layer, which includes a first gate layer 2041 located on the field oxide region and a second gate layer 2042 located on the body region 202 and the beak region.

[0093] For example, the gate structure 204 includes a gate dielectric layer on the surface of the semiconductor substrate 200 and a gate layer on the gate dielectric layer.

[0094] For example, a gate dielectric layer can be formed on the surface of a semiconductor substrate by deposition or thermal oxidation, and then a polysilicon material layer can be deposited to cover the gate dielectric layer and the field oxide layer. The polysilicon material layer can be patterned to form a gate layer, wherein the gate layer includes a first gate layer 2041 located on the field oxide region and a second gate layer 2042 located on the body region 202 and the beak region.

[0095] The gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant electrolyte material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0096] It is worth mentioning that when the gate dielectric layer 210, such as an oxide, is formed using a thermal oxidation process, the oxide can be formed on the entire substrate surface. In addition to the oxide layer below the gate layer serving as the gate dielectric layer, the oxide layers on the source and drain regions can also reduce lattice damage to the semiconductor substrate surface caused by ion implantation when the source and drain are formed by ion implantation.

[0097] Then, continue as Figure 2B As shown, at least a portion of the second gate layer is doped to form a doped gate layer, while the first gate layer is an undoped gate layer.

[0098] For example, the method of this application further includes: forming a source 207 and a drain 205 in the semiconductor substrate on both sides of the gate structure 204, wherein the drain 205 is located in the drift region 201 and the source 207 is located in the body region 202.

[0099] The second gate layer can be doped at the same time as the source and drain are formed, or the second gate layer can be doped first and then the source and drain are formed, or the source and drain can be formed first and then the second gate layer is doped.

[0100] The second gate layer can be doped simultaneously with the formation of the source and drain, for example, such as... Figure 2BAs shown, a patterned mask layer 209, such as a photoresist layer, is first formed on the semiconductor substrate 200, the surface of the field oxide layer 203, and the surface of the gate structure 204. This patterned mask layer 209 exposes at least a portion of the surface of the second gate layer 2042, such as the gate layer on the channel region and the beak region in the body region 202, as well as the surface of the drain region in the drift region 201 used to form the drain 205 and the surface of the source region in the body region 202 used to form the source 207. Then, using the mask layer 209 as a mask, the second gate layer 2042, the drain region, and the source region are heavily doped with ions to form at least a portion of the second gate layer as a doped gate layer and to form the drain and source. The mask layer is then removed.

[0101] Depending on the conductivity type of the predetermined source and drain, corresponding ion implantation is performed. For example, for N-type source and drain, N-type doped ions, such as phosphorus or arsenic, are implanted; for P-type source and drain, P-type doped ions, such as boron, are implanted.

[0102] It is worth mentioning that, in this article, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0103] The source 207 and drain 205 have the same conductivity type as the drift region 201. For example, if the drift region 201 is an N-type drift region, then the source and drain are N-type source and drain.

[0104] The source 207 and drain 205 can be formed using ion implantation processes commonly used in the art, which will not be elaborated here.

[0105] In this embodiment, the impurity doping concentration of the drain 205 is greater than that of the drift region 201. For example, the drift region 201 is a lightly doped N-type drift region, and the drain 205 is a heavily doped N-type doped region.

[0106] For example, a predetermined distance is spaced between the drain 205 and the gate structure.

[0107] By making the first gate layer 2041 on the field oxide region undoped, the first gate layer 2041 is made substantially dielectric, thus avoiding the formation of a MOS capacitor with the field oxide region and the drain below the field oxide region. This reduces the Miller capacitance of the device, shortens the Miller plateau caused by the Miller effect, optimizes the power consumption of the power device, and improves the overall performance of the semiconductor device. Meanwhile, the second gate layer located on the body region 202 and the beak region is a doped gate layer, such as a heavily doped gate layer, thus avoiding damage to the beak structure (i.e., the beak region) during subsequent processing and preventing the abrupt termination of the electric field at the beak structure. Simultaneously, the second gate layer covering the body region 202 is a doped gate layer, such as a heavily doped gate layer, and the body region 202 covered by the gate structure 204 serves as the channel region of the LDMOS device.

[0108] Optionally, the second gate layer may have the same conductivity type as the source 207, drain 205, and drift region. Ion implantation is performed on the second gate layer simultaneously with ion implantation on the regions corresponding to the source and drain. The doping ions in the second gate layer differ depending on the conductivity type. For example, for N-type conductivity, the doping ions include P and / or As, while for P-type conductivity, the doping ions include boron (B).

[0109] Furthermore, by simultaneously doping the second gate layer during source and drain formation, this method exhibits good compatibility with current processes and is easy to implement. Subsequently, as... Figure 2C As shown, the body terminal 208 is formed by heavily doped ion implantation into the body region used to form the body terminal, wherein the body terminal has a conductivity type opposite to that of the drift region. For example, one side of the body terminal 208 is in contact with one side of the source 207. Optionally, the body terminal 208 may have the same conductivity type as the body region 202. For example, the body terminal 208 may be formed by heavily doping the predetermined region in the body region 202 where the body terminal is to be formed, that is, the doping dose of the body terminal 208 is higher than that of the body region 202. For example, if the body region 202 is lightly doped, then the body terminal 208 is heavily doped.

[0110] For example, the method of forming the body end 208 may include first forming a patterned mask layer, such as a patterned photoresist layer, which exposes the surface of the body lead-out region of the predetermined body end, using the patterned mask layer as a mask to perform ion implantation on the body lead-out region to form the body end 208, and then removing the mask layer.

[0111] Subsequent conventional process steps for fabricating a complete LMOS device include: forming a metal silicide barrier layer to cover at least a portion of the surface of the semiconductor substrate 200 between the gate structure 204 and the drain 205, i.e., covering the surface of the drift region 201 between the gate structure 204 and the drain 205. The metal silicide barrier layer may be an oxide layer deposited using processes such as LPCVD or PECVD, for example, low-temperature oxidation (LTO) or tetraethoxysilane (TEO), and patterning the metal silicide barrier layer to expose portions of the source, drain, body, and gate structures; then, depositing a metal layer using, for example, a sputtering process, which may contain nickel, cobalt, and platinum, or combinations thereof. Next, heating the substrate causes silicide formation between the metal layer and the underlying silicon layer, thus forming the metal silicide region. Then, using an etchant that can erode the metal layer but not the metal silicide region, unreacted metal layers are removed. Subsequently, an inner insulating layer (ILD) is deposited, and the ILD is etched using processes such as photolithography and etching to form lead holes. The lead holes are then filled with metal to form leads. These processes can employ any suitable techniques well-known to those skilled in the art, and will not be elaborated upon here.

[0112] This concludes the introduction of the key steps in the fabrication method of the LDMOS device according to this embodiment. Other steps may also be included in the complete device fabrication process, and are not limited here. It should be noted that, in this embodiment, "N-type" refers to devices doped with N-type dopant ions, and "P-type" refers to devices doped with P-type dopant ions.

[0113] In summary, the LDMOS device manufacturing method of the present invention selectively implants the gate layer of the deposited gate structure during the heavy doping implantation of the source and drain. That is, it performs heavy doping implantation on the gate layer on the bird's beak region covering the channel (i.e., the capping region) and the field oxide layer to form a heavily doped gate layer, while not doping the gate layer on the field oxide region covering the field oxide layer. This avoids the formation of additional MOS capacitance by the gate layer, field oxide region and drain on the field oxide region, thereby reducing the Miller capacitance of the device, shortening the Miller plateau caused by the Miller effect, optimizing the power consumption of the power device, and thus improving the overall performance of the LDMOS device.

[0114] Example 3

[0115] The present invention also provides an electronic device, including the LDMOS device described in Embodiment 1, wherein the LDMOS device is prepared according to the method described in Embodiment 2.

[0116] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned LDMOS device, has better performance.

[0117] The mobile phone mentioned above includes the LDMOS device described in Embodiment 1, and the LDMOS device mainly includes:

[0118] Semiconductor substrate;

[0119] A drift region is disposed in the semiconductor substrate;

[0120] The body region is disposed in the semiconductor substrate and spaced apart from the drift region;

[0121] A field oxide layer is disposed within the drift region, wherein the field oxide layer includes a field oxygen region and a beak region located at one end of the field oxygen region, the beak region being close to the body region and the field oxygen region being far from the body region;

[0122] A gate structure covering a portion of the field oxide layer and extending outward from the field oxide layer to cover a portion of the surface of the body region, wherein the gate structure includes a gate layer, the gate layer including a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region, the first gate layer being an undoped gate layer, and at least a portion of the second gate layer being a doped gate layer.

[0123] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An LDMOS power device, characterized by, include: Semiconductor substrate; A drift region is disposed in the semiconductor substrate; The body region is disposed in the semiconductor substrate and spaced apart from the drift region; A field oxide layer is disposed within the drift region, wherein the field oxide layer includes a field oxygen region and a beak region located at one end of the field oxygen region, the beak region being close to the body region and the field oxygen region being far from the body region; A gate structure covering a portion of the field oxide layer and a portion of the body region surface, wherein the gate structure includes a gate layer, the gate layer including a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region, the first gate layer being an undoped gate layer, the first gate layer being substantially in a dielectric state, the first gate layer, the field oxide region, and the drain below the field oxide region not forming a MOS capacitor, thereby reducing the Miller capacitance of the device, and at least a portion of the second gate layer being a doped gate layer.

2. The LDMOS power device as described in claim 1, characterized in that, Also includes: The source and drain are respectively disposed in the semiconductor substrates on both sides of the gate structure, wherein the drain is disposed in the drift region and has a gap between it and the field oxide layer, and the source is disposed in the body region.

3. The LDMOS power device as described in claim 2, characterized in that, The drift region has a first conductivity type, the body region has a second conductivity type, the source and the drain have a first conductivity type, and the second gate layer has the same conductivity type as the source and the drain.

4. The LDMOS power device as described in claim 2, characterized in that, Also includes: The body end is disposed in the body region and connected to the source electrode.

5. The LDMOS power device as described in claim 1, characterized in that, The gate structure further includes a gate dielectric layer disposed on the surface of a semiconductor substrate below the gate layer, and the gate layer includes a polysilicon layer.

6. A method for manufacturing an LDMOS power device, characterized in that, include: A semiconductor substrate is provided in which a drift region and a body region are formed, the body region being spaced apart from the drift region, and a field oxide layer is formed in the drift region. The field oxide layer includes a field oxide region and a beak region located at one end of the field oxide region, the beak region being close to the body region and the field oxide region being far away from the body region. A gate structure is formed, covering a portion of the surface of the field oxide layer and extending outward from the field oxide layer to cover a portion of the surface of the body region. The gate structure includes a gate layer, which includes a first gate layer located on the field oxide region and a second gate layer located on the body region and the beak region. At least a portion of the second gate layer is doped to form a doped gate layer, while the first gate layer is an undoped gate layer. The first gate layer is generally in a dielectric state, and the first gate layer, the field oxide region, and the drain below the field oxide region do not constitute a MOS capacitor, thereby reducing the Miller capacitance of the device.

7. The manufacturing method as described in claim 6, characterized in that, The doping of at least a portion of the second gate layer includes: A patterned mask layer is formed on the surface of the semiconductor substrate, the surface of the field oxide layer, and the surface of the gate structure. The patterned mask layer exposes at least a portion of the surface of the second gate layer, the surface of the drain region in the drift region for forming the drain, and the surface of the source region in the body region for forming the source. Using the mask layer as a mask, the second gate layer, the drain region, and the source region are heavily doped with ions, so that at least a portion of the second gate layer is formed as a doped gate layer and the drain and source are formed; Remove the mask layer.

8. The manufacturing method as described in claim 7, characterized in that, The drift region has a first conductivity type, the body region has a second conductivity type, the source and the drain have a first conductivity type, and the doped gate layer has the same conductivity type as the source and the drain.

9. The manufacturing method as described in claim 6, characterized in that, Following the step of doping at least a portion of the second gate layer, the method further includes: The body terminal is formed by heavily doped ion implantation into the body lead-out region within the body region, which is used to form the body terminal, wherein the body terminal has a conductivity type opposite to that of the drift region.

10. An electronic device, characterized in that, The electronic device includes an LDMOS power device as described in any one of claims 1 to 5.

Images