A foreground analog calibration method applied to a capacitive bridged DAC

Abstract

The application discloses a foreground analog calibration method applied to a capacitive bridging type DAC, and comprises the following steps: inputting a sinusoidal signal into a SAR ADC to obtain a current digital code output by the SAR ADC; performing histogram distribution statistics on the current digital code; detecting whether the current digital code satisfies preset monotonicity based on N(i), and determining a connection mode of a calibration capacitor of a current capacitor in an LSB array of the bridging DAC according to a detection result; determining a calibration capacitor to be connected from all calibration capacitors of the current capacitor; returning to the step of inputting the sinusoidal signal into the SAR ADC after connecting the calibration capacitor to be connected to the bridging DAC according to the connection mode, and gradually reducing a quantization error of the DAC, so that INL and DNL satisfy error requirements. Meanwhile, the application takes a protection isolation capacitor filled around the LSB array as the calibration capacitor, adjusts a bit capacitor ratio of the capacitor array through a series-parallel calibration capacitor mode, reduces a proportion mismatch of the capacitor array as a whole, and reduces a non-linear error of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of digital-to-analog converter technology, specifically relating to a front-end analog calibration method for capacitor-bridged DACs. Background Technology

[0002] SAR (Successive approximation register) ADCs (Analog-to-Digital Converters) achieve high power efficiency due to their simple structure and dynamic operation. The conversion linearity of SAR ADCs primarily depends on the capacitive DAC (Digital-to-Analog Converter), which commonly uses binary weighted and bridged structures. Depending on noise requirements, a bridged DAC requires fewer units of capacitance per unit than a binary weighted DAC for the same total capacitance. For example, an 8-bit DAC with a binary weighted structure requires 256 units, while a bridged DAC requires at least 31 units, quantizing 4 bits in the MSB (most significant bit) and LSB (least significant bit) arrays. Therefore, bridged DACs have less interconnect area loss, but the difficulty in precisely matching bridging capacitors and the presence of parasitic capacitances within the internal nodes of the bridged DAC lead to severe conversion nonlinearity issues.

[0003] A bridged capacitor array divides a complete capacitor array into several sub-arrays connected by bridging capacitors. Under the influence of the bridging capacitors, the equivalent capacitance of the subsequent capacitor array is proportionally reduced, thus achieving quantization with a larger number of bits with a smaller capacitance value. Typically, the voltage change for each quantization step is designed according to a binary ratio. The equivalent capacitance of the bridge capacitor and its subsequent array in series should be equal to the unit capacitance of the preceding array. Taking a single-stage bridged array as an example: the original capacitor array is divided into two sub-arrays. The array with the higher quantization bits is designated the MSB array, and the array with the lower quantization bits is designated the LSB array. These are connected by bridging capacitors. The upper plate of the bridging capacitor is connected to the MSB array, and the lower plate is connected to the LSB array. The timing switching method remains unchanged. The capacitors of the MSB and LSB arrays are designed according to their respective quantization bit counts, using a binary ratio. The bridging capacitor is connected in series with the LSB array. The equivalent capacitance after series connection should be equal to the unit capacitance of the MSB array. At this point, the circuit voltage can change exactly according to the binary ratio, outputting the desired result.

[0004] However, in reality, due to significant mismatches in parasitic and bridging capacitances within the circuit, the capacitance ratio of the capacitor array changes, preventing the voltage change from strictly adhering to a binary ratio. The most significant factors are the parasitic capacitances of the sampling plates of the MSB array, the LSB array, and the bridging capacitors. All three types of capacitors degrade circuit performance. The parasitic capacitance of the sampling plates of the MSB array primarily introduces gain error, having little impact on nonlinearity. The latter two, however, drastically worsen the circuit's INL (Integral Nonlinearity) and DNL (Differential Nonlinearity).

[0005] Calibration methods in related technologies typically perform calibration in the digital domain, processing only the ADC output digital code. This involves shifting missing digital codes to the upper boundary of the digital output to improve circuit nonlinearity without altering the circuit's structure. While the calibration compensates for the circuit's nonlinearity, the actual quantization range is reduced because the problem of partially lost digital codes remains unresolved. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a front-end analog calibration method for capacitor-bridged DACs. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] This invention provides a front-end analog calibration method for a capacitor-bridged DAC, comprising:

[0008] A sinusoidal signal is input into the successive approximation register analog-to-digital converter (SAR ADC) to obtain the current digital code output by the SAR ADC;

[0009] Perform histogram distribution statistics on the current digit code, denot the i-th current digit code as Dout(i) and the number of the i-th current digit code as N(i), i = 0 to 255;

[0010] Based on N(i), it is determined whether the current digital code satisfies the preset monotonicity, and the connection method of the calibration capacitor of the current capacitor in the least significant bit (LSB) array of the bridge DAC is determined according to the detection result.

[0011] From all the calibration capacitors of the current capacitor, determine the calibration capacitor to be connected;

[0012] After connecting the calibration capacitor to be connected to the bridge DAC according to the connection method, return to the step of inputting the sine signal into the SAR ADC, and use the digital code output by the SAR ADC as the current digital code until the current digital code meets the preset monotonicity, at which point the calibration ends.

[0013] In one embodiment of the present invention, the step of detecting whether the current digital code satisfies a preset monotonicity based on N(i), and determining the connection method of the calibration capacitor of the current capacitor in the least significant bit (LSB) array of the bridge DAC based on the detection result, includes:

[0014] Let i = 1, and determine whether N(i) - N(i-1) < 0 is true; if N(i) - N(i-1) ≥ 0, then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in series to the bridge DAC; otherwise, further determine whether N(i+1) - N(i) ≤ 0 is true.

[0015] If N(i+1)-N(i)>0, then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in parallel to the bridge DAC; otherwise, let i=i+1 and then determine whether i<128 is true.

[0016] If i < 128, then return to the step of determining whether N(i) - N(i-1) < 0 is true; otherwise, further determine whether i = 255 is true.

[0017] If i < 255, then determine whether N(i) - N(i+1) < 0 is true; when N(i) - N(i+1) < 0 is not true, connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in series to the bridge DAC, and return to the step of setting i = 1 and determining whether N(i) - N(i-1) < 0 is true; when N(i) - N(i+1) < 0 is true, then further determine whether N(i-1) - N(i) ≤ 0 is true.

[0018] If N(i-1)-N(i)>0, then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in parallel to the bridge DAC, and return to the step of setting i=1 and judging whether N(i)-N(i-1)<0 is true; otherwise, set i=i+1 and return to the step of judging whether i=255 is true, until i=255.

[0019] In one embodiment of the present invention, the bridged DAC further includes a most significant bit (LSB) array and a bridging capacitor Ca, wherein the LSB array includes a capacitor C. dummy C dummyThe MSB array includes capacitors C5, C6, C7, and C8, with C2 being the pre-amplifier, C3 being the pre-amplifier of C2, and C4 being the pre-amplifier of C3.

[0020] Among them, the first plate of Ca is connected to the output terminal Vout, and the second plate is connected to C4, C3, C2 and C6. dummy The first electrode plate is connected, and the second electrodes of C4, C3, and C2 are connected to the calibration module. dummy The calibration module is connected; the first plates of C8, C7, C6 and C5 are connected to the first plate of Ca, and the second plates are connected to the first reference level.

[0021] In one embodiment of the present invention, the calibration module includes M calibration capacitors: C S1 C S2 C S3 ... C SM and N calibration switches: S0, S1, S2, ..., S N ;in,

[0022] The first plate of the current capacitor is connected to C via S1. S1 The first and second plates are connected to C via S0. SM The first and second plates, C S1 The first plate and C S2 The first plate is connected via S3, and the first node N1 is located near C on S3. S1 On one side, the second plate of the capacitor is connected to N1 via S2, and the second node N2 is located on S3 away from C. S1 On one side, the second plate of the current capacitor is connected to N2 via S4, C Sm The first plate and C Sm+1 The first electrode plate passes through S n Connection, C Sm The second electrode plate and C Sm+1 The second electrode plate and C Sm+1 Through S n+1 Connect; where m = 2, 3, ..., M-1, n = 2m+1.

[0023] In one embodiment of the present invention, the step of determining the calibration capacitor to be connected from all calibration capacitors of the current capacitor includes:

[0024] C dummy The x-th calibration capacitor in the corresponding calibration module is denoted as C. d(x), let the y-th calibration capacitor in the calibration module corresponding to C2 be denoted as C2(y), the z-th calibration capacitor in the calibration module corresponding to C3 be denoted as C3(z), and the j-th calibration capacitor in the calibration module corresponding to C4 be denoted as C4(j), and let x = 1, y = 1, z = 1, j = 1;

[0025] Determine whether x > M is true;

[0026] If x > M is true, then further determine whether y > M is true; otherwise, then set C... d (x) is determined to be the calibration capacitor to be connected and x = x + 1 is set. Then, the process returns to the step of determining whether x > M is true.

[0027] If y > M holds true, then further determine whether z > M holds true; otherwise, determine C2(y) as the calibration capacitor to be connected, and then connect the preceding capacitor C... dummy After all the calibration switches in the corresponding calibration module are reset, set y = y + 1 and x = 1, and return to the step of determining whether x > M is true;

[0028] If z > M holds true, then further determine whether j > M holds true; otherwise, determine C3(z) as the calibration capacitor to be connected, and then... dummy After all the calibration switches in the calibration module corresponding to C2 are reset, set z = z + 1, x = 1, y = 1, and return to the step of determining whether x > M is true;

[0029] If j > M, then all calibration capacitors to be connected are obtained; otherwise, C4(j) is determined as the calibration capacitor to be connected, and C is then... dummy After all the calibration switches in the calibration modules corresponding to C2 and C3 are reset, set j = j + 1, x = 1, y = 1, z = 1, and return to the step of determining whether x > M is true.

[0030] In one embodiment of the present invention, before the step of connecting the calibration capacitor of the current capacitor to the bridge DAC according to the connection method, the method further includes:

[0031] Close switch S0 in the calibration module corresponding to the current capacitor;

[0032] The steps of connecting the calibration capacitor to the bridge DAC according to the connection method described include:

[0033] Adjust the state of each switch in the calibration module corresponding to the current capacitor, so that the calibration capacitor to be connected is connected to the bridge DAC in sequence according to the connection method.

[0034] In one embodiment of the present invention, if all calibration capacitors of the current capacitor have been connected to the bridge DAC and the current digital code does not satisfy a preset monotonicity, then before the step of inputting the sinusoidal signal into the successive approximation register analog-to-digital converter (SAR ADC), the method further includes:

[0035] Use the preceding capacitor of the current capacitor as the current capacitor.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] This invention provides a front-end analog calibration method for a capacitor-bridged DAC. First, it utilizes the piecewise monotonicity of the digital code histogram output by the ADC under ideal conditions. The histogram of the current digital code is tested piecewise to determine if there are nodes that do not satisfy monotonicity. Then, the capacitance values ​​of the dummy bit capacitors and the low-order capacitors in the LSB array are calibrated, making the histogram curve exhibit a piecewise monotonic trend, reducing quantization error, and ensuring that INL and DNL meet error requirements. Simultaneously, this invention uses the protective isolation capacitors filling the area around the LSB array on the layout as calibration capacitors. By connecting the calibration capacitors in series or parallel with the last dummy capacitor of the LSB array, the equivalent capacitance of the LSB array and the bridging capacitors in series is changed, thereby adjusting the bit capacitance ratio of the entire capacitor array, reducing the overall proportional mismatch of the capacitor array, and minimizing the nonlinear error of the circuit.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0039] Figure 1 This is a flowchart of a front-end analog calibration method for a capacitor-bridged DAC provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the bridged DAC provided in an embodiment of the present invention;

[0041] Figure 3 This is another flowchart of the front-end analog calibration method for a capacitor-bridged DAC provided in this embodiment of the invention;

[0042] Figure 4 This is another flowchart of the front-end analog calibration method for a capacitor-bridged DAC provided in this embodiment of the invention;

[0043] Figure 5 This is a schematic diagram of the dummy bit calibration module provided in an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the structure of other bit calibration modules in the LSB array provided in the embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0046] Figure 1 This is a schematic flowchart of a front-end analog calibration method for a capacitor-bridged DAC provided in an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a front-end analog calibration method for a capacitor-bridged DAC, comprising:

[0047] S1. Input the sinusoidal signal into the successive approximation register analog-to-digital converter (SAR ADC) to obtain the current digital code output by the SAR ADC;

[0048] S2. Perform histogram distribution statistics on the current digit code, denot the i-th current digit code as Dout(i) and the number of the i-th current digit code as N(i), i = 0 ~ 255;

[0049] S3. Based on N(i), detect whether the current digital code satisfies the preset monotonicity, and determine the connection method of the calibration capacitor of the current capacitor in the least significant bit LSB array of the bridge DAC according to the detection result.

[0050] S4. Determine the calibration capacitor to be connected from all the calibration capacitors of the current capacitor;

[0051] S5. After connecting the calibration capacitor to be connected to the bridge DAC according to the connection method, return to step S1 above to execute the step of inputting the sine signal into the SAR ADC, and use the digital code output by the SAR ADC as the current digital code until the current digital code meets the preset monotonicity, and the calibration ends.

[0052] Figure 2 This is a schematic diagram of the bridged DAC provided in an embodiment of the present invention. Figure 2 As shown, in this embodiment, the bridged DAC includes an eight-bit capacitor array. Specifically, the bridged DAC includes three parts: an MSB array, a bridging capacitor Ca, and an LSB array. The MSB array consists of four-bit quantizations B8, B7, B6, and B5, and the LSB array consists of four-bit quantizations B4, B3, B2, and B1. The MSB array and the LSB array are each composed of four capacitors.

[0053] It should be understood that, ideally, when the input signal to the SAR ADC is a standard sine wave, performing 10,000 quantizations and generating a histogram of the ADC output digital codes—specifically, plotting the digital codes on the horizontal axis and the frequency of each digital code on the vertical axis—results in a bowl-shaped histogram (high on both sides and low in the middle), with the frequency of each digital code being predictable. Dividing the histogram into left and right halves from the middle value, both halves are monotonic functions, with the left half monotonically decreasing and the right half monotonically increasing. However, when quantization errors exist in the bridged DAC, the histogram will show increases or decreases in the number of digital codes, potentially disrupting the piecewise monotonicity of the curve.

[0054] During the research process, the inventors modeled three factors that significantly influenced the quantification results and compared them with the ideal situation:

[0055] Firstly, considering only the parasitic capacitance of the sampling plates in the MSB array, the histogram is bowl-shaped overall. The left and right halves of the middle bits show monotonically decreasing and monotonically increasing values, respectively. However, the number of bits per digit changes. Specifically, the number of bits at the boundaries of the histogram increases sharply, while the number of bits for each other digit decreases, with the decrease being greater closer to the edge. Clearly, this parasitic capacitance only introduces gain error (linear error), while the nonlinear errors of INL and DNL are very small.

[0056] Secondly, considering only the parasitic capacitance of the sampling plates in the LSB array, the histogram shows that the height of most digital codes decreases except at the boundaries, while a few increase. The increased digital code height is related to the structure of the DAC capacitor array. Using the aforementioned 8-bit bridged capacitor array as a model, the increase in digital code height occurs during the toggle of the high four bits (B8-5) of the MSB array quantization. In other words, this parasitic capacitance introduces not only gain error but also nonlinear error, and both INL and DNL show significant errors.

[0057] Thirdly, considering only the mismatch of the bridging capacitor Ca, this mismatch introduces both gain and nonlinearity errors. When the bridging capacitor is larger than the theoretical value, the number of digits related to the flipping of the high four bits B8-5 from 0 to 1 in the histogram is almost zero. The number of digits on both sides is greater than zero but less than the ideal value, and the number of digits in other parts increases slightly. INL and DNL show large errors, with DNL showing code loss. When the bridging capacitor is smaller than the normal value, the number of digits related to the flipping of the high four bits B8-5 from 0 to 1 in the histogram increases significantly, and the number of digits in other parts decreases slightly. INL and DNL show large errors.

[0058] The modeling results above show that the presence of non-ideal factors in the capacitor array mainly affects the quantization results of the high-order MSB array, disrupting the piecewise monotonicity of the digital code distribution histogram. Based on this principle, this invention detects whether the histogram of the current digital code satisfies the preset piecewise monotonicity and compares it with the ideal histogram to determine the change in the number of digital codes. Finally, it determines the series or parallel connection method for the calibration capacitors. Specifically, if there is a surge in the number of critical bits, the number of calibration capacitors connected in series is increased; if there is a decrease in the number of critical bits, the number of calibration capacitors connected in parallel is increased.

[0059] Please continue reading Figure 2 In this embodiment, the bridged DAC further includes a most significant bit (MSB) array and a bridging capacitor Ca. The LSB array includes capacitor C. dummy C dummy The MSB array includes capacitors C5, C6, C7, and C8, with C2 being the pre-amplifier, C3 being the pre-amplifier of C2, and C4 being the pre-amplifier of C3.

[0060] Among them, the first plate of Ca is connected to the output terminal Vout, and the second plate is connected to C4, C3, C2 and C6. dummy The first plate connection, C4, C3, C2 and C dummy The second electrode plate is connected to the calibration module; the first electrodes of C8, C7, C6 and C5 are connected to the first electrode plate of Ca, and the second electrodes are connected to the first reference level.

[0061] Specifically, the LSB array consists of four-bit quantized cells B4, B3, B2, and B1, with corresponding capacitors C4, C3, C2, and C1, respectively. dummy The MSB array is a four-bit quantized array consisting of B8, B7, B6, and B5, composed of four capacitors: C8, C7, C6, and C5. It should be noted that the final dummy capacitor C... dummy Used for binary balancing, its size can be flexibly set according to the influence of parasitic effects on the bridge capacitor value in the actual DAC capacitor array. For example, connecting the calibration capacitor in series with the bridge DAC in the calibration module will decrease the capacitance of that bit, thereby decreasing the equivalent series capacitance of the bridge capacitor and the LSB array; conversely, connecting the calibration capacitor in parallel with the bridge DAC will increase the capacitance of that bit, thereby increasing the equivalent series capacitance of the bridge capacitor and the LSB array. Therefore, by utilizing the variable capacitance of the dummy bit, the total capacitance of the entire capacitor array can be adjusted, making the voltage change during quantization approach a binary ratio.

[0062] Figure 3 This is another flowchart of the front-end analog calibration method for a capacitor-bridged DAC provided in this embodiment of the invention. Figure 3As shown, in step S3 above, the step of detecting whether the current digital code satisfies the preset monotonicity based on N(i), and determining the connection method of the calibration capacitor of the current capacitor in the least significant bit (LSB) array of the bridge DAC according to the detection result, includes:

[0063] S301. Let i = 1, and determine whether N(i) - N(i-1) < 0 is true. If N(i) - N(i-1) ≥ 0, it means that the number of current digital codes Dout(i) is too large. Then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in series to the bridge DAC. Otherwise, further determine whether N(i+1) - N(i) ≤ 0 is true.

[0064] S302. If N(i+1)-N(i)>0, it means that the number of current digital codes Dout(i) is too small. Then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in parallel to the bridge DAC. Otherwise, let i=i+1 and then determine whether i<128 is true.

[0065] S303. If i < 128, then return to the step of judging whether N(i) - N(i-1) < 0 is true; otherwise, further judge whether i = 255 is true.

[0066] S304. If i < 255, then determine whether N(i) - N(i+1) < 0 is true; when N(i) - N(i+1) < 0 is not true, it means that the number of current digital codes Dout(i) is too large. Connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in series to the bridge DAC, and return to step S301 above. Execute the step of setting i = 1 and determining whether N(i) - N(i-1) < 0 is true; when N(i) - N(i+1) < 0 is true, then further determine whether N(i-1) - N(i) ≤ 0 is true.

[0067] S305. If N(i-1)-N(i)>0, it means that the number of current digital codes Dout(i) is too small. Then, connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in parallel to the bridge DAC, return to step S301 above, and execute the step of setting i=1 and judging whether N(i)-N(i-1)<0 is true; otherwise, set i=i+1 and return to the step of judging whether i=255 is true, until i=255.

[0068] It should be understood that in this embodiment, the judgment starts from i=1 because i=0 corresponds to the first current digit code, and monotonicity cannot be detected by the current digit codes on the left and right. Similarly, since i=255 corresponds to the last current digit code, it is also impossible to compare it with the current digit codes on the left and right. Therefore, the comparison ends when i=255.

[0069] Furthermore, the calibration module includes M calibration capacitors: C S1 C S2 C S3 ... C SM and N calibration switches: S0, S1, S2, ..., S N ;in,

[0070] The first plate of the current capacitor is connected to C via S1. S1 The first and second plates are connected to C via S0. SM The first and second plates, C S1 The first plate and C S2 The first plate is connected via S3, and the first node N1 is located near C on S3. S1 On one side, the second plate of the capacitor is connected to N1 via S2, and the second node N2 is located on S3 away from C. S1 On one side, the second plate of the current capacitor is connected to N2 via S4, C Sm The first plate and C Sm+1 The first electrode plate passes through S n Connection, C Sm The second electrode plate and C Sm+1 The second electrode plate and C Sm+1 Through S n+1 Connect; where m = 2, 3, ..., M-1, n = 2m+1.

[0071] Figure 4 This is another flowchart of the front-end analog calibration method for a capacitor-bridged DAC provided in this embodiment of the invention. Figure 5 This is a schematic diagram of the dummy bit calibration module provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of other bit calibration modules in the LSB array provided in this embodiment of the invention. For example... Figure 4-6 As shown, step S4 above, the step of determining the calibration capacitor to be connected from all calibration capacitors of the current capacitor, includes:

[0072] S401, C dummy The x-th calibration capacitor in the corresponding calibration module is denoted as C. d (x), let the y-th calibration capacitor in the calibration module corresponding to C2 be denoted as C2(y), the z-th calibration capacitor in the calibration module corresponding to C3 be denoted as C3(z), and the j-th calibration capacitor in the calibration module corresponding to C4 be denoted as C4(j), and let x = 1, y = 1, z = 1, j = 1;

[0073] S402. Determine whether x > M is true;

[0074] S403. If x > M is true, then further determine whether y > M is true; otherwise, then set C... d (x) After determining that it is the calibration capacitor to be connected and setting x = x + 1, return to step S402 above and execute the step of judging whether x > M is true;

[0075] S404. If y > M is true, then further determine whether z > M is true; otherwise, determine C2(y) as the calibration capacitor to be connected, and then connect the preceding capacitor C. dummy After all the calibration switches in the corresponding calibration module are reset, let y = y + 1 and x = 1, return to step S402 above, and execute the step of judging whether x > M is true;

[0076] S405. If z > M holds true, then further determine whether j > M holds true; otherwise, determine C3(z) as the calibration capacitor to be connected, and then... dummy After all the calibration switches in the calibration module corresponding to C2 are reset, let z = z+1, x = 1, y = 1, return to step S402 above, and execute the step of judging whether x > M is true;

[0077] S406. If j > M, then all calibration capacitors to be connected are obtained; otherwise, C4(j) is determined as the calibration capacitor to be connected, and C is... dummy After all the calibration switches in the calibration modules corresponding to C2 and C3 are reset, set j = j + 1, x = 1, y = 1, z = 1, return to step S402 above, and execute the step of judging whether x > M is true.

[0078] If all calibration capacitors of the current capacitor are connected to the bridge DAC and the current digital code does not satisfy the preset monotonicity, then before the step of inputting the sinusoidal signal into the successive approximation register analog-to-digital converter (SAR ADC), the following steps are also included:

[0079] Use the preceding capacitor of the current capacitor as the current capacitor.

[0080] For the LSB array in a bridged DAC, during calibration, the capacitor to be connected in the calibration module corresponding to the current capacitor can be determined according to steps S401 to S406. The current capacitor is C. dummy C2, C3, and C4. Specifically, the connection order of the calibration capacitors in the calibration module is as follows: If the current digital code does not meet the preset monotonicity, then determine the connection method of the calibration capacitors during this calibration process, and then determine C... dummy The corresponding calibration module contains the capacitor to be connected, and the capacitor to be connected is connected to C according to this connection method. dummyIf the circuit is connected in series or parallel, return to the steps of inputting a sinusoidal signal into the successive approximation register analog-to-digital converter (SAR ADC) and check the current digital code generated by the SAR ADC after the first calibration. If the current digital code still does not meet the preset monotonicity, determine the connection method of the calibration capacitor in the second calibration process, and connect the calibration capacitor to be connected in series or parallel to complete the second calibration... If the capacitor mismatch is too large, follow the above steps to connect C... dummy If, after connecting all calibration capacitors in the corresponding calibration module to the DAC, the quantization result still cannot be controlled within the error range, then it is necessary to adjust C. dummy The calibration module corresponding to the preamp capacitor C2 participates in the calibration; if the quantization result of the DAC still cannot reach the acceptable error range, the calibration module corresponding to the preamp capacitor C3 of C2 can continue to be used. If the quantization result still does not reach the acceptable error range, the calibration module corresponding to the preamp capacitor C4 of C3 can continue to be used until all the calibration capacitors in the calibration module corresponding to C4 are connected to the bridge DAC.

[0081] It should be noted that the calibration process for C4, C3, and C2 is the same as that for the dummy bit, so it will not be repeated here. Additionally, when calibrating the bit containing the current capacitor, during the phase where the lower plate of other capacitors switches the reference level, the lower plate of the current capacitor is disconnected from the reference level and connected to the corresponding calibration capacitor. When the lower plate of the current capacitor needs to be connected to the reference level for quantization, its lower plate is disconnected from the calibration capacitor and connected to the reference level, maintaining this state until the circuit is reset. If the circuit still cannot be calibrated to an acceptable error range, the preceding capacitor of the current capacitor can continue to be used.

[0082] Optionally, before the step of connecting the calibration capacitor of the current capacitor to the bridge DAC according to the connection method, the method further includes:

[0083] Close switch S0 in the calibration module corresponding to the current capacitor, so that C dummy The second electrode plate is connected to the second reference level V. CM .

[0084] Step S5 above, the step of connecting the calibration capacitor to be connected to the bridge DAC according to the connection method, includes:

[0085] Adjust the state of each switch in the calibration module corresponding to the current capacitor, and connect the calibration capacitors to be connected to the bridge DAC in sequence according to the connection method described above.

[0086] Because C4, C3, C2, C dummy The calibration capacitors to be connected in the corresponding calibration modules are all connected to the DAC in the same way, so C is still used. dummy Let's take an example to illustrate. Specifically, when the current capacitance is C...dummy The steps of adjusting the state of each switch in the calibration module corresponding to the current capacitor, and sequentially connecting the calibration capacitors to be connected to the bridge DAC according to the connection method, include:

[0087] If the first detection of the current digital code does not meet the preset monotonicity and the connection method is series, close calibration switches S2 and S... n+1 And disconnect other calibration switches, so that C S1 Connect the dummy bit in series; if the first detection of the current digit code does not satisfy the preset monotonicity and the connection method is parallel, close S1 and S2. n+1 And disconnect other calibration switches, so that C S1 Parallel connection to the dummy bit; if the second detection of the current digital code does not meet the preset monotonicity and the connection method is parallel, close calibration switches S2, S3 and S... n+1 And disconnect other switches, so that C S1 Connect the dummy bit in series; if the current digital code does not meet the preset monotonicity in the second detection and the connection method is series, then close calibration switches S0, S1 and S2. n And disconnect other switches, so that C S1 C S2 Connect the dummy bit in series; if the third detection of the current digital code does not meet the preset monotonicity and the connection method is series, then close S2, S3, S6, S7, S9... and disconnect other calibration switches; if the third detection of the current digital code does not meet the preset monotonicity and the connection method is parallel, then close S0, S1, S5, S6, S7, S9... and disconnect other calibration switches; and so on.

[0088] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0089] This invention provides a front-end analog calibration method for a capacitor-bridged DAC. First, it utilizes the piecewise monotonicity of the digital code histogram output by the ADC under ideal conditions. The histogram of the current digital code is tested piecewise to determine if there are nodes that do not satisfy monotonicity. Then, the capacitance values ​​of the dummy bit capacitors and the low-order capacitors in the LSB array are calibrated, making the histogram curve exhibit a piecewise monotonic trend, reducing quantization error, and ensuring that INL and DNL meet error requirements. Simultaneously, this invention uses the protective isolation capacitors filling the area around the LSB array on the layout as calibration capacitors. By connecting the calibration capacitors in series or parallel with the last dummy capacitor of the LSB array, the equivalent capacitance of the LSB array and the bridging capacitors in series is changed, thereby adjusting the bit capacitance ratio of the entire capacitor array, reducing the overall proportional mismatch of the capacitor array, and minimizing the nonlinear error of the circuit.

[0090] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0091] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0092] Although this application has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in carrying out the claimed application by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0093] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A front-end analog calibration method for a capacitor-bridged DAC, characterized in that, include: A sinusoidal signal is input into the successive approximation register analog-to-digital converter (SAR ADC) to obtain the current digital code output by the SAR ADC; Perform histogram distribution statistics on the current digit code, denot the i-th current digit code as Dout(i) and the number of the i-th current digit code as N(i), i=0~255; Based on N(i), it is determined whether the current digital code satisfies the preset monotonicity, and the connection method of the calibration capacitor of the current capacitor in the least significant bit (LSB) array of the bridge DAC is determined according to the detection result. From all the calibration capacitors of the current capacitor, determine the calibration capacitor to be connected; After connecting the calibration capacitor to be connected to the bridge DAC according to the connection method, return to the step of inputting the sine signal into the SAR ADC, and use the digital code output by the SAR ADC as the current digital code until the current digital code satisfies the preset monotonicity, and the calibration ends. The steps of detecting whether the current digital code satisfies a preset monotonicity based on N(i) and determining the connection method of the calibration capacitor of the current capacitor in the least significant bit (LSB) array of the bridge DAC based on the detection result include: Let i=1, and determine whether N(i)-N(i-1)<0 holds true; if N(i)-N(i-1)≥0, then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in series to the bridge DAC; otherwise, further determine whether N(i+1)-N(i)≤0 holds true. If N(i+1)-N(i)>0, then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in parallel to the bridge DAC; otherwise, let i=i+1 and then determine whether i<128 is true. If i < 128, then return to the step of determining whether N(i) - N(i-1) < 0 is true; otherwise, further determine whether i = 255 is true. If i < 255, then determine whether N(i) - N(i+1) < 0 is true; when N(i) - N(i+1) < 0 is not true, connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in series to the bridge DAC, and return to the step of setting i = 1 and determining whether N(i) - N(i-1) < 0 is true; when N(i) - N(i+1) < 0 is true, then further determine whether N(i-1) - N(i) ≤ 0 is true. If N(i-1)-N(i)>0, then connect the calibration capacitor in the calibration module corresponding to the current capacitor in the LSB array in parallel to the bridge DAC, and return to the step of setting i=1 and judging whether N(i)-N(i-1)<0 is true; otherwise, set i=i+1 and return to the step of judging whether i=255 is true, until i=255. The bridged DAC also includes a most significant bit (LSB) array and a bridging capacitor Ca. The LSB array includes capacitor C. dummy C dummy The MSB array includes capacitors C5, C6, C7, and C8, with C2 as the pre-amplifier, C3 as the pre-amplifier, and C4 as the pre-amplifier. The first plate of capacitor C5 is connected to the output terminal Vout, and the second plate is connected to capacitors C4, C3, C2, and C8. dummy The first plate connection, C4, C3, C2 and C dummy The second electrode plate is connected to the calibration module; the first electrodes of C8, C7, C6 and C5 are connected to the first electrode plate of Ca, and the second electrodes are connected to the first reference level; The calibration module includes M calibration capacitors: C S1 C S2 C S3 ... C SM and N calibration switches: S0, S1, S2, ..., S N The first plate of the current capacitor is connected to C via S1. S1 The first and second plates are connected to C via S0. SM The first and second plates, C S1 The first plate and C S2 The first plate is connected via S3, and the first node N1 is located near C on S3. S1 On one side, the second plate of the capacitor is connected to N1 via S2, and the second node N2 is located on S3 away from C. S1 On one side, the second plate of the current capacitor is connected to N2 via S4, C Sm The first plate and C Sm+1 The first electrode plate passes through S n Connection, C Sm The second electrode plate and C Sm+1 The second electrode plate and C Sm+1 Through S n+1 Connect; where m = 2, 3, ..., M-1, n = 2m+1; The step of determining the calibration capacitor to be connected from all calibration capacitors of the current capacitor includes: C dummy The x-th calibration capacitor in the corresponding calibration module is denoted as C. d (x), let the y-th calibration capacitor in the calibration module corresponding to C2 be denoted as C2(y), the z-th calibration capacitor in the calibration module corresponding to C3 be denoted as C3(z), and the j-th calibration capacitor in the calibration module corresponding to C4 be denoted as C4(j), and let x=1, y=1, z=1, j=1; Determine whether x > M is true; If x > M is true, then further determine whether y > M is true; otherwise, then set C... d (x) After determining the calibration capacitor to be connected and setting x=x+1, return to the step of judging whether x>M is true; If y > M holds true, then further determine whether z > M holds true; otherwise, determine C2(y) as the calibration capacitor to be connected, and then connect the preceding capacitor C... dummy After all the calibration switches in the corresponding calibration module are reset, set y=y+1 and x=1, and return to the step of determining whether x>M is true; If z > M holds true, then further determine whether j > M holds true; otherwise, determine C3(z) as the calibration capacitor to be connected, and then... dummy After all the calibration switches in the calibration module corresponding to C2 are reset, set z=z+1, x=1, y=1, and return to the step of determining whether x>M is true; If j > M, then all calibration capacitors to be connected are obtained; otherwise, C4(j) is determined as the calibration capacitor to be connected, and C is then... dummy After all the calibration switches in the calibration modules corresponding to C2 and C3 are reset, set j=j+1, x=1, y=1, z=1, and return to the step of determining whether x>M is true.

2. The front-end analog calibration method for a capacitor-bridged DAC according to claim 1, characterized in that, Before the step of connecting the calibration capacitor of the current capacitor to the bridge DAC according to the described connection method, the method further includes: Close switch S0 in the calibration module corresponding to the current capacitor; The steps of connecting the calibration capacitor to the bridge DAC according to the connection method described include: Adjust the state of each switch in the calibration module corresponding to the current capacitor, so that the calibration capacitor to be connected is connected to the bridge DAC in sequence according to the connection method.

3. The front-end analog calibration method for a capacitor-bridged DAC according to claim 1, characterized in that, If all calibration capacitors of the current capacitor are connected to the bridge DAC and the current digital code does not satisfy the preset monotonicity, then before the step of inputting the sinusoidal signal into the successive approximation register analog-to-digital converter (SAR ADC), the following steps are also included: Use the preceding capacitor of the current capacitor as the current capacitor.

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