Rate mode control method and device of eMMC, storage medium and terminal

Abstract

A rate mode control method and device of an eMMC, a storage medium and a terminal are provided.The method comprises the following steps: determining a working scene rate mode of an embedded multimedia card (eMMC), and determining a highest rate mode supported by the eMMC; comparing the highest rate mode and the working scene rate mode, and determining a target rate mode of the eMMC according to a comparison result; and switching a current rate mode of the eMMC to the target rate mode.The above scheme can adaptively select a proper working rate mode according to a working scene demand of the eMMC and the highest rate mode supported by the eMMC, so as to improve data transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a rate mode control method and apparatus, storage medium, and terminal for eMMC. Background Technology

[0002] Embedded Multi Media Card (eMMC) is a standard specification for embedded memory in terminal devices such as mobile phones and tablets, defined by the MMC Association. eMMC consists of Flash memory, a Flash controller (containing multiple registers), and a data transfer interface. Different specifications of eMMC can operate in different speed modes, mainly including Legacy mode, High Speed ​​(HS) mode, HS200 mode, HS400 mode, and HS400ES mode.

[0003] The bootloader is a program primarily used in embedded systems (mainly U-Boot) and can support various computer system architectures. Currently, most eMMCs typically operate in HS mode during the U-Boot phase. However, the bootloader performs numerous read and write operations on the eMMC during both the boot and download phases. During the terminal device boot phase, the bootloader reads the kernel image (e.g., the Linux kernel) from the eMMC's Flash and loads it into Random Access Memory (RAM); during the download phase, the bootloader needs to write a large number of image files transferred via Universal Serial Bus (USB) into the eMMC's Flash. Therefore, compared to high-speed modes like HS400ES, operating the eMMC solely in HS mode severely impacts boot and download efficiency, delaying download completion time. Especially for applications with high demands for boot speed or file download speed, the data transfer rate of the eMMC can be significantly optimized.

[0004] In the prior art, a method for implementing eMMC HS400 transmission mode under a U-Boot system is provided. This method sets the eMMC's operating speed mode to HS400 mode during the U-Boot stage. Although this implementation improves the transmission rate to some extent, it lacks compatibility, does not consider the actual working scenario requirements of eMMC, and is not compatible with eMMCs that do not support HS400 mode. Summary of the Invention

[0005] The technical problem solved by the embodiments of the present invention is how to adaptively select an appropriate working rate mode based on the working scenario requirements of eMMC and the highest supported rate mode in order to improve data transmission efficiency.

[0006] To address the aforementioned technical problems, this invention provides a rate mode control method for an eMMC, comprising the following steps: determining the working scenario rate mode of the embedded multimedia card eMMC, and determining the highest rate mode supported by the eMMC; comparing the highest rate mode and the working scenario rate mode, and determining the target rate mode of the eMMC based on the comparison result; and switching the current rate mode of the eMMC to the target rate mode.

[0007] Optionally, determining the target rate mode of the eMMC based on the comparison result includes: if the highest rate mode is the same as the working scenario rate mode, then the working scenario rate mode is taken as the target rate mode of the eMMC; if the highest rate mode is different from the working scenario rate mode, then the mode with the lower rate between the highest rate mode and the working scenario rate mode is selected as the target rate mode of the eMMC.

[0008] Optionally, the highest speed mode and the working scenario speed mode are selected from: Legacy mode, HS mode, HS200 mode, HS400 mode, and HS400ES mode.

[0009] Optionally, switching the current rate mode of the eMMC to the target rate mode includes: sending a first rate mode switching instruction to the eMMC, the first rate mode switching instruction being used to instruct the eMMC to switch from the current operating rate mode to HS mode; in response to the eMMC successfully switching to HS mode and the target rate mode being HS mode, sending a first bus mode switching instruction to the eMMC, the first bus mode switching instruction being used to instruct the eMMC to switch the current bus transmission mode to the bus transmission mode corresponding to HS mode; and in response to the successful bus transmission mode switching, updating the current clock frequency to the clock frequency corresponding to HS mode.

[0010] Optionally, after sending the first rate mode switching instruction, the method further includes: in response to the eMMC successfully switching to HS mode and the rate of the target rate mode being higher than that of HS mode, sending a second bus mode switching instruction to the eMMC, the second bus mode switching instruction being used to instruct the eMMC to switch its current bus transmission mode to the bus transmission mode corresponding to the target rate mode; in response to the successful bus transmission mode switching, sending a second rate mode switching instruction to the eMMC, the second rate mode switching instruction being used to instruct the eMMC to switch from HS mode to the target rate mode; and in response to the eMMC successfully switching to the target rate mode, updating the current clock frequency to the clock frequency corresponding to the target rate mode.

[0011] Optionally, the method further includes: whenever it is confirmed that the eMMC has failed to switch to HS mode, repeatedly sending the first rate mode switching instruction to the eMMC until it is confirmed that the eMMC has successfully switched to HS mode or the number of repeated transmissions reaches a preset number; in response to the preset number of repeated transmissions and the eMMC still failing to switch to HS mode, sending a rate reduction mode switching instruction to the eMMC, the rate reduction mode switching instruction being used to instruct the eMMC to switch from the current operating rate mode to Legacy mode.

[0012] Optionally, the target rate mode is selected from either the HS200 mode or the HS400 mode; after updating the current clock frequency to the clock frequency corresponding to the target rate mode, the method further includes: tuning the transmission delay parameter corresponding to the target rate mode.

[0013] Optionally, tuning the transmission delay parameter corresponding to the target rate mode includes: using the starting value of a preset sampling interval as the initial value of the transmission delay parameter; repeatedly sending a tuning template acquisition instruction to the eMMC, wherein after each sending of the tuning template acquisition instruction, the value of the transmission delay parameter is increased by 1 until all values ​​of the transmission delay parameter from the initial value to the current value completely cover the preset sampling interval, and then stopping the sending of the tuning template acquisition instruction; based on the tuning template returned by the eMMC after each sending of the tuning template acquisition instruction, comparing it with a pre-stored tuning template, and determining the tuned value of the transmission delay parameter.

[0014] Optionally, based on the results of comparing the tuning template returned by the eMMC after each transmission of the tuning template acquisition instruction with the pre-stored tuning template, the tuned value of the transmission delay parameter is determined, including: selecting a sub-interval from the preset sampling interval that has the most consecutive successful comparisons and the largest total number of successful comparisons; and taking the average or midpoint value of the values ​​of each transmission delay parameter contained in the sub-interval as the tuned value of the transmission delay parameter.

[0015] Optionally, determining the highest rate mode supported by the eMMC includes: sending a data read instruction to the eMMC, the data read instruction being used to instruct the eMMC to return highest rate mode indication data; and determining the highest rate mode supported by the eMMC based on the received highest rate mode indication data.

[0016] Optionally, determining the eMMC's operating scenario rate mode includes: in response to receiving an operating scenario switching instruction, determining whether a predefined scenario rate mode exists for the operating scenario after the switch indicated by the operating scenario switching instruction; or, in response to receiving an operating scenario start instruction, determining whether a predefined scenario rate mode exists for the operating scenario to be started indicated by the operating scenario start instruction; if the determination result is yes, then the predefined scenario rate mode is adopted as the operating scenario rate mode of the eMMC; if the determination result is no, then the HS mode is adopted as the target rate mode of the eMMC.

[0017] Optionally, the predefined scene rate mode is based on macro definition.

[0018] This invention also provides a rate mode control device for an eMMC, comprising: a rate mode determination module, configured to determine the working scenario rate mode of the embedded multimedia card eMMC and to determine the highest rate mode supported by the eMMC; a rate mode comparison module, configured to compare the highest rate mode and the working scenario rate mode, and determine the target rate mode of the eMMC based on the comparison result; and a rate mode switching module, configured to switch the current rate mode of the eMMC to the target rate mode.

[0019] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the above-described eMMC rate mode control method.

[0020] This invention also provides a terminal, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the steps of the above-described eMMC rate mode control method when running the computer program.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] This invention provides a rate mode control method for an eMMC, which determines the working scenario rate mode of the embedded multimedia card eMMC and the highest rate mode supported by the eMMC; compares the highest rate mode and the working scenario rate mode, and determines the target rate mode of the eMMC based on the comparison result; and switches the current rate mode of the eMMC to the target rate mode.

[0023] In this embodiment of the invention, the working scenario rate mode of the eMMC and the highest rate mode supported by the eMMC are compared to determine the target rate mode, and then the device switches to the target rate mode. The working scenario rate mode is determined based on the actual working scenario of the eMMC (e.g., it can be determined in response to receiving a working scenario switching command or a working scenario initiation command), while the highest rate mode is limited by the performance of the eMMC device itself. Compared to existing technologies that always keep the eMMC operating in a fixed rate mode (e.g., a lower-speed HS mode), this embodiment can adaptively select between the highest rate mode and the working scenario rate mode to determine an appropriate target rate mode, thereby maximizing data transmission efficiency.

[0024] Further, determining the target rate mode of the eMMC based on the comparison result includes: if the highest rate mode is the same as the working scenario rate mode, then the working scenario rate mode is taken as the target rate mode of the eMMC; if the highest rate mode is different from the working scenario rate mode, then the mode with the lower rate between the highest rate mode and the working scenario rate mode is selected as the target rate mode of the eMMC. In this embodiment of the invention, by adopting the above comparison scheme, it can be ensured that the target rate mode to be switched will not exceed the range of the highest rate mode of the eMMC, and can meet the data transmission rate requirements of the working scenario as much as possible.

[0025] Furthermore, the method further includes: whenever it is confirmed that the eMMC has failed to switch to HS mode, repeatedly sending the first rate mode switching instruction to the eMMC until it is confirmed that the eMMC has successfully switched to HS mode or the number of repeated transmissions reaches a preset number; in response to the preset number of repeated transmissions, and the eMMC still has not successfully switched to HS mode, sending a rate reduction mode switching instruction to the eMMC, the rate reduction mode switching instruction being used to instruct the eMMC to switch from the current operating rate mode to Legacy mode.

[0026] In this embodiment of the invention, if the switch from eMMC to HS mode fails, the aforementioned retry mechanism can be used to avoid rate mode switching failures caused by accidental factors, thereby increasing the probability of successful rate mode switching. Furthermore, if multiple attempts to switch fail, switching the eMMC to Legacy mode (typically considered the lowest rate mode) ensures the normal operation of the eMMC and improves the reliability and stability of the device.

[0027] Furthermore, based on the tuning template returned by the eMMC after each transmission of the tuning template acquisition instruction, and the comparison result with the pre-stored tuning template, the tuned value of the transmission delay parameter is determined, including: selecting a sub-interval from the preset sampling interval with the highest number of consecutive successful comparisons; and using the average or midpoint value of the values ​​of each transmission delay parameter contained in the sub-interval as the tuned value of the transmission delay parameter. In this embodiment of the invention, by selecting a sub-interval with the highest number of consecutive successful comparisons and then determining the tuned value of the transmission delay parameter from that sub-interval, the reliability and accuracy of the determined tuned value can be improved. Attached Figure Description

[0028] Figure 1 This is a flowchart of a rate mode control method for eMMC according to an embodiment of the present invention;

[0029] Figure 2 yes Figure 1 A flowchart of the first specific implementation of step S13;

[0030] Figure 3 yes Figure 1 A flowchart of the second specific implementation method of step S13;

[0031] Figure 4 This is a schematic diagram illustrating the statistical results of comparing a tuning template returned by eMMC with a pre-stored tuning template in an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the structure of a rate mode control device for eMMC in an embodiment of the present invention. Detailed Implementation

[0033] As mentioned in the background section, if eMMC operates only in a low-speed fixed mode (e.g., HS mode) during the bootloader stage, it will severely impact startup and download efficiency, delaying download completion time. Especially for applications with high demands for startup or file download speeds, there is significant room for optimization in eMMC's data transfer rate.

[0034] In the prior art, a method for implementing eMMC HS400 transmission mode under U-Boot system is provided. This method sets the working speed mode of eMMC to HS400 mode in the U-Boot stage. Although it improves the transmission speed to a certain extent, the compatibility is not strong. It does not take into account the actual working scenario requirements of eMMC, and it is not compatible with eMMC that does not support HS400 mode.

[0035] To address the aforementioned technical problems, this invention provides a rate mode control method for an eMMC, characterized by comprising: determining the working scenario rate mode of the embedded multimedia card eMMC, and determining the highest rate mode supported by the eMMC; comparing the highest rate mode and the working scenario rate mode, and determining the target rate mode of the eMMC based on the comparison result; and switching the current rate mode of the eMMC to the target rate mode.

[0036] Therefore, in this embodiment of the invention, the working scenario rate mode of the eMMC and the highest rate mode supported by the eMMC are combined; after comparing the two, a target rate mode is determined, and then the device switches to the target rate mode. The working scenario rate mode is determined based on the actual working scenario of the eMMC (e.g., it can be determined in response to receiving a working scenario switching command or a working scenario start command), while the highest rate mode is limited by the performance of the eMMC device itself. Compared to keeping the eMMC always operating in a fixed rate mode (e.g., a lower-speed HS mode), the solution in this embodiment can adaptively select between the highest rate mode and the working scenario rate mode to determine an appropriate target rate mode, thereby maximizing data transmission efficiency.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Reference Figure 1 , Figure 1 This is a flowchart of a rate mode control method for eMMC according to an embodiment of the present invention. The method can be applied to various terminal devices configured with eMMC, and is mainly applied in the bootloader stage. The method can be implemented as a software program, which runs in a processor integrated within a chip or chip module; or, the method can be implemented in hardware or a combination of hardware and software. The terminals include, but are not limited to, mobile phones, computers, tablets, wearable devices (e.g., smartwatches), in-vehicle terminals (e.g., rearview mirrors, smart cockpits, in-vehicle computers), etc.

[0039] The method may include steps S11 to S13:

[0040] Step S11: Determine the working scenario rate mode of the embedded multimedia card eMMC, and determine the highest rate mode supported by the eMMC;

[0041] Step S12: Compare the highest rate mode and the working scenario rate mode, and determine the target rate mode of the eMMC based on the comparison result;

[0042] Step S13: Switch the current rate mode of the eMMC to the target rate mode.

[0043] In this embodiment, the correspondence between different rate modes of the eMMC and the bus transmission mode (or bus data transmission mode), as well as the correspondence between different rate modes of the eMMC and the clock frequency of the host or host controller, are pre-defined, for example, in the JESD84-B51 protocol. According to the definition of the JESD84-B51 protocol, the correspondence between at least some rate modes of the eMMC and the bus transmission mode, and the clock frequency (usually referring to the highest clock frequency provided by the host to the eMMC), is as follows:

[0044] The eMMC's rate mode is Legacy mode, and the corresponding bus transmission mode is Single Data Rate (SDR) transmission mode with a bus width of 1 bit, 4 bits, or 8 bits, and the corresponding clock frequency is 26MHz.

[0045] The eMMC's rate mode is HS mode, and the corresponding bus transmission mode is SDR transmission mode with a bus width of 1 bit, 4 bits, or 8 bits, and the corresponding clock frequency is 52MHz.

[0046] The eMMC's rate mode is HS200 mode, and the corresponding bus transmission mode is SDR transmission mode with a bus width of 4 bits or 8 bits, and the corresponding clock frequency is 200MHz.

[0047] The eMMC's data rate mode is HS400 mode, and the corresponding bus transmission mode is Double Data Rate (DDR) transmission mode with a bus width of 4 bits or 8 bits, and the corresponding clock frequency is 200MHz.

[0048] The eMMC uses the HS400ES mode for its data rate, and the corresponding bus transmission mode is the DDR transmission mode with a bus width of 8 bits and a clock frequency of 200MHz.

[0049] Among them, the data transfer efficiency is sorted from low to high as: Legacy mode < HS mode < HS200 mode < HS400ES mode.

[0050] It should be noted that in this embodiment, the rate modes in which the eMMC can operate are exemplified by Legacy mode, HS mode, HS200 mode, HS400 mode, and HS400ES mode, but it is not limited to this in actual applications. For newly added or modified rate modes, they can be updated according to their data transfer efficiency.

[0051] In this embodiment, each instruction sent to the eMMC can also be defined by the JESD84 - B51 protocol. Specifically, for instructions related to eMMC rate mode switching and bus transfer mode switching, the cmd6 command defined by the JESD84 - B51 protocol can be used. Among them, for different target modes to be switched, the specific information or parameters included in the corresponding cmd6 command can be different. Specifically, the functions of each instruction in the embodiment of the present invention are as follows:

[0052] The first rate mode switching instruction is used to instruct the eMMC to switch from the current working rate mode to the HS mode;

[0053] The second rate mode switching instruction is used to instruct the eMMC to switch from the HS mode to the target rate mode. It should be noted that the second rate mode switching instruction does not refer to a single instruction, but different target rate modes correspond to different second rate mode switching instructions;

[0054] The down - rate mode switching instruction is used to instruct the eMMC to switch the current bus transfer mode to the Legacy mode;

[0055] The first bus mode switching instruction is used to instruct the eMMC to switch the current bus transfer mode to the bus transfer mode corresponding to the HS mode;

[0056] The second bus mode switching instruction is used to instruct the eMMC to switch the current bus transfer mode to the bus transfer mode corresponding to the target rate mode. It should be noted that the second bus mode switching instruction does not refer to a single instruction, but for different target rate modes, the corresponding bus transfer modes correspond to different second bus mode switching instructions;

[0057] The data read instruction (for example, the cmd8 command defined by the JESD84 - B51 protocol) is used to instruct the eMMC to return the highest rate mode indication data;

[0058] A tuning template retrieval instruction (e.g., the cmd21 command defined in the JESD84-B51 protocol) is used to instruct the eMMC to return a tuning template (e.g., tuning_block_pattern).

[0059] In the specific implementation of step S11, the maximum rate mode can be determined by the device performance of the eMMC itself. For a specific eMMC, the maximum rate mode is usually uniquely determined. The working scenario mode can be determined according to the actual working scenario requirements of the eMMC, and is therefore variable, or can be predefined / set. In practical applications, the working scenario rate mode can be the same as or different from the maximum rate mode.

[0060] Without limitation, the highest speed mode and the working scenario speed mode may be selected from: Legacy mode, HS mode (which may include HS DDR mode and HS SDR mode), HS200 mode, HS400 mode, HS400ES mode, etc.

[0061] Furthermore, the determination of the eMMC's working scenario rate mode in step S11 can include at least the following specific implementation methods.

[0062] In a first specific implementation, in response to receiving a work scene switching instruction, it is determined whether a predefined scene rate mode exists in the work scene after the switch indicated by the work scene switching instruction. If the determination result is yes, the predefined scene rate mode is adopted as the work scene rate mode of the eMMC; if the determination result is no, the HS mode can be directly adopted as the target rate mode of the eMMC, and then the process jumps to execute step S13.

[0063] The predefined scene rate modes corresponding to various work scenarios can be defined based on macros, or they can be preset in other appropriate ways.

[0064] In the second specific implementation, in response to receiving a work scenario start command, it is determined whether the work scenario to be started indicated by the work scenario start command has a predefined scenario rate mode; if the determination result is yes, the predefined scenario rate mode is adopted as the work scenario rate mode of the eMMC; if the determination result is no, the HS mode can be directly adopted as the target rate mode of the eMMC, and then the process jumps to execute step S13.

[0065] In the third specific implementation, in response to receiving the eMMC rate mode change instruction, it is determined whether there is a predefined scene rate mode in the current working scenario of the eMMC. If the determination result is yes, the predefined scene rate mode is adopted as the working scene rate mode of the eMMC; if the determination result is no, the HS mode can be directly adopted as the target rate mode of the eMMC, and then the process jumps to execute step S13.

[0066] Further, determining the highest rate mode supported by the eMMC in step S11 may include: sending a data read instruction to the eMMC, the data read instruction being used to instruct the eMMC to return the highest rate mode indication data; and determining the highest rate mode supported by the eMMC based on the received highest rate mode indication data.

[0067] The highest rate mode indication data may be located in a specific bit of the EXT_CSD register (e.g., the devicetype flag bit of the 196th bit of the EXT_CSD register).

[0068] In the specific implementation of step S12, the highest rate mode and the working scenario rate mode are compared. The comparison result may be that they are the same or they are different. The cases where they are different are: the transmission rate corresponding to the highest rate mode is higher than the transmission rate corresponding to the working scenario mode; or, the transmission rate corresponding to the working scenario mode is higher than the transmission rate corresponding to the highest rate mode.

[0069] Further, in step S12, determining the target rate mode of the eMMC based on the comparison result may specifically include: if the highest rate mode is the same as the working scenario rate mode, then the working scenario rate mode is taken as the target rate mode of the eMMC; if the highest rate mode is different from the working scenario rate mode, then the mode with the lower rate between the highest rate mode and the working scenario rate mode is selected as the target rate mode of the eMMC.

[0070] In this embodiment of the invention, the above comparison scheme is adopted: if the rate modes are the same, either one is selected; if the rate modes are different, the lower rate mode is selected. This ensures that the target rate mode to be switched to does not exceed the maximum rate mode range of the eMMC, while also meeting the data transmission rate requirements of the working scenario as much as possible. Therefore, while ensuring the reliability of rate mode switching, data transmission efficiency is improved as much as possible.

[0071] In a specific implementation of step S13, the current rate mode of the eMMC is switched to the target rate mode. Specifically, the specific implementation scheme for switching typically differs for different target rate modes.

[0072] Reference Figure 2 , Figure 2 yes Figure 1 A flowchart of the first specific implementation of step S13. In this specific implementation, the target rate mode to be switched is HS mode. Step S13 may include steps S21 to S23.

[0073] In step S21, a first rate mode switching instruction is sent to the eMMC, which instructs the eMMC to switch from the current operating rate mode to HS mode.

[0074] In step S22, in response to the eMMC successfully switching to HS mode and the target rate mode being HS mode, a first bus mode switching instruction is sent to the eMMC. The first bus mode switching instruction is used to instruct the eMMC to switch the current bus transmission mode to the bus transmission mode corresponding to HS mode.

[0075] Furthermore, whenever it is confirmed that the eMMC has failed to switch to HS mode, the first rate mode switching instruction is repeatedly sent to the eMMC until it is confirmed that the eMMC has successfully switched to HS mode or the number of repeated transmissions reaches a preset number; in response to the preset number of repeated transmissions and the eMMC still failing to switch to HS mode, a rate reduction mode switching instruction is sent to the eMMC, the rate reduction mode switching instruction being used to instruct the eMMC to switch from the current operating rate mode to Legacy mode.

[0076] The preset number of times can be set appropriately according to the specific application scenario requirements, for example, it can be set to an appropriate number of times between 3 and 5 times.

[0077] In this embodiment of the invention, if the switch from eMMC to HS mode fails, the aforementioned retry mechanism can be used to avoid rate mode switching failures caused by accidental factors, thereby increasing the probability of successful rate mode switching. Furthermore, if multiple attempts to switch fail, switching the eMMC to Legacy mode (typically considered the lowest rate mode) ensures the normal operation of the eMMC and improves the reliability and stability of the device.

[0078] In step S23, in response to the successful switching of the bus transmission mode, the current clock frequency is updated to the clock frequency corresponding to the HS mode.

[0079] Specifically, the current clock frequency may refer to the highest clock frequency currently provided by the host or host controller to the eMMC. The host controller may be, for example, a hardware or software module integrated on the central processing unit (CPU) and primarily used for communicating with the eMMC.

[0080] In practice, whenever the bus transmission mode switching fails, the retry mechanism and the switch to the lowest rate mode mechanism can be adopted as described in step S22 above. The specific implementation scheme is as described above and will not be repeated here.

[0081] Reference Figure 3 , Figure 3 yes Figure 1 A flowchart of the second specific implementation of step S13. In this specific implementation, the rate of the target rate mode to be switched is higher than that of the HS mode. For example, the target rate mode can be selected from any one of HS200 mode, HS400 mode, and HS400ES mode. Step S13 may include steps S31 to S34, wherein step S31 and... Figure 2 The same applies to step S21 shown below. The following applies to... Figure 2 The different aspects of the illustrated embodiments will be explained.

[0082] In step S31, a first rate mode switching instruction is sent to the eMMC, which is used to instruct the eMMC to switch from the current operating rate mode to HS mode.

[0083] In step S32, in response to the eMMC successfully switching to HS mode and the target rate mode having a higher rate than the HS mode, a second bus mode switching instruction is sent to the eMMC. The second bus mode switching instruction is used to instruct the eMMC to switch the current bus transmission mode to the bus transmission mode corresponding to the target rate mode.

[0084] In step S33, in response to the successful bus transmission mode switch, a second rate mode switching instruction is sent to the eMMC, the second rate mode switching instruction being used to instruct the eMMC to switch from HS mode to the target rate mode.

[0085] In step S34, in response to the successful switching of the eMMC to the target rate mode, the current clock frequency is updated to the clock frequency corresponding to the target rate mode.

[0086] In this specific implementation, whenever a rate mode switching failure is confirmed during eMMC rate mode switching, or whenever a bus transmission mode switching failure is confirmed during bus transmission mode switching, reference can be made to... Figure 2 The retry mechanism and the switch to the lowest rate mode mechanism described in step S22 perform multiple repeated switches and switch back to Legacy mode after multiple failed switches to improve the success rate of rate mode switching and enhance the reliability and stability of device operation. The specific implementation process will not be elaborated here.

[0087] Among these, the target rate mode to be switched and the bus transmission mode to be switched are different, and the number of retries (i.e., the number of times the relevant instructions are repeatedly sent) can be the same or different.

[0088] Furthermore, the target rate mode is selected from either the HS200 mode or the HS400 mode; after updating the current clock frequency to the clock frequency corresponding to the target rate mode, the method further includes: tuning the transmission delay parameter corresponding to the target rate mode.

[0089] The transmission delay parameter corresponding to the target rate mode can be preset. Specifically, the transmission delay parameter can be used to indicate the delay of data communication between the host and the eMMC.

[0090] In practice, the transmission delay parameters can be determined based on the sdioconfig parameters obtained from memory, which can be stored in memory as a structure. After determining the transmission delay parameters, they can be written into the corresponding transmission delay parameter register in the host. The transmission delay parameters written into the corresponding register in the host can include data read falling edge delay (readdata negedge delay), data read rising edge delay (readdata posedge delay), command read delay (read command delay), and data write delay (writedata delay).

[0091] Specifically, the transmission delay parameters that need to be tuned may differ depending on the target rate mode to be switched. For example, if the target rate mode is HS200, the transmission delay parameters that need to be tuned include readdata posedge delay and read command delay; or if the target rate mode is HS400, the transmission delay parameter that needs to be tuned is read command delay.

[0092] Furthermore, the transmission delay parameter corresponding to the target rate mode is tuned, including: using the starting value of a preset sampling interval as the initial value of the transmission delay parameter; repeatedly sending a tuning template acquisition instruction to the eMMC, wherein after each sending of the tuning template acquisition instruction, the value of the transmission delay parameter is increased by 1 until all values ​​of the transmission delay parameter from the initial value to the current value completely cover the preset sampling interval, and then the sending of the tuning template acquisition instruction is stopped; based on the tuning template returned by the eMMC after each sending of the tuning template acquisition instruction, the result of comparing it with a pre-stored tuning template is used to determine the tuned value of the transmission delay parameter.

[0093] In this sampling interval, each value is an integer. As a non-limiting embodiment, the preset sampling interval can be set to [0x00, 0xff] (this interval is a hexadecimal range, which is [0, 255] in decimal). By setting the starting value of the preset sampling interval to 0, the value range of the transmission delay parameter during tuning can be wider, avoiding the omission of small but reliable values.

[0094] Furthermore, based on the results of comparing the tuning template returned by the eMMC after each transmission of the tuning template acquisition instruction with the pre-stored tuning template, the tuned value of the transmission delay parameter is determined, including: selecting a sub-interval from the preset sampling interval that has the most consecutive successful comparisons and the largest total number of successful comparisons; and taking the average or midpoint value of the values ​​of each transmission delay parameter contained in the sub-interval as the tuned value of the transmission delay parameter.

[0095] If the received tuning template is completely consistent with the pre-stored coordination template, the comparison can be considered successful; if the received tuning template is not completely consistent with the pre-stored coordination template, the comparison can be considered a failure.

[0096] In specific implementation, regarding the method of comparing tuning templates, after each sending of the tuning template acquisition command, the tuning template returned by the eMMC can be compared with the pre-stored tuning template, and the comparison result can be recorded; or, after stopping sending the tuning template acquisition command, all coordination templates received from the eMMC each time can be compared with the pre-stored tuning template, and the comparison result can be recorded; or, other appropriate comparison methods can also be used.

[0097] Reference Figure 4 , Figure 4 This is a schematic diagram illustrating the statistical results of comparing a tuning template returned by eMMC with a pre-stored tuning template in an embodiment of the present invention.

[0098] In this embodiment, the sampling interval is [0, 255], where successful alignment results are recorded as "Y" and unsuccessful alignment results are recorded as "N". As shown in the figure, the alignment sub-interval [n1, n2] contains the most successful alignment results. Therefore, the average or midpoint value of each value contained in [n1, n2] is used as the tuned value of the transmission delay parameter corresponding to the target rate mode.

[0099] Wherein, when the number of values ​​contained in [n1,n2] is odd, the midpoint value is (n2+n1) / 2, and when the number of values ​​contained in [n1,n2] is even, the midpoint value can be (n2+n1+1) / 2 or (n2+n1-1) / 2.

[0100] In this embodiment of the invention, by selecting the sub-interval with the most consecutive successful comparisons and the highest total number of successful comparisons, and then determining the tuned value of the input delay parameter from the sub-interval, the reliability and accuracy of the determined tuned value can be improved.

[0101] Reference Figure 5 , Figure 5 This is a schematic diagram of a rate mode control device for eMMC according to an embodiment of the present invention. The rate mode control device for eMMC may include:

[0102] The rate mode determination module 51 is used to determine the working scenario rate mode of the embedded multimedia card eMMC, and to determine the highest rate mode supported by the eMMC.

[0103] The rate mode comparison module 52 is used to compare the highest rate mode and the working scenario rate mode, and determine the target rate mode of the eMMC based on the comparison result.

[0104] The rate mode switching module 53 is used to switch the current rate mode of the eMMC to the target rate mode.

[0105] For the principles, implementation details, and beneficial effects of the rate mode control device for this eMMC, please refer to the preceding text. Figures 1 to 3 The description of the rate mode control method for eMMC shown is not repeated here.

[0106] This invention also provides a storage medium, such as a computer-readable storage medium, on which a computer program is stored, the computer program being executed by a processor. Figures 1 to 3The steps of the rate mode control method for eMMC are shown. The computer-readable storage medium may include non-volatile or non-transitory memory, and may also include optical discs, hard disk drives, solid-state drives, etc.

[0107] Specifically, in this embodiment of the invention, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0108] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0109] This invention also provides a terminal, including a memory and a processor. The memory stores a computer program that can run on the processor, and when the processor runs the computer program, it performs the above-described... Figures 1 to 3 The steps of the rate mode control method for eMMC are shown. It should be understood that the term "and / or" in this document is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document indicates that the preceding and following associated objects are in an "OR" relationship.

[0110] In the embodiments of this application, "multiple" refers to two or more.

[0111] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0112] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0113] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A rate mode control method for eMMC, characterized in that, The application is in the Boot loader stage, including: Determine the operating scenario rate mode of the embedded multimedia card eMMC, and determine the highest rate mode supported by the eMMC; The highest rate mode and the working scenario rate mode are compared, and the target rate mode of the eMMC is determined based on the comparison result; Switching the current rate mode of the eMMC to the target rate mode includes: sending a first rate mode switching instruction to the eMMC, the first rate mode switching instruction instructing the eMMC to switch from the current operating rate mode to HS mode; in response to the eMMC successfully switching to HS mode and the target rate mode being HS mode, sending a first bus mode switching instruction to the eMMC, the first bus mode switching instruction instructing the eMMC to switch the current bus transmission mode to the bus transmission mode corresponding to HS mode; in response to the successful bus transmission mode switching, updating the current clock frequency to the clock frequency corresponding to HS mode; whenever it is confirmed that the eMMC has failed to switch to HS mode, repeatedly sending the first rate mode switching instruction to the eMMC until it is confirmed that the eMMC has successfully switched to HS mode or the number of repeated sending reaches a preset number; in response to the number of repeated sending reaching the preset number and the eMMC still failing to switch to HS mode, sending a rate reduction mode switching instruction to the eMMC, the rate reduction mode switching instruction instructing the eMMC to switch from the current operating rate mode to Legacy mode.

2. The method according to claim 1, characterized in that, Determining the target rate mode of the eMMC based on the comparison results includes: If the highest rate mode is the same as the working scenario rate mode, then the working scenario rate mode is taken as the target rate mode of the eMMC. If the highest rate mode is different from the working scenario rate mode, then the mode with the lower rate between the highest rate mode and the working scenario rate mode is selected as the target rate mode of the eMMC.

3. The method according to claim 1 or 2, characterized in that, The highest rate mode and the working scenario rate mode are selected from: Legacy mode, HS mode, HS200 mode, HS400 mode, HS400ES mode.

4. The method according to claim 1, characterized in that, After sending the first rate mode switching instruction, the method further includes: In response to the eMMC successfully switching to HS mode and the rate of the target rate mode being higher than that of HS mode, a second bus mode switching instruction is sent to the eMMC. The second bus mode switching instruction is used to instruct the eMMC to switch the current bus transmission mode to the bus transmission mode corresponding to the target rate mode. In response to a successful bus transmission mode switch, a second rate mode switching instruction is sent to the eMMC, the second rate mode switching instruction being used to instruct the eMMC to switch from HS mode to the target rate mode; In response to the successful switch of the eMMC to the target rate mode, the current clock frequency is updated to the clock frequency corresponding to the target rate mode.

5. The method according to claim 4, characterized in that, The target rate mode is selected from either the HS200 mode or the HS400 mode; After updating the current clock frequency to the clock frequency corresponding to the target rate mode, the method further includes: The transmission delay parameters corresponding to the target rate mode are tuned.

6. The method according to claim 5, characterized in that, Tuning the transmission delay parameters corresponding to the target rate mode includes: The initial value of the preset sampling interval is used as the initial value of the transmission delay parameter; Repeatedly send the tuning template acquisition instruction to the eMMC, wherein after each sending of the tuning template acquisition instruction, the value of the transmission delay parameter is increased by 1 until all values ​​from the initial value to the current value of the transmission delay parameter completely cover the preset sampling interval, and then stop sending the tuning template acquisition instruction. Based on the comparison between the tuning template returned by the eMMC after each transmission of the tuning template acquisition instruction and the pre-stored tuning template, the tuned value of the transmission delay parameter is determined.

7. The method according to claim 6, characterized in that, Based on the tuning template returned by the eMMC after each transmission of the tuning template acquisition command, and the comparison result with the pre-stored tuning template, the tuned value of the transmission delay parameter is determined, including: From the preset sampling interval, select the sub-interval with the highest number of consecutive successful comparisons and the largest total number of successful comparisons; The average or midpoint value of the transmission delay parameters contained in the sub-interval is taken as the tuned value of the transmission delay parameter.

8. The method according to claim 1, characterized in that, Determining the highest rate mode supported by the eMMC includes: Send a data read command to the eMMC, the data read command being used to instruct the eMMC to return the highest rate mode indication data; Based on the received highest rate mode indication data, determine the highest rate mode supported by the eMMC.

9. The method according to claim 1, characterized in that, Determine the operating rate mode of eMMC, including: In response to receiving a work scene switching instruction, determine whether the work scene after the switch indicated by the work scene switching instruction has a predefined scene rate mode; or, in response to receiving a work scene start instruction, determine whether the work scene to be started indicated by the work scene start instruction has a predefined scene rate mode. If the determination result is yes, then the predefined scene rate mode is adopted as the working scene rate mode of the eMMC; If the determination result is negative, then the HS mode is adopted as the target rate mode of the eMMC.

10. The method according to claim 9, characterized in that, The predefined scene rate mode is based on macro definition.

11. A rate mode control device for eMMC, characterized in that, The application is in the Boot loader stage, including: A rate mode determination module is used to determine the working rate mode of the embedded multimedia card eMMC and to determine the highest rate mode supported by the eMMC. A rate mode comparison module is used to compare the highest rate mode with the working scenario rate mode, and determine the target rate mode of the eMMC based on the comparison result. A rate mode switching module is used to switch the current rate mode of the eMMC to the target rate mode, including: sending a first rate mode switching instruction to the eMMC, the first rate mode switching instruction being used to instruct the eMMC to switch from the current operating rate mode to HS mode; in response to the eMMC successfully switching to HS mode and the target rate mode being HS mode, sending a first bus mode switching instruction to the eMMC, the first bus mode switching instruction being used to instruct the eMMC to switch the current bus transmission mode to the bus transmission mode corresponding to HS mode; in response to the successful bus transmission mode switching, updating the current clock frequency to the clock frequency corresponding to HS mode; whenever it is confirmed that the eMMC has failed to switch to HS mode, repeatedly sending the first rate mode switching instruction to the eMMC until it is confirmed that the eMMC has successfully switched to HS mode or the number of repeated sending reaches a preset number; in response to the number of repeated sending reaching the preset number and the eMMC still has not successfully switched to HS mode, sending a rate reduction mode switching instruction to the eMMC, the rate reduction mode switching instruction being used to instruct the eMMC to switch from the current operating rate mode to Legacy mode.

12. A storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by the processor, performs the steps of the rate mode control method for eMMC according to any one of claims 1 to 10.

13. A terminal comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the rate mode control method for eMMC according to any one of claims 1 to 10.

Images