Non-volatile memory cells and related array structures

Abstract

A non-volatile memory cell and its associated array structure are disclosed. The memory cell includes a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and the auxiliary gate region form a capacitor. The floating gate and the erase gate region form another capacitor. The select transistor, the floating gate transistor, and the two capacitors form a four-terminal memory cell, which provides the advantages of a smaller size and easier operation.

Description

Technical Field

[0001] This invention relates to a non-volatile memory, and more particularly to a non-volatile memory cell with a programmable and erasable single polysilicon layer and its associated array structure. Background Technology

[0002] As is well known, a memory cell in non-volatile memory includes a memory cell. For example, a memory cell can be a floating-gate transistor. The storage state of the memory cell is determined by the amount of charge stored in the floating gate of the floating-gate transistor.

[0003] To be compatible with the fabrication process of traditional standard CMOS transistors, it is now possible to design single-poly floating gate transistors in the memory cells of non-volatile memory. By combining floating gate transistors with other electronic components, a single-poly nonvolatile memory cell can be formed.

[0004] US Patent 8,941,167 discloses an erasable programmable single-poly nonvolatile memory. Please refer to... Figure 1A and Figure 1B The diagram shows a top view and equivalent circuit of a conventional single-layer polysilicon non-volatile memory cell. In the following description, the single-layer polysilicon non-volatile memory cell will be simply referred to as a memory cell.

[0005] like Figure 1A As shown, the N-type well region NW1 includes three p-type doped regions 31, 32, and 33. Above the surface between the three p-type doped regions 31, 32, and 33 are two selection gates 34 and a floating gate 36, both composed of polysilicon layers. The floating gate 36 extends outward and is adjacent to the p-type doped region 48 and the n-type doped region 49, which are located within the N-type well region NW2. Additionally, the floating gate 36 is also adjacent to the n-type doped region 53.

[0006] Existing memory cells include: selection transistor M S Floating gate transistor M F p-type transistors and n-type transistors. Among them, the selector transistor M...S With floating gate transistor M F The N-type transistor is fabricated in the N-type well region NW1, the p-type transistor is fabricated in the N-type well region NW2, and the n-type transistor is fabricated in the P-type well region PW (not shown, located below the n-type doped region 53).

[0007] Select transistor M S It consists of a p-type doped region 31, a p-type doped region 32, a select gate 34, and an N-type well region NW1. Floating gate transistor M F It consists of a p-type doped region 32, a p-type doped region 33, a floating gate 36, and an N-type well region NW1. The p-type transistor consists of a floating gate 36 and an erase gate region 45. The n-type transistor consists of a floating gate 36 and an assistant gate region 55. Furthermore, the erase gate region 45 includes an N-type well region NW2, a p-type doped region 48, and an n-type doped region 49. The assistant gate region 55 includes a p-type well region PW and an n-type doped region 53.

[0008] like Figure 1B As shown, select transistor M S The select gate 34 is connected to a select gate voltage V SG Select transistor M S The first drain / source terminal receives the source line voltage V. SL Select transistor M S The body terminal receives the N-type well voltage V. NW1 Floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal receives the bit line voltage V. BL Floating gate transistor M F The body terminal receives the N-type well voltage V. NW1 .

[0009] Furthermore, the p-type doped region 48 can be considered as the two drain / source terminals of a p-type transistor connected to each other, and the body terminal of the p-type transistor receives the N-type well voltage V. NW2 In other words, p-type transistors are connected to form a metal-oxide-semiconductor capacitor (MOS capacitor). MOS1MOS capacitor C MOS1 The first terminal is connected to the floating gate 36, and the MOS capacitor C MOS1 The second terminal receives the erase line voltage V EL .

[0010] Similarly, the n-type doped region 53 can be considered as the two drain / source terminals of an n-type transistor connected to each other, and the body terminal of the n-type transistor receives the voltage V from the P-type well region. PW In other words, the n-type transistors are connected to form a MOS capacitor C. MOS2 MOS capacitor C MOS2 The first terminal is connected to the floating gate 36, and the MOS capacitor C MOS2 The second terminal receives the auxiliary gate voltage V AG .

[0011] Furthermore, an appropriate bias voltage is provided as the selection gate voltage V. SG Source line voltage V SL Line voltage V SL ,Eliminate line voltage V EL Auxiliary gate voltage V AG N-type well voltage V NW1 N-type well voltage V NW2 P-type well voltage V PW It can perform programming, erasing, or reading operations on non-volatile memory units.

[0012] Basically, in the auxiliary gate region 55, the MOS capacitor C MOS2 The second terminal receives the auxiliary gate voltage V AG During programming, erasing, or reading operations, the auxiliary gate voltage V... AG It can be coupled to the floating gate 36 to improve the programming efficiency, erasure efficiency and read speed of the non-volatile memory cell.

[0013] As can be seen from the above description, the existing single polysilicon layer non-volatile memory cell has an auxiliary gate region 55, so the existing memory cell is a five-terminal memory cell. Summary of the Invention

[0014] This invention relates to an array structure of a programmable and erasable single polysilicon layer non-volatile memory cell, the array structure being fabricated on a semiconductor substrate. The array structure includes: an isolation structure formed on the semiconductor substrate, the isolation structure dividing the surface of the semiconductor substrate into a first region and a second region; a well region formed below the surface of the first region of the semiconductor substrate; a first gate structure and a second gate structure formed on the surface of the first region, the first gate structure and the second gate structure dividing the surface of the first region into a first sub-region, a second sub-region, and a third sub-region; wherein the first sub-region is located on a first side of the first gate structure, the second sub-region is located between a second side of the first gate structure and a first side of the second gate structure, and the third sub-region is located on a second side of the second gate structure; the first gate structure is connected to a first select gate line, and a branch of the second gate structure extends outward from the surface of the isolation structure to the second region; the second gate junction... A first portion of the array structure covers a portion of the second region, and a second portion of the second gate structure covers a portion of the third sub-region; a first doped region, a second doped region, and a third doped region are respectively formed below the surfaces of the first sub-region, the second sub-region, and the third sub-region, the first doped region being connected to a first source line, and the third doped region being connected to a first bit line; and a fourth doped region is formed below the surface of the second region and is connected to an erase line; wherein the first doped region, the first gate structure, and the second doped region form a first select transistor; the second doped region, the second gate structure, and the third doped region form a first floating gate transistor; the first portion of the second gate structure and the fourth doped region form a first capacitor; the second portion of the second gate structure and the third doped region form a second capacitor; and a first memory cell of the array structure includes: the first select transistor, the first floating gate transistor, the first capacitor, and the second capacitor.

[0015] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0016] Figure 1A and Figure 1B The top view and equivalent circuit diagram of an existing single polysilicon layer non-volatile memory cell;

[0017] Figures 2A to 2F This is a fabrication process and top view of a single polysilicon layer non-volatile memory cell according to the first embodiment of the present invention;

[0018] Figure 2G The equivalent circuit diagram of the single polysilicon layer non-volatile memory cell in the first embodiment is shown.

[0019] Figures 3A to 3E A bias gauge and related operation diagram for performing programming, erasing and two types of read operations on the storage unit of the first embodiment of the present invention;

[0020] Figure 4A and Figure 4B This is a top view and equivalent circuit diagram of the array structure composed of storage units using the first embodiment of the present invention;

[0021] Figures 5A to 5E This is a top view showing the fabrication process of a single polysilicon layer non-volatile memory cell according to the second embodiment of the present invention;

[0022] Figure 6A and Figure 6B This is a top view and equivalent circuit diagram of the array structure composed of storage units using the second embodiment of the present invention;

[0023] Figure 7 This is a top view of the array structure composed of storage units according to the third embodiment of the present invention;

[0024] Figure 8A and Figure 8B This is a diagram of a single polysilicon layer non-volatile memory cell and its equivalent circuit according to the fourth embodiment of the present invention.

[0025] Figure 8C A schematic diagram of a bias meter for performing programming, erasing, and two types of read operations on the storage unit of the fourth embodiment; and

[0026] Figure 9 This is a schematic diagram of a single polysilicon layer non-volatile memory cell according to the fifth embodiment of the present invention.

[0027] Symbol Explanation

[0028] 31, 32, 33, 48: p-type doped regions

[0029] 34: Select Gate

[0030] 36: Floating gate

[0031] 45: Floating Gate

[0032] 45: Erasure gate region

[0033] 49,53: n-type doped regions

[0034] 55: Auxiliary gate region

[0035] 102,502: Isolation structure

[0036] 103, 105, 503, 505, 801, 901: Gate oxide layer

[0037] 113, 115, 421~428, 451~458, 513, 515, 631~636, 731~733, 811, 911: Polysilicon gate layer

[0038] 123,125,523,525,821,921: Gate structure

[0039] 141~145, 411~419, 431~439, 461, 462, 541~545, 611~627, 711~719: n-type doped regions Detailed Implementation

[0040] Figures 2A to 2F This is a top view showing the fabrication process of a single polysilicon layer non-volatile memory cell according to the first embodiment of the present invention. Figure 2G This is the equivalent circuit of a single polysilicon layer non-volatile memory cell according to the first embodiment of the present invention. In the following description, the single polysilicon layer non-volatile memory cell will be simply referred to as a memory cell.

[0041] like Figure 2A The diagram illustrates the steps involved in forming the isolation structure. This isolation structure can be a shallow trench isolation (STI) structure. First, an isolation structure 102 is formed on a p-substrate, defining regions A and B. That is, the p-substrate is covered by the isolation structure 102, with only regions A and B exposing the surface of the p-substrate. Region B is a rectangular region, and region A consists of two rectangular sub-regions A1 and A2. In subsequent fabrication processes, region A will form two cascaded n-type transistors and an assistant gate region, while region B will form an erase gate region.

[0042] Next, the trap formation step is performed. For example... Figure 2B As shown, region A is exposed and a P-type well region PW is formed. Therefore, a P-type well region PW is formed below region A on the surface of the p-type substrate (p-sub). Alternatively, a well region may not be formed below region B. Of course, in other embodiments, another P-type well region PW (not shown) may be formed below region B, or an N-type well region (not shown) may be formed below region B.

[0043] Next, the gate structure formation step is performed. For example... Figure 2CAs shown, two gate oxide layers 103 and 105 are first formed. Then, polysilicon gate layers 113 and 115 are formed to cover the two gate oxide layers 103 and 105 respectively, forming two gate structures 123 and 125.

[0044] exist Figure 2C In this design, two gate structures 123 and 125 are formed on the surface of region A, dividing region A into three sub-regions. More specifically, both gate structures 123 and 125 are formed on the surface of region A1. The left side of gate structure 123 is the first sub-region, the right side of gate structure 123 and the area between it and the left side of gate structure 125 is the second sub-region, and the right side of gate structure 125 (including sub-region A2) is the third sub-region. In other words, the third sub-region is an L-shaped sub-region.

[0045] Furthermore, the branch extending outward from the gate structure 125 via the surface of the isolation structure 102 includes two extension segments. The first extension segment of the gate structure 125 extends to region B and covers a portion of region B. The second extension segment of the gate structure 125 extends to sub-region A2 within region A and covers a portion of sub-region A2. According to an embodiment of the present invention, the polysilicon gate layer 115 of the gate structure 125 is a floating gate. The polysilicon gate layer 113 in the other gate structure 123 is a select gate.

[0046] Next, the doped region formation step is performed. For example... Figure 2D As shown, the surface of the p-type substrate (p-sub) is doped using two gate structures 123 and 125 as masks. Therefore, the portion of region B not covered by gate structure 125 forms an n-type doped region 145. The three sub-regions of region A not covered by the two gate structures 123 and 125 form three n-type doped regions 141, 142, and 143.

[0047] In region A, gate structure 123 and its two n-type doped regions 141 and 142 form a select transistor. Gate structure 125 and its two n-type doped regions 142 and 143 form a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors fabricated within the P-type well region PW. That is, the body terminals of the floating gate transistor and the select transistor are connected to the P-type well region PW.

[0048] Furthermore, the n-type doped region 143, in addition to serving as a drain / source terminal of the floating gate transistor, can also serve as an auxiliary gate region. That is, the second extension branch of the gate structure 125 extends outward and is adjacent to the auxiliary gate region. Therefore, the auxiliary gate region and the gate structure 125 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0049] Furthermore, the n-type doped region 145 in region B is the erased gate region, and the first extension branch of the gate structure 125 extends outward and is adjacent to the erased gate region. Therefore, the erased gate region and the gate structure 125 form an n-type transistor, and the n-type transistor is connected to form another MOS capacitor.

[0050] like Figure 2E As shown, the connection line step is performed to complete the memory cell of this embodiment of the invention. That is, the n-type doped region 141 is connected to the source line SL, the n-type doped region 143 is connected to the bit line BL, the n-type doped region 145 is connected to the erase line EL, and the polysilicon gate layer 113 is connected to the select gate line SG.

[0051] Furthermore, the special design of the storage unit in this invention allows for better programming and erasing efficiency; however, this invention is not limited to this special design. For example, in... Figure 2F In the middle, there are two overlapping regions A between the polysilicon gate layer 115 and region A. MF A AG Overlapping region A MF Located below the polysilicon gate layer 115, between the n-type doped regions 142 and 143, this is the channel region of the floating gate transistor, which is also the active region of the floating gate transistor. Overlapping region A AG Located in the third sub-region of region A, below the polysilicon gate layer 115 and adjacent to the n-type doped region 143 on three sides, it serves as the functional region of the auxiliary gate region. Furthermore, there is an overlapping region A between the polysilicon gate layer 115 and region B. EG Overlapping region A EG Located within region B, below the polysilicon gate layer 115, and adjacent to the n-type doped region 145 on three sides, it serves as the functional region for erasing the gate region. The area A of the functional region of the auxiliary gate region is... AG The area A of the active region of the erased gate region is greater than the area of ​​the active region. EG That is, A AG >A EG Additionally, the area A of the auxiliary gate region is... AG Add the area A of the gate region's active region EG It will be larger than the area A of the active region of the floating gate transistor.MF That is, (A) AG +A EG A MF .

[0052] Furthermore, the special design in the storage unit of this invention allows for a smaller storage unit size; however, this invention is not limited to this special design. For example, in Figure 2F In this design, the channel region of the floating gate transistor is oriented in the wx direction (e.g., horizontal direction). The extension direction of the second extension branch of the polysilicon gate layer 115 (or gate structure 125) is the yz direction (e.g., horizontal direction). In other words, in the design of the polysilicon gate layer 115, the extension direction of the second extension branch is the same as the channel region direction of the floating gate transistor.

[0053] like Figure 2G As shown, the equivalent circuit of the memory cell in the first embodiment of the present invention includes: a selection transistor M S A floating gate transistor M F A capacitor C EG With a capacitor C AG Among them, capacitor C EG C AG It is a MOS capacitor.

[0054] Select transistor M S The gate terminal is connected to a select gate line SG, and the select transistor M S The first drain / source terminal is connected to the source line SL. Floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal is connected to the bit line BL. Capacitor C EG The first terminal is connected to the floating gate transistor M F Floating gate 115, capacitor C EG The second terminal is connected to the erase line EL. Capacitor C AG The first terminal is connected to the floating gate transistor M F Floating gate 115, capacitor C AG The second end is connected to the bit line BL.

[0055] As can be seen from the above description, the memory cell in this embodiment of the invention has an auxiliary gate region and an erase gate region. Compared to Figure 1A The storage unit of the present invention is a four-terminal storage unit and has a small size.

[0056] Please refer to Figures 3A to 3EThe diagram shows a bias table and related operation schematics of the storage unit performing programming (PGM), erasure (ERS) and two read operations (Read_1 and Read_2) according to the first embodiment of the present invention.

[0057] During programming (PGM), erasure (ERS), and two read operations (Read_1 and Read_2), the P-type well region PW receives a ground voltage (0V). Additionally, the erasure voltage V... EE Greater than the programming voltage V PP Programming voltage V PP Greater than the reading voltage V R Read voltage V R Greater than the ground voltage (0V). For example, the erase voltage V EE 12V, programming voltage V PP It is 9V, read the voltage V R It is 5V.

[0058] like Figure 3B As shown, during programming operation (PGM), the bit line BL receives the programming voltage V. PP The source line SL receives the ground voltage (0V), and the select gate line SG receives the programming voltage V. PP The voltage received by the erase line EL can be set between the ground voltage (0V) and the erase voltage V. EE between.

[0059] When programming, select transistor M. S When the bit line BL is turned on, a programming current I is generated between the bit line BL and the source line SL. P Therefore, when the programming current I... P Hot carriers (e.g., electrons) pass through the floating gate transistor M F When the channel region is reached, the channel hot electron injection effect (CHE effect) occurs, causing hot carriers to be injected into the floating gate 115. Among these, capacitor C... AG The programming voltage V received by the bit line BL can be pp By coupling to the floating gate 115, the number of hot carriers injected into the floating gate 115 can be increased, thereby improving programming efficiency.

[0060] like Figure 3C As shown, during the erase operation (ERS), the bit line BL receives the ground voltage (0V), the source line SL receives the ground voltage (0V), the select gate line SG receives the ground voltage (0V), and the erase line EL receives the erase voltage V. EE .

[0061] During the erase operation, select transistor M. S Turn off. At this time, capacitor C EG The FN tunneling effect is generated at both ends, and hot carriers are ejected from the floating gate 115 to the erase line EL.

[0062] like Figure 3D As shown, during the first read operation (Read_1), the bit line BL receives the read voltage V. R The source line SL receives the ground voltage (0V), and the select gate line SG receives the read voltage V. R The voltage received by the erase line EL can be set between the ground voltage (0V) and the erase voltage V. EE between.

[0063] In the first read operation, transistor M is selected. S When the bit line BL is turned on, a read current I is generated between the bit line BL and the source line SL. R Read current I R The current flows from the bit line BL to the source line SL. And according to the read current I... R The size of the current determines the storage state of the memory cell. For example, when electrons are stored in the floating gate 115, the read current I... R Very small, almost zero, the visible memory cell is in its first storage state. When no electrons are stored in the floating gate 115, the read current I... R The size is relatively large, and the visible storage unit is in the second storage state.

[0064] like Figure 3E As shown, during the second read operation (Read_2), the source line SL receives the read voltage V. R Bit line BL receives ground voltage (0V), select gate line SG receives read voltage V. R The voltage received by the erase line EL can be set between the ground voltage (0V) and the erase voltage V. EE between.

[0065] In the second read operation, transistor M is selected. S When the bit line BL is turned on, a read current I is generated between the bit line BL and the source line SL. R Read current I R The current flows from the source line SL to the bit line BL. And according to the read current I... R The size of the current determines the storage state of the memory cell. For example, when electrons are stored in the floating gate 115, the read current I... RVery small, almost zero, the visible memory cell is in its first storage state. When no electrons are stored in the floating gate 115, the read current I... R The size is relatively large, and the visible storage unit is in the second storage state.

[0066] Furthermore, multiple storage units can be arranged into an array structure. Please refer to [link / reference]. Figure 4A and Figure 4B The diagram illustrates a top view and equivalent circuit of an array structure composed of memory cells according to the first embodiment of the present invention. The array structure consists of 2×4 memory cells from the first embodiment, connected to source lines SL1-SL2, select gate lines SG1-SG4, bit lines BL1-BL2, and erase line EL. The array structure includes: n-type doped regions 411-419, 431-439, and 461-462, and polysilicon gate layers 421-428 and 451-458.

[0067] In some embodiments, in order to perform Figure 3D The first reading action described can... Figure 4B The source lines SL1 and SL2 are interconnected. In another part of the implementation, in order to perform... Figure 3E The second reading action described can... Figure 4B Bit lines BL1 and BL2 are interconnected.

[0068] Because the structure of each storage unit is similar to Figure 2E The following only describes storage unit c22; the other storage units will not be discussed further. Figure 4A In the memory cell c22 shown, n-type doped regions 433 and 434 and the polysilicon gate layer 453 form a selection transistor. n-type doped regions 434 and 435 and the polysilicon gate layer 454 form a floating gate transistor. The polysilicon gate layer 454 and the n-type doped region 461 form an n-type transistor and are connected to form a MOS capacitor. The polysilicon gate layer 454 and the n-type doped region 435 form an n-type transistor and are connected to form a MOS capacitor.

[0069] Next, n-type doped region 433 is connected to source line SL2, n-type doped region 435 is connected to bit line BL2, polysilicon gate layer 453 is connected to select gate line SG2, and n-type doped region 461 is connected to erase line EL.

[0070] like Figure 4B The equivalent circuit of the array structure is shown below. The array structure consists of 2×4 memory cells c11 to c24. Since the structure of each memory cell c11 to c24 is similar, only memory cell c11 will be described below, and the other memory cells will not be described in detail.

[0071] In memory cell C11, select transistor M SThe first drain / source terminal is connected to the source line SL1, selecting transistor M. S The gate terminal is connected to the select gate line SG1, and the floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal is connected to bit line BL1, capacitor C EG The first terminal is connected to the floating gate transistor M F Floating gate, capacitor C EG The second terminal is connected to the erase line EL, capacitor C AG The first terminal is connected to the floating gate transistor M F Floating gate, capacitor C AG The second end is connected to bit line BL1.

[0072] Similar to Figure 3A The biasing method provides appropriate bias to the source lines SL1-SL2, selects the gate lines SG1-SG4, bit lines BL1-BL2, and erase line EL. Programming, erasing, and reading operations can be performed on the memory cells c11-c24 in the array structure. Further details are omitted here.

[0073] Furthermore, the memory cell in this invention is implemented using an n-type transistor. However, this invention is not limited to this. Those skilled in the art can, based on the description in the first embodiment, use p-type transistors instead of n-type transistors to complete the memory cell and array structure of this invention.

[0074] Figures 5A to 5E This is a top view showing the fabrication process of a single polysilicon layer non-volatile memory cell according to the second embodiment of the present invention.

[0075] like Figure 5A The diagram illustrates the steps involved in forming the isolation structure. This isolation structure can be a shallow trench isolation (STI) structure. First, an isolation structure 502 is formed on the p-substrate, defining regions A and B. That is, the p-substrate is covered by the isolation structure 502, with only regions A and B exposing the surface of the p-substrate. In subsequent fabrication processes, region A will form two cascaded n-type transistors and an assistant gate region, while region B will form an erase gate region.

[0076] Next, the trap formation step is performed. For example... Figure 5AAs shown, region A is exposed and a P-type well region PW is formed. Therefore, a P-type well region PW is formed below region A on the surface of the p-type substrate (p-sub). Alternatively, a well region may not be formed below region B. Of course, in other embodiments, another P-type well region PW (not shown) may be formed below region B, or an N-type well region (not shown) may be formed below region B.

[0077] Next, the gate structure formation step is performed. For example... Figure 5B As shown, two gate oxide layers 503 and 505 are first formed. Then, polysilicon gate layers 513 and 515 are formed to cover the two gate oxide layers 503 and 505 respectively, forming two gate structures 523 and 525.

[0078] exist Figure 5B In this structure, two gate structures 523 and 525 are formed on the surface of region A, dividing region A into four sub-regions. Specifically, the right side of gate structure 523 is the first sub-region, the area between the left side of gate structure 523 and the left side of gate structure 525 is the second sub-region, and the two sides of the extension segment of gate structure 525 are the third and fourth sub-regions.

[0079] According to a second embodiment of the present invention, the polysilicon gate layer 515 of the gate structure 525 is a floating gate. The polysilicon gate layer 513 in the other gate structure 523 is a select gate.

[0080] Next, the doped region formation step is performed. For example... Figure 5C As shown, the surface of the p-type substrate (p-sub) is doped using two gate structures 523 and 525 as masks. Therefore, the portion of region B not covered by gate structure 525 forms an n-type doped region 545. The four sub-regions of region A not covered by the two gate structures 523 and 525 form four n-type doped regions 541, 542, 543, and 544.

[0081] In region A, gate structure 523 and its two n-type doped regions 541 and 542 form a select transistor. Gate structure 525 and its two n-type doped regions 542 and 543 form a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors fabricated within the P-type well region PW. That is, the body terminals of the floating gate transistor and the select transistor are connected to the P-type well region PW.

[0082] Furthermore, the n-type doped region 543, besides serving as a drain / source terminal of the floating gate transistor, can also serve as an auxiliary gate region. That is, the branch of the gate structure 525 extends and is adjacent to the auxiliary gate region. Therefore, the auxiliary gate region and the gate structure 525 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0083] Furthermore, the n-type doped region 545 in region B is the erased gate region, and the branches of the gate structure 525 extend outward and are adjacent to the erased gate region. Therefore, the erased gate region and the gate structure 525 form an n-type transistor, and the n-type transistor is connected to form another MOS capacitor.

[0084] Notably, in another embodiment, the branches of the gate structure 525 can be designed to cover region A and extend along the edge of region A to region B. In this case, region A is only divided into three sub-regions. However, after the doping region formation step, only three n-type doped regions 541, 542, and 543 will be formed, lacking the required doping region. Figure 5C The n-type doped region 544 in the middle.

[0085] like Figure 5D As shown, the connection line step is performed to complete the memory cell of this embodiment of the invention. That is, the n-type doped region 541 is connected to the source line SL, the n-type doped region 543 is connected to the bit line BL, the n-type doped region 545 is connected to the erase line EL, and the polysilicon gate layer 513 is connected to the select gate line SG.

[0086] The equivalent circuit of the storage unit in the second embodiment of the present invention is a four-terminal storage unit, which is the same as... Figure 2G This will not be elaborated upon here.

[0087] Furthermore, the special design of the storage unit in this invention allows for better programming and erasing efficiency; however, this invention is not limited to this special design. For example, in... Figure 5E In the middle, there are two overlapping regions A between the polysilicon gate layer 515 and region A. MF A AG Overlapping region A MF Located below the polysilicon gate layer 515, between the n-type doped regions 542 and 543, this is the channel region of the floating gate transistor, which is also the active region of the floating gate transistor. Overlapping region A AG Located below the branch of the polysilicon gate layer 515 and adjacent to the n-type doped regions 543 and 544, it serves as the functional region of the auxiliary gate region. Furthermore, there is an overlapping region A between the polysilicon gate layer 515 and region B. EG Overlapping region A EGLocated within region B, below the polysilicon gate layer 515, and adjacent to the n-type doped region 545 on three sides, it serves as the functional region for erasing the gate region. The area A of the functional region of the auxiliary gate region is... AG The area A of the active region of the erased gate region is greater than the area of ​​the active region. EG That is, A AG >A EG Additionally, the area A of the auxiliary gate region is... AG Add the area A of the gate region's active region EG It will be larger than the area A of the active region of the floating gate transistor. MF That is, (A) AG +A EG A MF .

[0088] Furthermore, the special design in the storage unit of this invention allows for a smaller storage unit size; however, this invention is not limited to this special design. For example, in Figure 5E In this design, the channel region of the floating gate transistor is oriented in the wx direction (e.g., horizontal direction). The branch extension direction of the polysilicon gate layer 515 (or gate structure 525) is in the yz direction (e.g., horizontal direction). In other words, in the design of the polysilicon gate layer 515, the branch extension direction is the same as the channel region direction of the floating gate transistor.

[0089] Furthermore, multiple storage units can be arranged into an array structure. Please refer to [link / reference]. Figure 6A and Figure 6B The diagram illustrates a top view and equivalent circuit of an array structure composed of memory cells from the second embodiment of the present invention. The array structure consists of 2×2 memory cells from the second embodiment, connected to source lines SL1-SL2, select gate lines SG1-SG2, bit lines BL1-BL2, and erase line EL. The array structure includes: n-type doped regions 621-627 and polysilicon gate layers 631-636.

[0090] Because the structure of each storage unit is similar to Figure 5E The following only describes storage unit c12; the other storage units will not be discussed further. Figure 5A In the memory cell c12 shown, n-type doped regions 611 and 612 and the polysilicon gate layer 631 form a selection transistor. n-type doped regions 612 and 613 and the polysilicon gate layer 632 form a floating gate transistor. The polysilicon gate layer 632 and the n-type doped region 627 form an n-type transistor and are connected as a MOS capacitor. The polysilicon gate layer 632 and the n-type doped region 613 form an n-type transistor and are connected as a MOS capacitor.

[0091] Next, n-type doped region 611 is connected to source line SL1, n-type doped region 613 is connected to bit line BL1, polysilicon gate layer 632 is connected to select gate line SG2, and n-type doped region 627 is connected to erase line EL.

[0092] like Figure 6B The equivalent circuit of the array structure is shown below. The array structure consists of 2×2 memory cells c11 to c22. Since the structure of each memory cell c11 to c22 is similar, only memory cell c11 will be described below, and the other memory cells will not be described in detail.

[0093] In memory cell C11, select transistor M S The first drain / source terminal is connected to the source line SL1, selecting transistor M. S The gate terminal is connected to the select gate line SG1, and the floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal is connected to bit line BL1, capacitor C EG The first terminal is connected to the floating gate transistor M F Floating gate, capacitor C EG The second terminal is connected to the erase line EL, capacitor C AG The first terminal is connected to the floating gate transistor M F Floating gate, capacitor C AG The second end is connected to bit line BL1.

[0094] Similar to Figure 3A The biasing method provides appropriate bias to the source lines SL1-SL2, selects the gate lines SG1-SG2, bit lines BL1-BL2, and erase line EL. This allows for programming, erasing, and reading operations on the memory cells c11-c22 in the array structure. The magnitude of the bias provided can be referenced... Figure 3A and Figure 4B This will not be elaborated upon here.

[0095] In some embodiments, in order to perform Figure 3D The first reading action described can... Figure 6B The source lines SL1 and SL2 are interconnected. In another part of the implementation, in order to perform... Figure 3E The second reading action described can... Figure 6B Bit lines BL1 and BL2 are interconnected.

[0096] Please refer to Figure 7The diagram shows a top view of an array structure composed of memory cells according to the third embodiment of the present invention. The array structure includes: n-type doped regions 711-719 and polysilicon gate layers 731-733. Furthermore, the memory cells of the third embodiment are similar to those of the second embodiment, as described below.

[0097] exist Figure 6A In the second embodiment, the n-type doped region 613 of memory cell c12 and the n-type doped region 617 of the adjacent memory cell are connected by a metal wire, namely a bit line BL1. Compared to Figure 6A The array structure composed of storage units in the second embodiment Figure 7 In the disclosed array structure, in the third embodiment, memory cell c12 and adjacent memory cell c22 share an n-type doped region 713, and in the third embodiment, memory cell c11 and adjacent memory cell c21 share an n-type doped region 719. The n-type doped regions 713 and 719 are connected to each other by metal wires, i.e. bit lines BL.

[0098] Furthermore, the equivalent circuit of the memory cell in the third embodiment is similar to that of the memory cell in the second embodiment. The equivalent circuit of the column structure composed of the memory cells in the third embodiment is also similar to that of the column structure composed of the memory cells in the second embodiment. Further details will not be provided here.

[0099] Similarly, provide appropriate bias to source lines SL1-SL2, select gate lines SG1-SG2, bit lines BL1-BL2, and erase line EL. This allows for... Figure 7 The memory cells c11 to c22 in the array structure perform programming, erasing, and reading operations. The magnitude of the bias voltage can be referenced. Figure 3A .in addition, Figure 7 In the array structure, memory cells c11 to c22 are all connected to bit line BL, thus effectively reducing the size of the array structure. Therefore, during read operations, the size of the array can be reduced. Figure 3E The second read operation uses a bias method to read the array structure.

[0100] Please refer to Figure 8A and Figure 8B The diagram shown is a single polysilicon layer non-volatile memory cell and its equivalent circuit diagram according to the fourth embodiment of the present invention. Please refer to... Figure 8C The diagram shows the bias table for the memory cell performing programming (PGM), erasure (ERS) and two read operations (Read_1 and Read_2) according to the fourth embodiment of the present invention.

[0101] Compared to Figure 2E The first embodiment of the storage unit, Figure 8AThe fourth embodiment of the memory cell further includes a gate structure 821. This gate structure 821 is located on the isolation structure 102, adjacent to the side of the gate structure 125. The gate structure 821 includes a gate oxide layer 801 and a polysilicon gate layer 811. The gate oxide layer 801 is located on the isolation structure 102, and the polysilicon gate layer 811 covers the gate oxide layer 801. Furthermore, the polysilicon gate layer 811 and the polysilicon gate layer 115 can form a polysilicon / polysilicon planar capacitor, and the polysilicon gate layer 811 is connected to the auxiliary gate line AG.

[0102] like Figure 8B As shown, polycrystalline silicon / polycrystalline silicon planar capacitor C AGP The first terminal is connected to the floating gate transistor M F Floating gate 115, polysilicon / polysilicon planar capacitor C AGP The second end is connected to the auxiliary gate line AG.

[0103] In addition, compared to Figure 3A Bias gauge, Figure 8C The bias table also includes the bias voltage for the auxiliary gate line AG. Only the bias voltage for the auxiliary gate line AG will be described below; other bias voltages will not be discussed further.

[0104] During programming operation (PGM), the voltage received by the auxiliary gate line AG is between ground voltage (0V) and positive auxiliary gate voltage V. AG Between. During the erase operation (ERS), the voltage received by the auxiliary gate line AG is between the negative auxiliary gate voltage -V. AG Between the voltage and ground (0V). During the first read operation (Read_1), the voltage received by the auxiliary gate line AG is between the negative auxiliary gate voltage -V. AG With positive auxiliary gate voltage V AG Between. During the second read operation (Read_2), the voltage received by the auxiliary gate line AG is between the negative auxiliary gate voltage -V. AG With positive auxiliary gate voltage V AG Between. For example, a positive auxiliary gate voltage V AG It is 10V.

[0105] Please refer to Figure 9 The illustration shows a single polysilicon layer non-volatile memory cell according to the fifth embodiment of the present invention.

[0106] Compared to Figure 5D The second embodiment of the storage unit, Figure 9The fifth embodiment of the memory cell further includes a gate structure 921. This gate structure 921 is located on the isolation structure 502, one side of the gate structure 525. The gate structure 921 includes a gate oxide layer 901 and a polysilicon gate layer 911. The gate oxide layer 901 is located on the isolation structure 502, and the polysilicon gate layer 911 covers the gate oxide layer 901. Furthermore, the polysilicon gate layer 911 and the polysilicon gate layer 515 can form a polysilicon / polysilicon planar capacitor, and the polysilicon gate layer 911 is connected to the auxiliary gate line AG. Additionally, in the array structure composed of the memory cells of the fifth embodiment, Figure 9 The memory cells can also share this gate structure 921 with adjacent memory cells.

[0107] Furthermore, the equivalent circuit of the storage cell in the fifth embodiment is the same as... Figure 8B The equivalent circuit of the memory cell in the fourth embodiment. The bias voltage of the memory cell in the fifth embodiment during programming, erasing, and reading operations is also similar. Figure 8C The bias gauge will not be described in detail here.

[0108] As described above, this invention proposes a programmable and erasable single polysilicon layer non-volatile memory cell and its associated array structure. The memory cell includes a select transistor and a floating gate transistor. The floating gate and auxiliary gate regions of the floating gate transistor form a capacitor, and the floating gate and erase gate regions form another capacitor. Furthermore, the select transistor, the floating gate transistor, and the two capacitors constitute a four-terminal memory cell, giving the memory cell the advantages of small size and ease of operation.

[0109] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An array structure of programmable and erasable single polysilicon layer nonvolatile memory cells fabricated on a semiconductor substrate, the array structure comprising: an isolation structure formed on the semiconductor substrate and dividing a surface of the semiconductor substrate into a first region and a second region; a well region formed under a surface of the first region of the semiconductor substrate; a first gate structure and a second gate structure formed on a surface of the first region and dividing the surface of the first region into a first sub-region, a second sub-region and a third sub-region, wherein the first sub-region is located at a first side of the first gate structure, the second sub-region is located between a second side of the first gate structure and a first side of the second gate structure, and the third sub-region is located at a second side of the second gate structure, the first gate structure is connected to a first select gate line, a branch of the second gate structure extends outwardly via a surface of the isolation structure, a first portion of the second gate structure covers part of the second region, and a second portion of the second gate structure covers part of the third sub-region; a first doped region, a second doped region and a third doped region formed under surfaces of the first sub-region, the second sub-region and the third sub-region, respectively, the first doped region is connected to a first source line, and the third doped region is connected to a first bit line; and a fourth doped region formed under a surface of the second region, and the fourth doped region is connected to an erase line; wherein the first doped region, the first gate structure and the second doped region form a first select transistor, the second doped region, the second gate structure and the third doped region form a first floating gate transistor, the first portion of the second gate structure and the fourth doped region form a first capacitor, the second portion of the second gate structure and the third doped region form a second capacitor, and a first memory cell of the array structure comprises the first select transistor, the first floating gate transistor, the first capacitor and the second capacitor; wherein the array structure further comprises a second memory cell, the second memory cell comprises a second select transistor, a second floating gate transistor, a third capacitor and a fourth capacitor, a gate terminal of the second select transistor is connected to a second select gate line, a first drain / source terminal of the second select transistor is connected to the first source line, a first drain / source terminal of the second floating gate transistor is connected to a second drain / source terminal of the second select transistor, a second drain / source terminal of the second floating gate transistor is connected to the first bit line, a first terminal of the third capacitor is connected to a floating gate of the second floating gate transistor, a second terminal of the third capacitor is connected to the erase line, a first terminal of the fourth capacitor is connected to the floating gate of the second floating gate transistor, and a second terminal of the fourth capacitor is connected to the first bit line.

2. The array structure of claim 1, wherein, The first storage unit includes a first select transistor, a first floating gate transistor, a first capacitor, and a second capacitor. The gate terminal of the first select transistor is connected to the first select gate line, the first drain / source terminal of the first select transistor is connected to the first source line, the first drain / source terminal of the first floating gate transistor is connected to the second drain / source terminal of the first select transistor, the second drain / source terminal of the first floating gate transistor is connected to the first bit line, the first terminal of the first capacitor is connected to the floating gate of the first floating gate transistor, the second terminal of the first capacitor is connected to the erase line, the first terminal of the second capacitor is connected to the floating gate of the first floating gate transistor, and the second terminal of the second capacitor is connected to the first bit line.

3. The array structure of claim 2, further comprising a third memory cell comprising: A third select transistor, a third floating gate transistor, a fifth capacitor, and a sixth capacitor. The gate terminal of the third select transistor is connected to the first select gate line, the first drain / source terminal of the third select transistor is connected to the second source line, the first drain / source terminal of the third floating gate transistor is connected to the second drain / source terminal of the third select transistor, the second drain / source terminal of the third floating gate transistor is connected to the second bit line, the first terminal of the fifth capacitor is connected to the floating gate of the third floating gate transistor, the second terminal of the fifth capacitor is connected to the erase line, the first terminal of the sixth capacitor is connected to the floating gate of the third floating gate transistor, and the second terminal of the sixth capacitor is connected to the second bit line.

4. The array structure of claim 1, wherein the first select transistor and the first floating gate transistor are n-type transistors.

5. The array structure of claim 1, wherein the first gate structure includes a first gate oxide layer and a first polysilicon gate layer, and the second gate structure includes a second gate oxide layer and a second polysilicon gate layer.

6. The array structure of claim 5, wherein in the third sub-region, a first active region of the auxiliary gate region is located under the second polysilicon gate layer; in the second region, a second active region of the erase gate region is located under the second polysilicon gate layer; and the area of the first active region is greater than the area of the second active region.

7. The array structure of claim 5, wherein in the third sub-region, a first active region of the auxiliary gate region is located under the second polysilicon gate layer; in the second region, a second active region of the erase gate region is located under the second polysilicon gate layer; a third active region of the first floating gate transistor is located under the second polysilicon gate layer and between the second doped region and the third doped region; and the area of the first active region plus the area of the second active region is greater than the area of the third active region.

8. The array structure of claim 5, wherein a channel region of the first floating gate transistor is located under the second polysilicon gate layer and between the second doped region and the third doped region; and the extension direction of the branch of the second gate structure is the same as the direction of the channel region.

9. The array structure of claim 1, wherein during a program operation, the first source line receives a ground voltage, the first select gate line receives a program voltage, the first bit line receives the program voltage, the erase line receives a first voltage in a range between the ground voltage and an erase voltage, the erase voltage being greater than the program voltage, the program voltage being greater than the ground voltage.

10. The array structure of claim 1, wherein during an erase operation, the first source line receives a ground voltage, the first select gate line receives the ground voltage, the first bit line receives the ground voltage, the erase line receives an erase voltage, the erase voltage being greater than the ground voltage.

11. The array structure of claim 1, wherein during a read operation, the first source line receives a ground voltage, the first select gate line receives a read voltage, the first bit line receives the read voltage, the erase line receives a first voltage in a range between the ground voltage and the read voltage, the read voltage being greater than the ground voltage.

12. The array structure of claim 1, wherein during a read operation, the first source line receives a read voltage, the first select gate line receives the read voltage, the first bit line receives a ground voltage, the erase line receives a first voltage in a range between the ground voltage and the read voltage, the read voltage being greater than the ground voltage.

13. The array structure of claim 1, wherein the array structure further comprises a third gate structure formed on the isolation structure, and the third gate structure is located on one side of the branch of the second gate structure.

14. The array structure of claim 13, wherein the second gate structure and the third gate structure form a poly / poly planar capacitor, a first end of the poly / poly planar capacitor is connected to a floating gate of the first floating gate transistor, a second end of the poly / poly planar capacitor is connected to an auxiliary gate line.

15. The array structure of claim 1, wherein the branch comprises a first extended branch and a second extended branch, the first extended branch is located on a first side of the second gate structure, the second extended branch is located on a second side of the second gate structure.

16. The array structure of claim 1, wherein the branch extends from the second gate structure and through the third doped region and the surface of the isolation structure to the fourth doped region.

17. The array structure of claim 16, wherein a second region is located on the second side of the second gate structure.

18. The array structure of claim 1, further comprising a third memory cell comprising: The first gate structure and the third gate structure are formed on the surface of the first region, and the first gate structure and the third gate structure further divide the surface of the first region into a fourth sub-region and a fifth sub-region, wherein the fourth sub-region is located at the first side of the first gate structure, the fifth sub-region is located between the second side of the first gate structure and the first side of the third gate structure, the third sub-region is located at the second side of the third gate structure, the first part of the third gate structure extends outward and covers the second region, and the second part of the third gate structure covers the third sub-region; The fifth doped region, the sixth doped region and the third doped region are respectively formed below the surfaces of the fourth sub-region, the fifth sub-region and the third sub-region, the fifth doped region is connected to the second source line, and the third doped region is connected to the first bit line; and The fourth doped region is formed below the surface of the second region, and the fourth doped region is connected to the erase line. The fifth doped region, the first gate structure and the sixth doped region form a third selection transistor; the sixth doped region, the third gate structure and the third doped region form a third floating gate transistor; the first part of the third gate structure and the fourth doped region form a fifth capacitor; and the second part of the third gate structure and the third doped region form a sixth capacitor.

19. The array structure of claim 18, further comprising a fourth memory cell comprising: The fourth selection transistor, the fourth floating gate transistor, the seventh capacitor and the eighth capacitor, the gate terminal of the fourth selection transistor is connected to a second selection gate line, the first drain / source terminal of the fourth selection transistor is connected to the second source line, the first drain / source terminal of the fourth floating gate transistor is connected to the second drain / source terminal of the fourth selection transistor, the second drain / source terminal of the fourth floating gate transistor is connected to a second bit line, the first terminal of the seventh capacitor is connected to the floating gate of the fourth floating gate transistor, the second terminal of the seventh capacitor is connected to the erase line, the first terminal of the eighth capacitor is connected to the floating gate of the fourth floating gate transistor, and the second terminal of the eighth capacitor is connected to the second bit line.

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