Processor-based devices, methods, and computer-readable media

Abstract

Tracking repeated reads in a processor-based device to guide dynamic selection of cache coherency protocols is disclosed. In this regard, the processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects a write-invalidate protocol or a write-update protocol on a per-store basis as a cache coherency protocol for maintaining cache coherency of memory store operations. The COP's selection is based on protocol preference indicators generated by the PEs using repeated read indicators that each PE maintains to track whether a coherency granule is repeatedly read by the PE (e.g., as a result of a polling read, or as a result of re-reading a coherency granule after the coherency granule is evicted from a cache due to an invalidate snoop). After selecting a cache coherency protocol, the COP sends a response message to the PEs indicating the selected cache coherency protocol.

Description

Technical Field

[0001] The technology disclosed herein relates to cache coherence protocols in processor-based devices, and more specifically, to the dynamic selection of cache coherence protocols. Background Technology

[0002] Processor-based devices may include multiple processing elements (PEs) (e.g., processor cores as a non-limiting example), each of which provides one or more local caches for storing frequently accessed data. Because the multiple PEs of a processor-based device can share memory resources such as system memory, multiple copies of shared data read from a given memory address can exist simultaneously in system memory and in the PE's local cache. Therefore, to ensure that all PEs have a consistent view of the shared data, processor-based devices provide support for cache coherency protocols, enabling local changes to shared data within one PE to propagate to other PEs. In this way, conflicts that may arise between PEs due to inconsistencies between local copies of shared data can be avoided.

[0003] Traditional cache coherence protocols include write-invalidate protocols and write-update protocols. Under the write-invalidate protocol, when a PE writes to a coherence granule (representing a byte-aligned partition of system memory that manages cache coherence), all copies of the coherence granule stored in the local caches of other PEs are invalidated, where dirty (i.e., modified) copies of the coherence granule are written to system memory before being invalidated. PEs that lose their cache copies of the coherence granule in this way can subsequently regain their copies via a memory load operation after the memory store operation that triggered the invalidation has completed. Conversely, under the write-update protocol, when one PE writes new data to the coherence granule, all other PEs receive copies of the new data and update their respective local copies with the coherence granule containing the new data. Therefore, the write-update protocol does not require invalidating any local cache copies of the coherence granule, and thus does not require additional memory load operations to regain lost coherence granules.

[0004] The relative efficiency of write invalidation protocols and write update protocols can depend on the environment in which each PE is operating. Generally, write invalidation protocols are more efficient than write update protocols when a PE performs many subsequent memory store operations on the same consistent granule, and the updated consistent granule is unlikely to be read by another PE in the short term. For example, when a software thread migrates from a first PE to a second PE, a memory store operation from the second PE invalidating the local cache copy of the consistent granule in the first PE would be more efficient than updating the value of the local cache copy of the consistent granule in the first PE. However, when a memory store operation on a consistent granule is followed by a memory load operation on the same consistent granule by multiple PEs, write update protocols are more efficient than write invalidation protocols. In this case, write update protocols ensure that all PEs holding local cache copies of the consistent granule receive the updated copy, while in the same situation, write invalidation protocols would require the PE holding the local cache copy of the consistent granule to invalidate its now outdated copy and then perform a memory load operation by sending a separate read bus command to the central sorting point circuit (COP) to read the updated value.

[0005] Therefore, while write-invalidate and write-update protocols each have their advantages in specific situations, neither is equally efficient in all cases. Furthermore, the information used to determine which cache coherence protocol is most efficient in a given scenario may not be accessible to a single entity such as the COP, but rather may be distributed among one or more of the master PE, snooping PE, and COP. Therefore, it is desirable to provide a mechanism that can use the appropriate cache coherence protocol based on the available conditions at the time of performing a memory storage operation. Summary of the Invention

[0006] The exemplary embodiments disclosed herein include tracking repeated reads in a processor-based device to guide the dynamic selection of cache coherence protocols. In this regard, in one exemplary embodiment, the processor-based device includes a central sorting point circuit (COP) and a plurality of processing elements (PEs), wherein each PE provides a plurality of repeated read indicators corresponding to coherent granules read by the PE. The repeated read indicators are used by the PEs to track whether a PE has repeatedly read a coherent granule (e.g., as a result of rereading a coherent granule due to polling, or as a result of rereading after a coherent granule has been evicted from the cache due to an invalid snoop). The plurality of PEs includes a master PE and at least one snooper PE. As used herein, the term "master PE" refers to the PE that performs a memory store operation and sends a cache coherence bus command to the COP. The term "snooper PE" refers to the PE that receives a snoop command associated with a memory store operation from the COP and then acts on the snoop command to maintain cache coherence. Thus, for one memory store operation, a PE can operate as a master PE, and for different memory store operations, it can also operate as a snooper PE.

[0007] One of the most accurate indicators of whether a write-update protocol is more advantageous than a write-invalidate protocol is whether a snooping PE holding a cache copy of a coherent granule written by a cache coherence bus command has performed read operations on that coherent granule in the past. Accordingly, after the primary PE among multiple PEs sends a cache coherence bus command to the COP as part of a memory store operation, the PEs among the multiple PEs (e.g., the primary PE or the snooping PE) use their repeated read indicators to generate a first protocol preference indicator to indicate whether the PE predicts that a write-invalidate protocol or a write-update protocol is preferred (as indicated by the corresponding repeated read indicator, based on the probability of subsequently rereading the coherent granule). The PE then sends the first protocol preference indicator to the COP. Using the protocol preference indicators (including the first protocol preference indicator) provided by the primary PE, the snooping PE, and the COP, the COP dynamically selects either a write-invalidate protocol or a write-update protocol as the cache coherence protocol on a store-by-store basis to maintain cache coherence of the memory store operation by the primary PE. After selecting the cache coherence protocol to use based on the protocol preference indicator, the COP sends a response message to each of the master PE and at least one snooping PE, indicating the selected cache coherence protocol for memory storage operations.

[0008] In another exemplary embodiment, a method is provided in a processor-based device for tracking repeated reads to guide the dynamic selection of a cache coherence protocol. The method includes a primary PE among a plurality of PEs in the processor-based device sending a cache coherence bus command to a COP as part of a memory storage operation. The method also includes a PE among the plurality of PEs generating a first protocol preference indicator based on repeated read indicators among a plurality of repeated read indicators of the PEs, each of the repeated read indicators corresponding to a coherence granule read by the PE and indicating whether the coherence granule has been repeatedly read by the PE. The method further includes, in response to receiving a cache coherence bus command, the COP dynamically selecting, on a per-store basis, one of a write invalidation protocol and a write update protocol as the cache coherence protocol for maintaining cache coherence, based on one or more protocol preference indicators provided by one or more of the primary PEs, at least one snooper PE among the plurality of PEs, and one or more of the COP, the one or more protocol preference indicators including the first protocol preference indicator. The method also includes the COP sending a response message indicating the selected cache coherence protocol to each of the primary PE and at least one snooper PE.

[0009] In another exemplary embodiment, a non-transitory computer-readable medium having computer-executable instructions stored thereon is provided. When executed by a processor-based device, the computer-executable instructions cause the processor-based device to send a cache coherence bus command to the COP as part of a memory storage operation via a primary PE among a plurality of PEs of the processor-based device. The computer-executable instructions also cause the processor-based device to generate a first protocol preference indicator from a plurality of repeat read indicators of the PEs, each of the repeat read indicators corresponding to a coherence granule read by the PE and indicating whether the PE repeats the read of the coherence granule. The computer-executable instructions further cause the processor-based device, in response to receiving a cache coherence bus command, to dynamically select, on a per-store basis, a write invalidation protocol and a write update protocol as the cache coherence protocol for maintaining cache coherence, based on one or more protocol preference indicators provided by the primary PE, at least one snooper PE among the plurality of PEs, and one or more of the COPs, the first protocol preference indicator among the protocol preference indicators. The computer-executable instructions also cause the processor-based device to send a response message from the COP to each of the master PE and at least one snooping PE, indicating the selected cache coherence protocol.

[0010] Those skilled in the art will understand the scope of this disclosure and will implement additional embodiments of this disclosure after reading the following detailed description of preferred embodiments associated with the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are included in and form a part of this specification, illustrate several embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0012] Figure 1 This is a block diagram illustrating an exemplary processor-based device according to some embodiments, the device being configured to track repeated reads using a protocol preference indicator generated based on a repeated read indicator to guide the dynamic selection of a cache coherence protocol in the processor-based device; Figure 2A and 2B This illustrates some embodiments. Figure 1 A block diagram of an embodiment of a processing element (PE) configured to track repeated reads of coherent granules due to polling and to track rereads of cache coherent granules evicted after a snooping failure. Figures 3A-3C This illustrates, according to some embodiments, a method for dynamically selecting a cache coherence protocol. Figure 1 A message flow diagram illustrating the exemplary communication flow between the main PE, the spy PE, and the COP; Figure 4 This is a flowchart illustrating exemplary operations for tracking repeated reads to guide the dynamic selection of a cache coherence protocol, according to some embodiments; Figures 5A-5C This is a flowchart illustrating exemplary operations according to some embodiments, which are used to track repeated reads of consistent granules due to polling and to track rereads of cache consistent granules that have been evicted after a snooping failure. Figure 6 This is a flowchart illustrating an exemplary operation according to a further embodiment, which is used to track rereads of cache coherency granules evicted after a snooping failure; Figure 7 This illustrates an embodiment. Figure 1 A flowchart of a further exemplary operation of the master PE, which is used to predict that writing invalid protocols is preferred and to provide a protocol preference indicator to the COP; Figure 8 This illustrates an embodiment. Figure 1 A flowchart illustrating an exemplary operation of the preferred write-up protocol for predicting COPs; Figure 9A and 9BThis illustrates an embodiment. Figure 1 A flowchart illustrating exemplary operations of the eavesdropping PE, which is used to predict whether a write update protocol is preferred and to provide a protocol preference indicator to the COP; and Figure 10 It is an exemplary processor-based device (e.g.) Figure 1 A block diagram of a processor-based device configured to track repeated reads to guide the dynamic selection of cache coherence protocols in a processor-based device. Detailed Implementation

[0013] The exemplary embodiments disclosed herein include tracking repeated reads to guide the dynamic selection of cache coherence protocols in a processor-based device. In this regard, in one exemplary embodiment, the processor-based device includes a central sorting point circuit (COP) and a plurality of processing elements (PEs), each PE providing a plurality of repeated read indicators corresponding to coherent particles read by the PE. The PEs use the repeated read indicators to track whether coherent particles are repeatedly read by the PEs (e.g., as a result of rereading a coherent particle as a result of polling, or as a result of rereading after a coherent particle has been evicted from the cache due to an invalid snoop). The plurality of PEs includes a master PE and at least one snooper PE. As used herein, the term "master PE" refers to the PE that performs a memory store operation and sends a cache coherence bus command to the COP. The term "snooper PE" refers to the PE that receives a snoop command associated with a memory store operation from the COP and then operates on the snoop command to maintain cache coherence. Thus, for one memory store operation, a PE can operate as a master PE, and for different memory store operations, it can also operate as a snooper PE.

[0014] One of the most accurate indicators of whether a write-update protocol is more advantageous than a write-invalidate protocol is whether a snooping PE holding a cache copy of a coherent granule written by a cache coherence bus command has performed read operations on that coherent granule in the past. Accordingly, after the primary PE among multiple PEs sends a cache coherence bus command to the COP as part of a memory storage operation, the PEs among the multiple PEs (e.g., the primary PE or the snooping PE) use their repeated read indicators to generate a first protocol preference indicator to indicate whether the PE predicts that a write-invalidate protocol or a write-update protocol is preferred (as indicated by the corresponding repeated read indicator, based on the probability of subsequently rereading the coherent granule). The PE then sends the first protocol preference indicator to the COP. Using the protocol preference indicators (including the first protocol preference indicator) provided by the primary PE, the snooping PE, and the COP, the COP dynamically selects either a write-invalidate protocol or a write-update protocol as the cache coherence protocol on a per-store basis to maintain cache coherence for storage operations performed by the primary PE's memory. After selecting the cache coherence protocol to use based on the protocol preference indicator, the COP sends a response message to each of the master PE and at least one snooping PE, indicating the selected cache coherence protocol for memory storage operations.

[0015] in this regard, Figure 1 An exemplary processor-based device 100 is shown, which provides a plurality of processing elements (PEs) 102(0)-102(P) for processing executable instructions. Each of the PEs 102(0)-102(P) may include, for example, a single processor core, which includes a logical execution unit and associated cache and functional units. Figure 1 In the example, each of PEs 102(0)-102(P) includes a corresponding execution pipeline 104(0)-104(P) configured to perform out-of-order execution of an instruction stream comprising computer-executable instructions. As a non-limiting example, each of the execution pipelines 104(0)-104(P) may include a fetch phase for retrieving instructions for execution, a decoding phase for converting the fetched instructions into control signals for instruction execution, a renaming phase for allocating physical register file (PRF) registers, a dispatch phase for issuing instructions for execution, an execution phase for sending instructions and operands to the execution unit, and / or a commit phase for irrevocably updating the architectural state of the corresponding PE 102(0)-102(P) based on the result of instruction execution.

[0016] Figure 1 The processor-based devices 100, PE 102(0)-102(P), are interconnected with each other via interconnect bus 108 and interconnected with system memory 106. For example... Figure 1 As shown, system memory 106 is subdivided into multiple coherence granules 110(0)-110(G), each coherence granule representing the smallest memory unit (e.g., 64 bytes, as a non-limiting example) for cache coherence maintained by processor-based device 100. PEs 102(0)-102(P) also include corresponding caches 112(0)-112(P), which respectively include cache lines 114(0)-114(C), 116(0)-116(C), and 118(0)-118(C). It should be understood that PEs 102(0)-102(P) may include Figure 1 The cache shown is a cache other than caches 112(0)-112(P), and caches 112(0)-112(P) may include Figure 1 Additional components, such as cache controller circuitry, are not shown. Caches 112(0)-112(P) are used by corresponding PEs 102(0)-102(P) to locally store data read from system memory 106 for faster access. For example, as... Figure 1 As shown, cache lines 114(0), 116(0) and 118(0) corresponding to caches 112(0)-112(P) store local copies (“COGRAN COPY”) 120, 122 and 124 of one of the consistency particles 110(0)-110(G) (e.g., consistency particle 110 as a non-limiting example).

[0017] Processor-based device 100 also includes COP 126, which is configured to arbitrate cache coherence bus commands received from the master PEs in PEs 102(0)-102(P) to direct snooping commands to the snooping PEs in PEs 102(0)-102(P) and receive snooping responses from them, and to send response messages to both the master PE and the snooping PEs in PEs 102(0)-102(P). COP 126 may work in conjunction with snooping filter 128, which is configured to monitor traffic on interconnect bus 108 to track the coherence status of cache lines 114(0)-114(C), 116(0)-116(C), and 118(0)-118(C) of PEs 102(0)-102(P).

[0018] Figure 1The processor-based device 100 and its constituent elements may include any one of known digital logic elements, semiconductor circuits, processing cores and / or memory structures, as well as other elements or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor sockets or packages. It should be understood that some embodiments of the processor-based device 100 may include, in addition to… Figure 1 Components other than those shown. For example, each of PE 102(0)-102(P) may further include one or more functional units, instruction caches, unified caches, memory controllers, interconnect buses and / or additional memory devices, cache and / or controller circuitry, for clarity. Figure 1 These have been omitted.

[0019] As mentioned above, conventional processor-based devices provide support for cache coherence protocols, such as write invalidation and write update protocols, to enable local changes to shared data within one PE 102(0)-102(P) to propagate to other PEs 102(0)-102(P), ensuring that all PEs 102(0)-102(P) have a consistent view of the shared data. However, while write invalidation and write update protocols each have their advantages in specific situations, neither is equally efficient in all situations. Furthermore, the information available to determine which cache coherence protocol is most efficient in a given scenario may not be available from a single entity (e.g., Figure 1 Instead of accessing COP 126, it can be distributed among the main PE in PE 102(0)-102(P), the spy PE in PE 102(0)-102(P), and one or more of COP 126.

[0020] in this regard, Figure 1 The processor-based device 100 is configured to provide dynamic selection of cache coherency protocols. See below for details. Figures 3A-3CIn more detail, COP 126 is configured to dynamically select a cache coherence protocol (i.e., either a write invalidation protocol or a write update protocol) for a given memory storage operation based on one or more protocol preference indicators provided by one or more master PEs among PEs 102(0)-102(P), at least one snooping PE among PEs 102(0)-102(P), and COP 126 itself. The selection of the cache coherence protocol is performed by COP 126 on a per-store basis, allowing different cache coherence protocols to be selected for consecutive memory storage operations. Accordingly, processor-based device 100 is configured to support both the write invalidation protocol and the write update protocol simultaneously, rather than supporting only one cache coherence protocol (as is the case with many traditional processor-based devices).

[0021] In some embodiments, PEs 102(0)-102(P) and COP 126 can be configured to provide one or more protocol preference indicators based on knowledge of each available environment. For example, when executing a memory store instruction (“MEM STOREINSTR”) 130, PE 102(0), acting as the master PE, can predict that a write invalidation protocol is preferred because PE 102(0) knows it will perform multiple subsequent memory store operations on a coherent particle such as coherent particle 110(0). Similarly, COP 126 can predict that a write update protocol is preferred based on the number of local cache copies 120, 122, and 124 of highly shared and disputed coherent particles held by PEs 102(0)-102(P). Based on one or more protocol preference indicators received by COP 126, COP 126 dynamically selects a cache coherence protocol and then transmits the selected cache coherence protocol to PEs 102(0)-102(P). As a non-limiting example, the logic for generating, providing and evaluating such protocol preference indicators can be embodied in the prediction logic circuits 132(0)-132(P) of PE 102(0)-102(P) and / or in the prediction logic circuit 134 of COP 126.

[0022] exist Figure 1In the example, PEs 102(0)-102(P) each provide multiple repeat read indicators (“RR”) 136(0)-136(R), 138(0)-118(R) and 140(0)-140(R), which correspond to the consistency particles read by PEs 102(0)-102(P) and cached in caches 112(0)-112(P). PEs 102(0)-102(P) use repeat read indicators 136(0)-136(R), 138(0)-138(R) and 140(0)-140(R) to track whether (and in some embodiments, how many times) a given consistency particle is repeatedly read by the corresponding PE 102(0)-102(P). PE 102(0)-102(P) then uses repeat read indicators 136(0)-136(R), 138(0)-138(R), and 140(0)-140(R) when generating the protocol preference indicator to be sent to COP 126. See below for details. Figure 2A and 2B In more detail, in some embodiments, the repeat read indicators 136(0)-136(R), 138(0)-138(R) and 140(0)-140(R) may each be merged into cache lines 114(0)-114(C), 116(0)-116(C) and 118(0)-118(C), and 140(0)-140(R) is merged into a separate data structure such as a snooping eviction table (not shown).

[0023] To explain Figure 1 Examples of PE 102(0)-102(P) for tracking repeated reads of consistency granules are provided. Figure 2A and 2B .according to Figure 2A Implementations may use a repeat read indicator, for example Figure 1 Repeated read indicators 136(0)-136(R), 138(0)-138(R), and 140(0)-140(R) are used to track repeated reads of consistent granules due to polling reads, and optionally can also be used to track rereads of cache consistent granules evicted after a snooping invalidation. Figure 2B The implementation can use a repeat read indicator to track repeat reads of consistent granularities due to invalid snooping. The operation of initializing and incrementing the repeat read indicator is also discussed below.

[0024] exist Figure 2A In terms of function, it corresponds to Figure 1PE 200 of any of PE 102(0)-102(P) includes cache 202, which includes multiple cache lines 204(0)-204(C). Cache 202 functionally corresponds to Figure 1 The cache lines 112(0)-112(P) and 204(0)-204(C) functionally correspond to Figure 1 The cache lines are 114(0)-114(C), 116(0)-116(C), and 118(0)-118(C). Accordingly, as Figure 2A As shown, each cache line 204(0)-204(C) corresponds to a coherent granular copy (“COGRAN COPY”) 206(0)-206(C).

[0025] like Figure 2A As shown, cache lines 204(0)-204(C) also include corresponding repeat read indicators 208(0)-208(C), which correspond to Figure 1 The repeat read indicators 136(0)-136(R), 138(0)-138(R) and 140(0)-140(R). Figure 2A Repeat read indicators 208(0)-208(C) may be used by PE 200 to track repeat reads of corresponding consistency granularities caused by polling reads, reads performed in the loop when entering and exiting power-saving states on each loop iteration, etc., which all hit cache 202. In some embodiments, each of repeat read indicators 208(0)-208(C) may include one (1) or more bits.

[0026] In normal operation, PE 200 is consistent with granularity (e.g., as a non-limiting example, Figure 1 During the first read of the coherent granule 110(0), a cache line, such as cache line 204(0), is allocated. The repeat read indicator 208(0) of cache line 204(0) is initialized to a zero (0) value. Subsequently, when it is determined that a read operation performed locally by PE 200 (i.e., not a read operation generated by external snooping) results in a hit on cache line 204(0), PE 200 increments the repeat read indicator 208(0) of cache line 204. In some embodiments, the repeat read indicator 208(0) may saturate at its maximum value. Thus, for example, if the repeat read indicator 208(0) comprises two (2) bits, the value of the repeat read indicator 206(0) may saturate at a value of three (3), which would indicate that three or more cache hits have occurred on cache line 204 since cache line 204(0) was allocated.

[0027] If PE 200 is subsequently spied on by a cache coherence bus command (e.g., a non-allocation write bus command, a read-with-intent-to-write bus command, or a promote-to-writable bus command) that results in a cache hit on cache line 204(0) in cache 202, PE 200 uses a repeat read indicator 208(0) to determine whether to accept or request a write update rather than perform a write invalidation operation. For example, if the repeat read indicator 208(0) comprises two (2) bits as described above, PE 200 will generate a protocol preference indicator to indicate a preference for a write update protocol if the repeat read indicator 208(0) is equal to a threshold (e.g., a value of three (3) as a non-limiting example), and will generate a protocol preference indicator to indicate a preference for a write invalidation protocol if the repeat read indicator 208(0) has a value less than the threshold. In some embodiments, the threshold may be provided by a programmable threshold that can be set in the firmware of the processor-based device 100.

[0028] When generating protocol preference indicators, information regarding the rereading of a consistent particle after it has been invalidated by an external snoop (e.g., due to a write operation from another PE using a write invalidation snooping protocol) may also be useful to PE 200. However, repeat read indicators 208(0)-208(C) cannot be used for this purpose because the corresponding invalid cache lines 204(0)-204(C) can be reassigned to another consistent particle before being reread. Accordingly, in some embodiments, PE 200 also provides a snoop eviction table 210 comprising multiple snoop eviction table entries 212(0)-212(S) for tracking consistent particles evicted from cache 202. Snoop eviction table entries 212(0)-212(S) include the corresponding consistent particle address (“COGRAN ADDRESS”) 214(0)-214(S), previous repeat read indicators 216(0)-216(S), and valid indicators 218(0)-218(S).

[0029] When a PE evicts a cache line (e.g., cache line 204(0)) from cache 202 due to a snooping invalidity, PE 200 allocates a snooping eviction table entry (e.g., snooping eviction table entry 212(0) as a non-limiting example). PE 200 fills the coherence granular address 214(0) of snooping eviction table entry 212(0) with the corresponding coherence granular address and initializes the previous repeat read indicator 216(0) to the value of the repeat read indicator 208(0) in the evicted cache line 204(0). PE 200 also initializes the validity indicator 218(0) of snooping eviction table entry 212(0) to indicate that 212(0) of snooping eviction table entry is valid. If PE 200 subsequently determines that a locally executed read operation resulted in a cache miss at cache 202, but matched a valid peek-out eviction table entry (e.g., peek-out eviction table entry 212(0)), then PE 200 increments the previous repeated read indicator 216(0) (unless the previous repeated read indicator 216(1) was implemented as a saturation counter and has reached its saturation value). PE 200 then allocates a new cache line (e.g., cache line 204(C) as a non-limiting example) and initializes the repeated read indicator 208(C) of the newly allocated cache line 204(C) to the value of the previous repeated read indicator 216(0) for peek-out eviction table entry 212(0). PE 200 also updates the validity indicator 218(0) to indicate that peek-out eviction table entry 212(0) is no longer valid.

[0030] In some embodiments, a Least Recently Used (LRU) mechanism is used to manage snooping eviction table entries 212(0)-212(S). Accordingly, when PE 200 needs to allocate one of snooping eviction table entries 212(0)-212(S), PE 200 will select the oldest snooping eviction table entry from among those snooping eviction table entries 212(0)-212(S) that have a valid indicator 218(0)-218(S) indicating that the snooping eviction table entry is not valid. If all snooping eviction table entries 212(0)-212(S) are valid, PE 200 will select the least recently used entry and overwrite its contents.

[0031] Figure 2B The PE 220 is shown, and its functions are similar to... Figure 1Corresponding to any of PEs 102(0)-102(P), PE 220 is configured to track only repeated reads of consistent granules due to snooping invalidities (e.g., for workloads that might not repeatedly poll consistent granules when repeatedly hitting the local cache). Therefore, PE 220 includes a cache 222 comprising a plurality of cache lines 224(0)-224(C), wherein cache 222 functionally corresponds to Figure 1 The cache lines 112(0)-112(P) and cache lines 224(0)-224(C) functionally correspond to Figure 1 The cache lines in the cache are 114(0)-114(C), 116(0)-116(C), and 118(0)-118(C). For example... Figure 2A As shown, each cache line 224(0)-224(C) corresponds to a coherent granular copy (“COGRAN COPY”) 226(0)-266(C).

[0032] PE 220 also provides a snoop eviction table 228, which includes multiple snoop eviction table entries 230(0)-230(S) for tracking coherent granules evicted from cache 222. Snoop eviction table entries 230(0)-230(S) include the corresponding coherent granule address (“COGRAN ADDRESS”) 232(0)-232(S), a repeat read indicator 234(0)-234(S), and a validity indicator 236(0)-236(S). The repeat read indicator 234(0)-234(S) corresponds to... Figure 1 The repeat read indicators 136(0)-136(R), 138(0)-138(R) and 140(0)-140(R) are included. According to some embodiments, each of the repeat read indicators 208(0)-208(C) may include one (1) bit.

[0033] When a cache line (e.g., cache line 224(0)) is evicted from cache 222 by PE 220 due to a snoop invalidation, PE 220 allocates a snoop eviction table entry (e.g., snoop eviction table entry 230(0) as a non-limiting example) and fills the coherence granular address 232(0) of snoop eviction table entry 230(0) with the corresponding coherence granular address. PE 220 also initializes the repeat read indicator 234(0) of snoop eviction table entry 230(0) to zero (0) and initializes the validity indicator 236(0) of snoop eviction table entry 230(0) to indicate that snoop eviction table entry 230(0) is valid. If PE 220 subsequently determines that a locally executed read operation results in a miss on cache 222, but matches a valid snoop eviction table entry (e.g., snoop eviction table entry 230(0)), then PE 220 increments the repeat read indicator 234(0) of snoop eviction table entry 230(0). If PE 220 is subsequently snooped by a cache coherence bus command that results in a cache hit on cache 202 (e.g., a non-allocation write bus command, a read bus command with write intent, or a promotion to a writable bus command), then PE 220 also searches snoop eviction table 228 and will use the repeat read indicator 234(0) (i.e., as stated above regarding...). Figure 2A The repeated read indicator 208(0) discussed here determines whether to accept or request to write updated data, rather than performing an invalid write operation.

[0034] Provided Figures 3A-3C In order to explain Figure 1 The communication flow between components of the processor-based device 100 is used to generate and provide protocol preference indicators and dynamically select cache coherence protocols. For clarity, in the description Figures 3A-3C Referenced at the time Figure 1 Components. For example... Figures 3A-3C As shown, message flow diagram 300 illustrates PE 102(0) (i.e., "master PE 102(0)" in this example), PE 102(1) and 102(P) (i.e., "spy PE 102(1) and (102)" in this example), and COP 126, represented by vertical lines, and the communication between these elements indicated by the header arrows. It should be understood that PE 102(0) is referred to as "master PE" for illustrative purposes only, and PE 102(1) and 102(P) are referred to as "spy PEs", and each of PE(0)-102(P) can operate as either a master PE or a spy PE, depending on the role of that PE in a particular memory storage operation. It should be further understood that not all embodiments are feasible. Figures 3A-3C All operations shown.

[0035] exist Figure 3A In this process, the operation begins with the master PE 102(0), which, in response to a memory storage operation performed by the master PE 102(0), predicts whether a write invalidation protocol is preferred, as shown in box 302. Generally, the master PE 102(0) may be subject to other agents (e.g., snooping PEs 102(1) and 102(P) as non-limiting examples, COP 126, software-provided hints, etc.) to determine whether a write update protocol is preferred. However, in some cases, the master PE 102(0) may predict that a write update protocol will be unfavorable and a write invalidation protocol is preferred. For example, if a repeated read indicator (e.g.) is used... Figure 1 If one of the repeat read indicators 136(0)-136(R) indicates that the primary PE 102(0) has repeatedly read the consistency particle, then the primary PE 102 can assume that the snooping PEs 102(1) and 102(P), if they also hold a cached copy of the consistency particle, will also likely reread the consistency particle after writing to it. Therefore, the primary PE 102(0) will predict that the write update protocol is preferred.

[0036] Similarly, if the primary PE 102(0) sends a promotion to writable bus command due to a write operation that results in a hit on cache 112(0) in a shared (S) cache coherent state, the primary PE 102(0) will predict that a write update is preferred if the corresponding repeat read indicator 136(0)-136(R) is at its saturation value, regardless of whether the primary PE 102(0) detects multiple writes to the corresponding coherent granularity. In an embodiment that also implements a primary PE 102(0) that snoops on the eviction table, when a non-allocated write bus command or a read bus command with write intent is sent, the primary PE 102(0) can use the previous repeat read indicator (e.g., Figure 2A Similar logic is applied to the previous repeated read indicators 216(0)-216(S)).

[0037] Based on its prediction, the master PE 102(0) sends a cache coherence bus command 304 to the COP 126, indicating its preferred cache coherence protocol, as shown by arrow 306. The cache coherence bus command 304 includes a write-preservation prevention attribute 308 asserted or deasserted by the master PE 102(0) to indicate its preference for the COP 126. Figure 3AAs shown, the prevent write update attribute 308 represents one possible embodiment of the protocol preference indicator 310, and may generally be referred to as such herein. In some embodiments, the prediction that the master PE 102(0) is a preferred write invalidation protocol will be considered certain by COP 126, thereby allowing the master PE 102(0) to disallow the use of the write update protocol for a given memory storage operation. Therefore, as per [the relevant context]... Figure 3B In a more detailed discussion, in such an embodiment, if the master PE 102(0) sends a cache coherence bus command 304 to the COP 126 and asserts the write-invalidation attribute 308, the COP 126 sends a response message to the master PE 102(0), the snoop PE 102(1), and 102(P), indicating that a write invalidation protocol has been selected.

[0038] In some embodiments, cache coherence bus command 304 may include a non-allocation write bus command sent by master PE 102 (0) in response to a cache miss on cache 112 (0), wherein the memory store operation is not a write allocation in cache 112 (0) of master PE 102 (0). Some embodiments may provide cache coherence bus command 304 including a read bus command with write intent sent by master PE 102 (0) in response to a cache miss on cache 112 (0), wherein the memory store operation is a write allocation in cache 112 (0) of master PE 102 (0). According to some embodiments, cache coherence bus command 304 may include an elevation to writable bus command sent by master PE 102 (0) in response to a cache hit on cache 112 (0), wherein cache lines (e.g., cache line 114 (0) as a non-limiting example) are maintained in a shared coherent state.

[0039] Upon receiving Cache Coherence Bus Command 304 from Master PE 102(0), COP 126 then makes its own prediction regarding whether a write update protocol is preferred, as shown in box 312. COP 126 then sends a snoop command 314 to Snoop PEs 102(1) and 102(P), as indicated by arrows 316 and 318, respectively. Snoop command 314 includes a write update request attribute 320, which COP 126 asserts or deasserts to indicate its cache coherence protocol preference to Snoop PEs 102(1) and 102(P). As described above, in some embodiments, COP 126 may deassert the write update request attribute 320 if Master PE 102(0) sends Cache Coherence Bus Command 304 and asserts the prevent write update attribute 308. It should be understood that, as Figure 3AAs shown, the write update request attribute 320 represents another possible embodiment of the protocol preference indicator 310, and therefore may be referred to as such herein. Then... Figure 3B Recovery operation.

[0040] Now for reference Figure 3B Each of the snoopers PE 102(1) and 102(P) can also independently predict whether a write update protocol is preferred, as indicated by boxes 322 and 324, respectively. In this way, snoopers PE 102(1) and 102(P) can confirm participation in or opt-out of a write update request (as indicated by the write update request attribute 320 of the asserted snooping command 314), or request a write update protocol if the write update request attribute 320 in the snooping command 314 is deasserted. In the former case, if the write update request attribute 320 of the snooping command 314 is asserted by COP 126, each of the snoopers PE 102(1) and 102(P) can default to using the write update protocol unless it determines that there is a reason for opting out. As a non-limiting example, a spy PE such as spy PE 102(1) and 102(P) may decide to opt out of using the write update protocol because the spy PE is unwilling to receive write update data due to lack of resources or because it is operating in a configuration that prohibits receiving write update data. Conversely, each of the spy PEs 102(1) and 102(P) may still request the write update protocol based on its own prediction of benefiting from using the write update protocol if the write update request attribute 320 of the spy command 314 is deasserted by COP 126.

[0041] According to some embodiments, based on the corresponding repeated read indicator (e.g. Figure 2A Repeat read indicator 208(0)-208(C) or Figure 2B The repeat read indicators 234(0)-234(S)) allow the snooping PEs 102(1) and 102(P) to use the probability of writing to the consistency granule 110(0) by the memory storage operation as the basis for their respective predictions regarding whether a write update protocol is preferred. If so, the snooping PEs 102(1) and 102(P) will indicate a preference for the write update protocol. Thus, for example, if the relevant repeat read indicator is at its saturation value, the snooping PEs 102(1) and 102(P) will predict that the write update protocol is preferred, and if the repeat read indicator is less than its saturation value, they will predict that the write invalidation protocol is preferred.

[0042] After predicting whether the write update protocol is preferred, the snoopers PE 102(1) and 102(P) send snoop responses 326 and 328 to COP 126, as shown by arrows 330 and 332, respectively. Snoop responses 326 and 328 include write update request attributes 334 and 336, respectively, which are asserted or deasserted based on whether the corresponding snoopers PE 102(1) and 102(P) predict that the write update protocol is preferred. It should be understood that, as Figure 3B As shown, writing update request attributes 334 and 336 represents other possible embodiments of the protocol preference indicator 310, and therefore may generally be referred to as such herein. Then... Figure 3C Recovery operation.

[0043] Now go to Figure 3C Upon receiving snoop responses 326 and 328, in some embodiments, COP 126 may determine whether either snoop response 326 or 328 includes asserted write update request attributes 334 or 336, as shown in box 338. Assuming that the master PE 102 (0) does not block the use of the write update protocol (i.e., by asserting write update block attribute 308 to indicate that the write invalid protocol will be selected), COP 126 will generate a response message 340 with a write update valid attribute 342, which is asserted or deasserted based on write update request attributes 334 and 336, and will send response messages 340 to the master PE 102 (0) and snoop PEs 102 (1) and 102 (P), as shown by arrows 344, 346 and 348, respectively. Because the snooping PEs 102(1) and 102(P) independently determine whether the write update protocol is preferred, they may assert both attributes 334 and 336 of the write update request, assert only one of these attributes, or assert neither. If either of the write update request attributes 334 and 336 is asserted (and the write update prevention attribute 308 of the cache coherence bus command 304 sent by the master PE 102(0) is not asserted), then COP 126 will assert the write update valid attribute 342 of the response message 340. However, if both the write update request attributes 334 and 336 are deasserted (or if the write update prevention attribute 308 of the cache coherence bus command 304 sent by the master PE 102(0) is asserted), then COP 126 will deasserte the write update valid attribute 342 of the response message 340.

[0044] The write update valid attribute 342 of response message 340 indicates to the primary PE 102(0) and the snooping PEs 102(1) and 102(P) that a cache coherence protocol will be selected by COP 126 for the memory storage operation. Upon receiving response message 340 with the asserted write update valid attribute 342, the primary PE 102(0) will perform a write update by sending data to the snooping PEs 102(1) and 102(P) to update their local cache copies 122 and 124, respectively. Similarly, upon receiving response message 340 with the asserted write update valid attribute 342, any snooping PE 102(1) or 102(P) whose snooping responses 326 and 328 include the asserted write update request attributes 334 and 336 will be ready to receive write update data from the primary PE 102(0). Any snooper PE 102(1), 102(P) whose snoop responses 326, 328 include the write update request attributes 334, 336 which have been deasserted will ignore the write update valid attribute 342 in the response message 340 and will perform write invalidation.

[0045] The mechanism described herein for dynamically selecting a cache coherence protocol allows COP 126 to storewise select a write invalidation protocol or a write update protocol based on inputs from one or more of the master PE 102 (0), the snooping PEs 102 (1) and 102 (P), and COP 126 itself. In this way, a cache coherence protocol that provides optimal performance and / or lowest power consumption can be used for each memory storage operation that finds a cache copy of the coherent granules in another PE 102 (0)-102 (P).

[0046] To illustrate exemplary operations for tracking repeated reads to guide the dynamic selection of cache coherence protocols according to some embodiments, Figure 4 A flowchart (400) is provided. For clarity, in the description... Figure 4 Referenced at the time Figure 1 and 3A -3C components. Figure 4 The operation begins in the main PE (e.g., PE 102(0)-102(P)) among multiple PEs. Figure 1 PE 102(0) in the processor-based device 100 sends cache coherence bus command 304 (box 402) to COP 126 as part of a memory storage operation. PEs (e.g., PEs 102(0)-102(P) in the processor-based device 100 are used to send cache coherence bus command 304 (box 402). Figure 1 The PE 102(1) in the multiple repeat read indicators 138(0)-138(R) based on PE102(1) (e.g.) Figure 1The repeated read indicator 138(0) generates a first protocol preference indicator 310, and each of the multiple repeated read indicators 138(0)-138(R) corresponds to a consistency particle read by PE 102(1) (e.g., Figure 1 The consistency particle 110(0) is indicated, and it indicates whether the consistency particle 110(1) is repeatedly read by PE 102(1) (box 404). Then, PE 102(1) sends a first protocol preference indicator 310 to COP 126 (box 406).

[0047] Upon receiving the cache coherence bus command 304, COP 126 dynamically selects one of the write invalidation protocol and write update protocol as the cache coherence protocol for maintaining cache coherence on a per-store basis, based on one or more protocol preference indicators 310 provided by the master PE 102(0), at least one of the snooping PEs (e.g., PE 102(1) and 102(P)) among the plurality of PEs 102(0)-102(P) and COP 126. The one or more protocol preference indicators include a first protocol preference indicator 310 (box 408). COP 126 then sends a response message 340 (box 410) indicating the cache coherence protocol to each of the master PE 102(0) and at least one of the snooping PEs 102(1) and 102(P).

[0048] Figures 5A-5C A flowchart 500 is provided according to some embodiments to illustrate exemplary operations for tracking repeated reads of consistent granularities due to polling and tracking rereads of cache consistent granularities evicted after a snooping failure. For clarity, in the description Figures 5A-5C Referenced at the time Figure 1 and 2A Components. In Figure 5A In this process, the operation begins with a PE, such as PE 200, after the first reading of the consistency granules by PE 200 (e.g., Figure 1When the consistency granule 110(0) is reached, a series of operations are performed (box 502). PE 200 allocates a corresponding cache line (e.g., cache line 204(0)) among a plurality of cache lines 204(0)-204(C) of PE 200's cache 202, wherein each cache line 204(0)-204(C) includes a corresponding repeat read indicator for a plurality of repeat read indicators 208(0)-208(C) (box 504). PE 200 then initializes the repeat read indicator 208(0) of cache line 204(0) to a value of zero (0) (box 506). When it is determined that a locally performed read operation results in a hit on cache line 204(0), PE 200 increments the repeat read indicator 208(0) of cache line 204(0) (box 508). Then, in some embodiments, the operation is performed in... Figure 5B Continue at box 510.

[0049] Now go to Figure 5B In embodiments where PE 200 also includes a snoop eviction table 210, PE 200 also performs a series of operations when a snoop eviction occurs due to invalid snooping, resulting in the eviction of cache line 204(0)-204(C) of cache 202 (box 510). PE 200 allocates snoop eviction entries (e.g., snoop eviction entry 212(0)) from a plurality of snoop eviction entries 212(0)-212(S) of PE 200's snoop eviction table 210, wherein each snoop eviction entry 212(0)-212(S) includes a consistency granular address 214(0)-214(S), a previously repeated read indicator 216(0)-216(S), and a valid indicator 218(0)-218(S) (box 512). PE 200 initializes the coherence granule address 214(0) of the snooping eviction table entry 212(0) to the address of the coherence granule 110(0) (box 514). Then, PE 200 initializes the previous repeat read indicator 216(0) of the snooping eviction table entry 212(0) to the value of the repeat read indicator 208(0) in cache line 204(0) (box 516). PE 200 also initializes the validity indicator 218(0) of the snooping eviction table entry 212(0) to indicate that 212(0) of the snooping eviction table entry is valid (box 518). Then... Figure 5C Continue operating on box 520.

[0050] Now for reference Figure 5CWhen it is determined that a locally executed read operation results in a cache miss but matches a valid snoop eviction table entry (e.g., snoop eviction table entry 212(0)), PE 200 performs a series of operations (box 520). PE 200 increments the previous repeated read indicator 216(0) of snoop eviction table entry 212(0) (box 522). PE 200 then allocates a new cache line (e.g., cache line 204(C)) corresponding to the locally executed read operation in the plurality of cache lines 204(0)-204(C) (box 524). PE 200 then initializes the repeated read indicator 208(C) of the new cache line 204(C) to the value of the previous repeated read indicator 216(0) of the valid snoop eviction table entry 212(0) (box 526). PE 200 also updates the validity indicator 218(0) of valid snooping eviction table entry 212(0) to indicate that valid snooping eviction table entry 212(0) is not valid (box 528).

[0051] Figure 6 A flowchart 600 is provided according to a further embodiment to illustrate exemplary operation for tracking rereads of cache coherency granules evicted after a snooping failure. For clarity, in the description... Figure 6 Referenced at the time Figure 1 and 2B Components. Figure 6 The operation in the process begins with the PE (e.g., Figure 2BPE 220 performs a series of operations in the following situation: cache lines (e.g., cache line 224(0)-224(C)) of cache 222 are evicted by PE 220 due to invalid snooping (box 602). PE 220 allocates snooping eviction table entries (e.g., snooping eviction table entry 230(0)-230(S)) of PE 220's snooping eviction table 228, wherein each snooping eviction table entry 230(0)-230(S) includes a consistency granular address 232(0)-232(S), a corresponding repeat read indicator among multiple repeat read indicators 234(0)-234(S), and a validity indicator 236(0)-236(S) (box 604). PE 220 initializes the coherence granule address 232(0) of the snoop eviction table entry 230(0) to the address of the coherence granule (e.g., coherence granule 110(0)) corresponding to cache line 224(0) (box 606). PE 220 also initializes the repeat read indicator 234(0) of the snoop eviction table entry 230(0) to a value of zero (0) (box 608). Additionally, PE 220 initializes the validity indicator 236(0) of the snoop eviction table entry 230(0) to indicate that 230(0) of the snoop eviction table entry is valid (box 610). When PE 220 determines that a read operation results in a miss on cache 222 but a matching valid snoop eviction table entry (e.g., snoop eviction table entry 230(0)), PE 220 increments the repeat read indicator 234(0) of the valid snoop eviction table entry 230(0) (box 612).

[0052] Figure 7 A description based on one embodiment is provided. Figure 1 and 3A A flowchart 700 of a further exemplary operation of the main PE 102(0) of -3C, which is used to predict that writing an invalid protocol is preferred and to provide a protocol preference indicator 310 to COP 126. For clarity, in the description Figure 7 Referenced at the time Figure 1 and 3A -3C components. In Figure 7 In the middle, the operation begins on the main PE 102 (0) based on multiple repeat read indicators (e.g. Figure 1The repeated read indicator in the repeated read indicator 136(0)-136(R)) predicts that the write invalidation protocol is preferred (box 702). In response to the prediction that the write invalidation protocol is preferred, the master PE 102(0) asserts the write-update prevention attribute 308 of the cache coherence bus command 304 (box 704). In response to receiving the cache coherence bus command 304 with the asserted write-update prevention attribute 308, COP 126 sends a response message 340 to each of the master PE 102(0) and at least one snoop PE 102(1), 102(P), which includes the deasserted write-update validity attribute 342 to indicate that the write invalidation protocol will be selected for memory storage operations (box 706).

[0053] To illustrate according to one embodiment Figure 1 COP 126 for predicting write update protocols is a preferred exemplary practice. Figure 8 A flowchart (800) is provided. For clarity, in the description... Figure 8 Referenced at the time Figure 1 and 3A -3C components. Figure 8 The operation begins with COP 126 predicting that the write update protocol is preferred (box 802). In response to the prediction that the write update protocol is preferred, COP 126 asserts the write update request attribute 320 of the snooping command 314 (box 806).

[0054] Figure 9A and 9B A description based on one embodiment is provided. Figure 1 and 3A Flowchart 900 of exemplary operation of the -3C snooper PE 102(1) and 102(P), which is used to predict that a write update protocol is preferred and to provide a protocol preference indicator 310 to COP 126. Figure 9A and 9B In this regard, it is assumed that cache coherence bus command 304 is sent by master PE 102 (0) to COP 126, which will prevent write update attribute 308 from re-asserting, thus allowing COP 126 and snoop PEs 102 (1) and 102 (P) to make their own predictions about the preferred cache coherence protocol. For clarity, in the description Figure 9A and 9B Referenced at the time Figure 1 and 3A -3C components. In Figure 9A In this process, the operation begins with the spy PE (e.g., spy PE 102 (1)) and is based on multiple repeated read indicators (e.g., Figure 1The repeat read indicator in repeat read indicator 138(0)-138(R)) to predict the write update protocol is preferred (box 902).

[0055] In response to the preferred write-update protocol, the snooper PE 102(1) asserts the write-update request attribute 334 of the snoop response 326 (box 904). COP 126 then receives at least one snoop response 326, 328 corresponding to at least one snooper PE 102(1), 102(P) (box 906). COP 126 then determines whether any of the at least one snoop response 326, 328 includes asserted write-update request attributes 334, 336 (box 908). If not, COP 126 sends a response message 340 to each of the master PE 102(0) and at least one snooper PE 102(1), 102(P), including the deasserted write-update valid attribute 342, indicating that the write invalidation protocol will be selected for the memory storage operation (box 910). If COP 126 determines at determination box 910 that any one of the attenuation responses 326, 328 includes assertion-based write update request attributes 334, 336, then processing continues. Figure 9B The box at position 912 in the middle has been restored.

[0056] Now for reference Figure 9B COP 126 sends a response message 340 to each of the primary PE 102(0) and at least one snooper PE 102(1), 102(P), the response message 340 including an asserted write update valid attribute 342 indicating that a write update protocol will be selected for the memory storage operation (block 912). In some embodiments, upon receiving a response message 340 including the asserted write update valid attribute 342, each of the at least one snooper PE 102(1), 102(P) corresponding to a snoop response 326, 328 including asserted write update request attributes 334, 336 may perform a write update operation (block 914). Similarly, in response to a response message 340 that includes an asserted write update valid attribute 342, each of at least one snoop PE 102(1), 102(P) corresponding to a snoop response 326, 328 that includes an asserted write update request attribute 334, 336 can perform a write invalidation operation (box 916).

[0057] Figure 10 It is an example of a processor-based device 1000 (e.g. Figure 1A block diagram of a processor-based device 1000 that provides dynamic selection of a cache coherence protocol. The processor-based device 1000 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based device 1000 includes a processor 1002. The processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc., and can correspond to... Figure 1 PE 102(0)-102(P). Processor 1002 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 1002 includes an instruction cache 1004 and instruction processing circuitry 1010 stored in temporary fast access memory for instructions. Instructions fetched or prefetched from memory (e.g., from system memory 1008 via system bus 1006) are stored in instruction cache 1004. Instruction processing circuitry 1010 is configured to process instructions fetched from instruction cache 1004 and process the instructions for execution.

[0058] Processor 1002 and system memory 1008 are coupled to system bus 1006 and can interconnect peripheral devices included in processor-based device 1000. Processor 1002 is known to communicate with these other devices by exchanging address, control, and data information on system bus 1006. For example, as an example of a peripheral device, processor 1002 can transmit bus transaction requests to memory controller 1012 in system memory 1008. Although... Figure 10 Not shown, but multiple system buses 1006 may be provided, each forming a different architecture. In this example, memory controller 1012 is configured to provide memory access requests to memory array 1014 in system memory 1008. Memory array 1014 includes an array of storage bit cells for storing data. As a non-limiting example, system memory 1008 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0059] Other devices can be connected to system bus 1006. For example... Figure 10As shown as an example, these devices may include system memory 1008, one or more input devices 1016, one or more output devices 1018, modem 1024, and one or more display controllers 1020. Input devices 1016 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Network 1026 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. Modem 1024 may be configured to support any type of communication protocol required. Processor 1002 may also be configured to access display controllers 1020 via system bus 1006 to control information sent to one or more displays 1022. Displays 1022 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal displays (LCDs), plasma displays, etc.

[0060] Figure 10 The processor-based device 1000 may include a set of instructions 1028, executed by the processor 1002 for any application desired according to the instructions. As an example of a non-transitory computer-readable medium 1030, the instructions 1028 may be stored in system memory 1008, the processor 1002, and / or the instruction cache 1004. The instructions 1028 may also reside wholly or at least partially in system memory 1008 and / or the processor 1002 during their execution. The instructions 1028 may also be transmitted or received on a network 1026 via a modem 1024, such that the network 1026 includes the computer-readable medium 1030.

[0061] Although computer-readable medium 1030 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more instruction sets 1028. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device, and causing the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0062] The embodiments disclosed herein include various steps. These steps may be formed by hardware components or embodied in machine-executable instructions that can be used by a general-purpose or special-purpose processor programmed with those instructions to perform the steps. Alternatively, these steps may be performed by a combination of hardware and software processes.

[0063] The embodiments disclosed herein may be provided as a computer program product or software process, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to the various embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0064] Unless otherwise specified and as is apparent from the foregoing discussion, it should be understood that throughout the description, the use of terms such as “processing,” “computing,” “determining,” “displaying,” etc., refers to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data and memory in computer system registers, represented as physical (electronic) quantities, into other data in computer system memory or registers or other such information storage, transmission, or display devices, similarly represented as physical quantities.

[0065] The algorithms and displays presented herein are not inherently associated with any particular computer or other device. Various systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The required structures for various such systems can be seen from the description above. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that the teachings of the embodiments described herein can be implemented using various programming languages.

[0066] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0067] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, which may include hardware components, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0068] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, with an exemplary storage medium coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0069] It should also be noted that the operational steps described in any exemplary embodiment herein are described as being for the purpose of example and discussion. The described operations can be performed in many different sequences than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0070] Unless otherwise expressly stated, no method described in this Agreement shall be construed as requiring the steps to be performed in a particular order. Therefore, no particular order is to be inferred unless a method claim actually enumerates the order in which its steps are performed, or unless otherwise specified in the claim or description, that the steps will be restricted to a particular order.

[0071] Various modifications and variations can be made by those skilled in the art without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments in conjunction with the spirit and essence of the invention may occur to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A processor-based device, comprising: Multiple processing elements (PEs) are included, each PE including multiple repeat read indicators, each repeat read indicator corresponding to a consistency particle read by the PE and indicating whether the consistency particle is read repeatedly by the PE; Central sorting point circuit (COP); The primary PE among the plurality of PEs is configured to send cache coherence bus commands to the COP as part of a memory storage operation; as well as The PE among the plurality of PEs is configured as follows: A first protocol preference indicator is generated based on the repeat read indicator among the plurality of repeat read indicators; as well as Send the first protocol preference indicator to the COP; The COP is configured as follows: In response to receiving the cache coherence bus command, based on one or more protocol preference indicators provided by the master PE, at least one snooper PE among the plurality of PEs and one or more of the COPs, a protocol is dynamically selected on a per-store basis, either the write invalidation protocol or the write update protocol, as the cache coherence protocol for maintaining cache coherence, wherein the one or more protocol preference indicators include the first protocol preference indicator; as well as Send a response message indicating the selected cache coherence protocol to each of the master PE and the at least one spy PE.

2. The processor-based device according to claim 1, wherein: Each of the plurality of PEs further includes a cache comprising a plurality of cache lines, wherein each cache line includes a corresponding repeat read indicator among the plurality of repeat read indicators; and The PE among the plurality of PEs is further configured to: During the first read of the consistent granularity: The corresponding cache line among the plurality of cache lines allocated to the cache; and The repeat read indicator of the cache line is initialized to a value of zero (0); as well as When it is determined that a locally executed read operation results in a hit on the cache line, the repeat read indicator on the cache line is incremented.

3. The processor-based device of claim 2, wherein each of the plurality of repeat read indicators comprises one or more bits.

4. The processor-based device according to claim 2, wherein: Each of the plurality of PEs further includes a snooping eviction table, the snooping eviction table comprising a plurality of snooping eviction table entries, wherein each snooping eviction table entry includes: Consistent granular address; Previously repeated read indicator; and Valid indicator; and The PE among the plurality of PEs is further configured to: When a cache line in the plurality of cache lines of the cache is evicted due to a snooping invalidation: Assign snoop table entries to the plurality of snoop table entries; The address of the consistency granule of the snooping table entry is initialized to the address of the consistency granule; The previously repeated read indicator of the peeping table entry is initialized to the value of the repeated read indicator of the cache line; and Initialize the validity indicator of the snooping eviction table entry to indicate that the snooping eviction table entry is valid; and When it is determined that the locally executed read operation resulted in a cache miss but a valid matching snoop evict table entry: Increment the previously repeated read indicator of the valid snooping eviction table entry; Allocate a new cache line corresponding to the locally executed read operation; The repeated read indicator of the new cache line is initialized to the value of the previous repeated read indicator of the valid peek-out evicted table entry; and Update the validity indicator of the valid snoop eviction table entry to indicate that the valid snoop eviction table entry is invalid.

5. The processor-based device according to claim 1, wherein: Each of the plurality of PEs further includes: Includes caches with multiple cache lines; and A snoop table containing multiple snoop entries. Each entry in the snooping expulsion table includes: Consistent granular address; The corresponding repeat read indicator among the plurality of repeat read indicators; and Valid indicator; and The PE among the plurality of PEs is further configured to: When a cache line in the plurality of cache lines of the cache is evicted due to a snooping invalidation: Assign snoop table entries to the plurality of snoop table entries; The address of the consistency granule of the snooping eviction table entry is initialized to the address of the consistency granule corresponding to the cache line; The repeated read indicator of the snooping eviction table is initialized to a value of zero (0); and Initialize the validity indicator to indicate that the snooping eviction table entry is valid; and When it is determined that a read operation results in a cache miss but a matching valid peek eviction table entry, the repeated read indicator of the valid peek eviction table entry is incremented.

6. The processor-based device of claim 5, wherein each of the plurality of repeat read indicators comprises one bit.

7. The processor-based device of claim 1, wherein the cache coherence bus command includes one of the following: a non-allocation write bus command, a read bus command with write intent, and a promotion to a writable bus command.

8. The processor-based device according to claim 1, wherein: The one or more protocol preference indicators include the write-to-update attribute of the cache coherence bus command of the primary PE; and The main PE is also configured as follows: Based on the repeated read indicator among the plurality of repeated read indicators, predict whether the write invalidation protocol is preferred; In response to the prediction that the write invalidation protocol is preferred, assert the write-prevention update attribute of the cache coherence bus command; as well as In response to the prediction that the write invalidation protocol is not preferred, the assertion of the anti-write update attribute of the cache coherence bus command is lifted.

9. The processor-based device of claim 8, wherein the COP is configured to send a response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooping PE by being configured to: in response to receiving a cache coherence bus command having the cache coherence bus command with the write update protection attribute asserted, sending the response message to each of the master PE and the at least one snooping PE, the response message including a deasserted write update valid attribute, the deasserted write update valid attribute indicating that the write invalidation protocol is selected for the memory storage operation.

10. The processor-based device according to claim 1, wherein: The one or more protocol preference indicators include a write update request attribute for a snooping response, the snooping response being associated with a snooping command sent by the COP and sent to the COP by the snooping PE of the at least one snooping PE; and The spy PE is configured as follows: Based on the repeated read indicator among the plurality of repeated read indicators, predict whether the write update protocol is preferred; In response to the prediction that the write-update protocol is preferred, assert the write-update request attributes of the snooping response; as well as In response to the prediction that the write-update protocol is not preferred, the assertion of the write-update request attribute of the snooping response is lifted.

11. The processor-based device according to claim 1, wherein: The COP is also configured to: Receive at least one spying response corresponding to the at least one spy PE; as well as Determine whether any of the at least one snooping responses includes the asserted write update request attribute; and The COP is configured to send a response message indicative of the cache coherence protocol to each of the primary PE and at least one snooping PE, configured as follows: In response to determining that any of the at least one snooping responses includes an asserted write update request attribute, the response message is sent to each of the master PE and the at least one snooping PE, the response message including an asserted write update valid attribute indicating that the write update protocol is selected for the memory storage operation; as well as In response to determining that none of the at least one snooping responses includes an asserted write update request attribute, the response message is sent to each of the master PE and the at least one snooping PE, the response message including a deasserted write update valid attribute, the deasserted write update valid attribute indicating that the write invalidation protocol is selected for the memory storage operation.

12. The processor-based device according to claim 11, wherein: Each of the at least one snooper PEs corresponding to the snooping response that includes the asserted write update request attribute in the at least one of the snooping responses is configured to: perform a write update operation in response to the response message including the asserted write update valid attribute; and Each of the at least one snooper PEs corresponding to the snooper response that includes the deasserted write update request attribute in the at least one snooper response is configured to perform a write invalidation operation in response to the response message including the asserted write update valid attribute.

13. A method for dynamically selecting a cache coherence protocol in a processor-based device, comprising: The master PE, one of the multiple processing elements PE in a processor-based device, sends cache coherence bus commands to the central sorting point circuit COP as part of a memory storage operation. A first protocol preference indicator is generated by one of the plurality of PEs based on the repeated read indicators among the plurality of repeated read indicators of the PE, wherein each of the plurality of repeated read indicators corresponds to a consistency particle read by the PE and indicates whether the consistency particle is repeatedly read by the PE; Send the first protocol preference indicator to the COP; In response to receiving the cache coherence bus command, the COP dynamically selects one of the write invalidation protocol and the write update protocol as the cache coherence protocol for maintaining cache coherence on a per-store basis, based on one or more protocol preference indicators provided by the master PE, at least one snooper PE among the plurality of PEs and one or more of the COPs, and the one or more protocol preference indicators include the first protocol preference indicator. as well as The COP sends a response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooping PE.

14. The method of claim 13, further comprising: During the first read by the consistent particles of the PE: The PE allocates a corresponding cache line from a plurality of cache lines of the PE's cache, wherein each cache line includes a corresponding repeat read indicator from a plurality of repeat read indicators; as well as The PE initializes the repeat read indicator of the cache line to a value of zero (0); as well as When it is determined that a locally executed read operation results in a hit on the cache line, the repeat read indicator on the cache line is incremented by the PE.

15. The method of claim 14, wherein each of the plurality of repeat read indicators comprises one or more bits.

16. The method of claim 14, further comprising: When a cache line in the cache of the PE is evicted due to a snooping invalidation: The PE assigns snoop table entries from a plurality of snoop table entries in the PE's snoop table, wherein each snoop table entry includes: Consistent granular address; Previously repeated read indicator; and Valid indicator; The PE initializes the address of the consistency granule of the snooping table entry to the address of the consistency granule; The PE initializes the previously repeated read indicator of the peeping table entry to the value of the repeated read indicator of the cache line; and The PE initializes the validity indicator of the snooping eviction table entry to indicate that the snooping eviction table entry is valid; and When the PE determines that the locally executed read operation results in a cache miss but a valid matching snoop evict table entry: The PE increments the previously repeated read indicator of the valid snooping eviction table entry; The PE allocates a new cache line corresponding to the locally executed read operation; The PE initializes the repeated read indicator of the new cache line to the value of the previous repeated read indicator of the valid eviction table entry; and The PE updates the validity indicator of the valid snoop eviction table entry to indicate that the valid snoop eviction table entry is invalid.

17. The method of claim 13, further comprising: When a cache line is evicted from one of the multiple cache lines cached by the PE due to a snooping invalidity: The PE assigns snoop table entries from a plurality of snoop table entries in the PE's snoop table, wherein each snoop table entry includes: Consistent granular address; The corresponding repeat read indicator among the plurality of repeat read indicators; and Valid indicator; The PE initializes the address of the consistency granule of the snooping eviction table entry to the address of the consistency granule corresponding to the cache line; The PE initializes the repeated read indicator of the snooping eviction table to a value of zero (0); and The PE initializes the validity indicator of the snooping eviction table entry to indicate that the snooping eviction table entry is valid; and When the PE determines that a read operation results in a miss but matching valid peek eviction table entry on the cache, the PE increments the repeat read indicator of the valid peek eviction table entry.

18. The method of claim 17, wherein each of the plurality of repeat read indicators comprises one bit.

19. The method of claim 13, wherein the cache coherence bus command includes one of the following: a non-allocation write bus command, a read bus command with write intent, and a promotion to a writable bus command.

20. The method of claim 13, wherein: The one or more protocol preference indicators include the write-to-update attribute of the cache coherence bus command of the primary PE; and The method further includes: The main PE predicts that the write invalidation protocol is preferred based on the repeated read indicator among the plurality of repeated read indicators. as well as In response to the prediction that the write invalidation protocol is preferred, the master PE asserts the write-prevention update attribute of the cache coherence bus command.

21. The method of claim 20, wherein sending the response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooping PE comprises: In response to receiving the cache coherence bus command with the preemptive write update attribute asserted, the COP sends the response message to each of the master PE and at least one snooping PE, the response message including the deasserted write update valid attribute, the deasserted write update valid attribute indicating that the write invalidation protocol is selected for the memory storage operation.

22. The method according to claim 13, wherein: The one or more protocol preference indicators include a write update request attribute for a snooping response, the snooping response being associated with a snooping command sent by the COP and sent to the COP by the snooping PE of the at least one snooping PE; and The method further includes: Based on the repeated read indicator among the plurality of repeated read indicators, the spy PE predicts that the write update protocol is preferred; In response to the prediction that the write-update protocol is preferred, the peeping PE asserts the write-update request attributes of the peeping response.

23. The method of claim 13, further comprising: The COP receives at least one spy response corresponding to the at least one spy PE; as well as The COP determines that the snoop response in the at least one snoop response includes the asserted write update request attribute; and The response message sent to each of the primary PE and at least one snooping PE, indicating the selected cache coherence protocol, includes: In response to determining that the snooping response in the at least one snooping response includes an asserted write update request attribute, the COP sends the response message to each of the master PE and the at least one snooping PE, the response message including an asserted write update valid attribute indicating that the write update protocol is selected for the memory storage operation.

24. A non-transient computer-readable medium having stored thereon computer-executable instructions that, when executed by a processor-based device, cause the processor-based device to: The master PE among the multiple processing elements PE of the processor-based device sends cache coherence bus commands to the central sorting point circuit COP as part of a memory storage operation. A first protocol preference indicator is generated by one of the plurality of PEs based on the repeated read indicators among the plurality of repeated read indicators of the PE, wherein each of the plurality of repeated read indicators corresponds to a consistency particle read by the PE and indicates whether the consistency particle is repeatedly read by the PE; Send the first protocol preference indicator to the COP of the processor-based device; In response to receiving the cache coherence bus command, the COP dynamically selects one of the write invalidation protocol and the write update protocol as the cache coherence protocol for maintaining cache coherence on a per-store basis, based on one or more protocol preference indicators provided by the master PE, at least one snooper PE among the plurality of PEs and one or more of the COPs, and the one or more protocol preference indicators include the first protocol preference indicator. as well as The COP sends a response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooping PE.

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