Semiconductor device for electric power

Abstract

The silicon substrate (10) has first to fourth semiconductor regions (11 to 14). The third semiconductor region (13) is separated from the first semiconductor region (11) of the first conductivity type by the second semiconductor region (12) of the second conductivity type. The fourth semiconductor region (14) of the second conductivity type is separated from the second semiconductor region (12) by the third semiconductor region (13). The first electrode (60) is provided on the first surface (F1). The barrier metal layer (20) is provided on the first portion (F2a) of the second surface (F2). The second electrode (70) is provided on the second surface (F2) and is separated from the first portion (F2a) of the second surface (F2) by the barrier metal layer (20). The second electrode (70) includes an Al–Si layer (71) in contact with the second portion (F2b) of the second surface (F2) and an Al layer (72) separated from the second portion (F2b) of the second surface (F2) by the Al–Si layer (71).

Description

Technical Field

[0001] The present invention relates to a semiconductor device for electric power, and particularly to a semiconductor device for electric power having a silicon substrate. Background Art

[0002] As one type of semiconductor device for electric power, an RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) in which an IGBT (Insulated Gate Bipolar Transistor) and a freewheeling diode are integrated on one chip is known. The RC-IGBT is used, for example, as a switching element for an inverter.

[0003] According to Japanese Unexamined Patent Application Publication No. 2013-48230 (Patent Document 1), the semiconductor device has a metal collector / cathode electrode formed on the lower surface of the silicon substrate and a metal emitter / anode electrode formed on the upper surface of the silicon substrate. The collector / cathode electrode is ohmically joined to the silicon substrate. The emitter / anode electrode has a portion ohmically joined to the silicon substrate and a portion Schottky-joined to the silicon substrate.

[0004] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2013-48230

[0005] Summary of the Invention

[0006] ​If a pure Al layer is bonded to a silicon substrate, Al spikes are likely to be generated in the silicon substrate due to the diffusion of Al atoms from the pure Al layer. As a representative method for preventing the generation of Al spikes, there is a method of using an Al-Si layer (an alloy layer having Al element as a main component and Si element as an element added thereto) instead of the pure Al layer. However, in this case, since Si atoms diffused from the Al-Si layer precipitate on the silicon substrate, Si nodules are likely to be generated. Both Al spikes and Si nodules may have an adverse effect on the electrical characteristics of a power semiconductor device. The generation of Al spikes and Si nodules is prevented by inserting a barrier metal layer through which Al atoms and Si atoms hardly diffuse between the electrode and the silicon substrate. The bonding between such a barrier metal layer and the silicon substrate is not a Schottky bond and is likely to be an ohmic bond. For example, a silicide, TiSi, is formed between a typical barrier metal layer, i.e., a Ti layer, and the silicon substrate, and as a result, the bonding between the two becomes an ohmic bond. Thus, when only relying on simply providing a barrier metal layer to prevent the generation of Al spikes and Si nodules, all the bonds become ohmic bonds. Accordingly, a Schottky barrier diode cannot be used as a freewheeling diode of an RC-IGBT. The present invention has been made to solve the above problems, and an object thereof is to provide a power semiconductor device capable of integrating an IGBT element and a Schottky barrier diode element and suppressing the generation of Al spikes and Si nodules.

[0007] A power semiconductor device according to one aspect of the present invention includes a silicon substrate, a gate insulating film, a gate electrode, a first electrode, a barrier metal layer, and a second electrode. The silicon substrate has a first surface and a second surface opposite to the first surface and having a first portion and a second portion. The silicon substrate includes: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type different from the first conductivity type; a third semiconductor region having the first conductivity type, which is separated from the first semiconductor region by the second semiconductor region; and a fourth semiconductor region having the second conductivity type, which is separated from the second semiconductor region by the third semiconductor region. The gate insulating film extends between the first semiconductor region and the third semiconductor region and faces the second semiconductor region. The gate electrode faces the second semiconductor region with the gate insulating film interposed therebetween. The first electrode is provided on the first surface of the silicon substrate and is in contact with the third semiconductor region and the fourth semiconductor region. The barrier metal layer is provided on the first portion of the second surface of the silicon substrate. The second electrode is provided on the second surface of the silicon substrate and is separated from the first portion of the second surface of the silicon substrate by the barrier metal layer. The second electrode includes an Al-Si layer in contact with the second portion of the second surface of the silicon substrate and an Al layer separated from the second portion of the second surface of the silicon substrate by the Al-Si layer.

[0008] Another type of semiconductor device for power applications according to the present invention includes a silicon substrate, a gate insulating film, a gate electrode, a first electrode, a barrier metal layer, a second electrode, and a polysilicon layer. The silicon substrate has a first surface and a second surface opposite to the first surface, and the second surface has a first portion and a second portion. The silicon substrate includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type different from the first conductivity type; a third semiconductor region of the first conductivity type separated from the first semiconductor region by the second semiconductor region; and a fourth semiconductor region of the second conductivity type separated from the second semiconductor region by the third semiconductor region. The gate insulating film extends between the first semiconductor region and the third semiconductor region and faces the second semiconductor region. The gate electrode faces the second semiconductor region with the gate insulating film therebetween. The first electrode is disposed on the first surface of the silicon substrate and contacts the third semiconductor region and the fourth semiconductor region. The barrier metal layer is disposed on the first portion of the second surface of the silicon substrate. The second electrode is disposed on the second surface of the silicon substrate and is separated from the first portion of the second surface of the silicon substrate by the barrier metal layer. The second electrode includes an Al-Si layer that contacts the second portion of the second surface of the silicon substrate. The polysilicon layer is away from the second surface of the silicon substrate and contacts the second electrode.

[0009] Effects of the Invention

[0010] In a semiconductor device for power applications according to one aspect of the present invention, the second electrode is ohmically bonded to the first portion of the second surface of the silicon substrate via the barrier metal layer, and is Schottky-bonded to the second portion of the second surface of the silicon substrate using the Al-Si layer. Thus, the second electrode can act as an ohmic electrode for an IGBT element on the first portion of the second surface of the silicon substrate, and can act as a Schottky electrode for a Schottky barrier diode element on the second portion of the second surface of the silicon substrate. Also, generation of Si nodules and Al spikes at the first portion of the second surface of the silicon substrate can be suppressed by the barrier metal layer. In addition, the Al layer is separated from the second portion of the second surface of the silicon substrate by the Al-Si layer, thereby suppressing generation of Al spikes at the second portion of the second surface of the silicon substrate. Further, since the second electrode includes an Al layer, compared with the case where the second electrode made of an Al-based material (a material mainly composed of Al) is composed only of the Al-Si layer, the Si content in the second electrode can be suppressed, and thus generation of Si nodules at the second portion of the second surface of the silicon substrate can be suppressed. Accordingly, in a semiconductor device for power applications in which an IGBT element and a Schottky barrier diode element are integrated, generation of Al spikes and Si nodules can be suppressed.

[0011] According to another aspect of the semiconductor device for electric power of the present invention, the second electrode is ohmically joined to the first part of the second surface of the silicon substrate via a barrier metal layer, and is Schottky joined to the second part of the second surface of the silicon substrate using an Al—Si layer. Thus, the second electrode can function as an ohmic electrode for an IGBT element above the first part of the second surface of the silicon substrate, and can function as a Schottky electrode for a Schottky barrier diode element above the second part of the second surface of the silicon substrate. Further, generation of Si nodules at the first part of the second surface of the silicon substrate can be suppressed by the barrier metal layer. Further, a polysilicon layer which is separated from the second surface of the silicon substrate and in contact with the second electrode is provided. Thus, at least a part of Si atoms diffused from the Al—Si layer generates Si nodules on the surface of the polysilicon layer instead of on the surface of the silicon substrate. Thereby, generation of Si nodules can be suppressed.

[0012] The object, features, aspects and advantages of the present invention will become clearer from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram schematically showing the structure of the semiconductor device for electric power in Embodiment 1.

[0014] Figure 2 is a cross-sectional view schematically showing the structure of the semiconductor device for electric power in Embodiment 1.

[0015] Figure 3 is a representation of Figure 2 a partial cross-sectional view of Region III.

[0016] Figure 4 is a partial cross-sectional view showing the first comparative example through a field of view corresponding to Figure 3 the same.

[0017] Figure 5 is a partial cross-sectional view showing the second comparative example through a field of view corresponding to Figure 3 the same.

[0018] Figure 6 is a partial cross-sectional view schematically showing the structure of the semiconductor device for electric power in Embodiment 2 through a field of view corresponding to Figure 3 the same.

[0019] Figure 7 is a partial cross-sectional view schematically showing the structure of the semiconductor device for electric power in Embodiment 3 through a field of view corresponding to Figure 3 the same.

[0020] Figure 8 is a partial cross-sectional view showing through a field of view corresponding to Figure 3A partial cross-sectional view schematically showing the structure of the semiconductor device for power use in Embodiment 4 corresponding to the corresponding visual field.

[0021] Figure 9 is through Figure 3 A partial cross-sectional view schematically showing the structure of the semiconductor device for power use in Embodiment 5 corresponding to the corresponding visual field. Detailed implementation manners

[0022] Hereinafter, embodiments will be described based on the drawings. In addition, in the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their descriptions will not be repeated.

[0023] <Embodiment 1>

[0024] Figure 1 A circuit diagram schematically showing the structure of an RC-IGBT 101 (semiconductor device for power use) in Embodiment 1. The RC-IGBT 101 is a semiconductor device for power use in which an IGBT element 201 and a Schottky barrier diode element 202 are integrated on one chip. The Schottky barrier diode element 202 has a function as a freewheeling diode by being reversely connected in parallel with the IGBT element 201. The RC-IGBT 101 has a gate electrode 51, a first electrode 60, and a second electrode 70. The first electrode 60 has a function as a collector electrode of the IGBT element 201 and a function as a cathode electrode of the Schottky barrier diode element 202. The second electrode 70 has a function as an emitter electrode of the IGBT element 201 and a function as an anode electrode of the Schottky barrier diode element 202. In addition, although details will be described later, the freewheeling diode of the RC-IGBT 101 does not necessarily have to be composed only of the Schottky barrier diode element 202, and other diode elements can also be combined.

[0025] Figure 2 A cross-sectional view schematically showing the structure of the RC-IGBT 101. The RC-IGBT 101 has a silicon substrate 10, a gate insulating film 41, a gate electrode 51, a barrier metal layer 20, and an interlayer insulating film 43. The silicon substrate 10 has a lower surface F1 (first surface) and an upper surface F2 (second surface opposite to the first surface). The lower surface F1 has an IGBT lower surface portion F1a and a diode lower surface portion F1b. The upper surface F2 has an IGBT upper surface portion F2a (first portion) and a diode upper surface portion F2b (second portion). In addition, Figure 2 shows a structure in which the boundary between the IGBT lower surface portion F1a and the diode lower surface portion F1b and the boundary between the IGBT upper surface portion F2a and the diode upper surface portion F2b are aligned in the in-plane direction. However, as a modification, their boundaries can also be offset from each other.

[0026] The silicon substrate 10 has a first semiconductor region 11 of n-type (first conductivity type), a second semiconductor region 12 of p-type (second conductivity type different from the first conductivity type), a third semiconductor region 13 of n-type, a fourth semiconductor region 14 of p-type, and a p + contact region 19. The third semiconductor region 13 is separated from the first semiconductor region 11 by the second semiconductor region 12. The fourth semiconductor region 14 is separated from the second semiconductor region 12 by the third semiconductor region 13.

[0027] The first semiconductor region 11 is the n-emitter region of the IGBT element 201 and forms a part of the upper surface portion F2a of the IGBT. The second semiconductor region 12 is the p-body region of the IGBT element 201. The third semiconductor region 13 has an n - drift layer 13D, an n-buffer layer 13B, an n-Schottky junction layer 13S of the Schottky barrier diode element 202, and an n + contact layer 13C of the Schottky barrier diode element 202. The fourth semiconductor region 14 is the p + collector region of the IGBT element 201 and forms the lower surface portion F1a of the IGBT. p + The p-contact region 19 extends from the upper surface portion F2a of the IGBT to reach the second semiconductor region (p-body region). p + The impurity concentration of the p-contact region 19 is higher than that of the second semiconductor region (p-body region).

[0028] Grooves TR are provided in the upper surface portion F2a of the IGBT and the upper surface portion F2b of the diode of the silicon substrate 10, respectively. Further, an interlayer insulating film 43 that covers the grooves TR in a cross-sectional view ( Figure 2 field of view) is provided above the upper surface portion F2a of the IGBT and above the upper surface portion F2b of the diode of the silicon substrate 10. The interlayer insulating film 43 may be an oxide film, for example, a silicon oxide film. A gate electrode 51 is disposed in the groove TR of the upper surface portion F2a of the IGBT with a gate insulating film 41 interposed therebetween. The gate electrode 51 is insulated from the stack of the barrier metal layer 20 and the second electrode 70 by the interlayer insulating film 43. A dummy electrode 52 is disposed in the groove TR of the upper surface portion F2b of the diode with a dummy insulating film 42 interposed therebetween. Preferably, a structure (not shown) for electrically connecting (typically, short-circuiting) the dummy electrode 52 and the second electrode 70 to each other is provided. The gate insulating film 41 extends between the first semiconductor region 11 (n-emitter region) and the third semiconductor region 13 (n - drift layer 13D) and faces the second semiconductor region 12 (p-body region). The gate electrode 51 faces the second semiconductor region 12 (p-body region) with the gate insulating film 41 interposed therebetween.

[0029] The first electrode 60 is disposed above the lower surface F1 of the silicon substrate 10. Further, the first electrode 60 is in contact with the n + contact layer 13C of the third semiconductor region 13 and the fourth semiconductor region 14 (p + collector region), whereby the first electrode 60 is ohmically joined to the n + contact layer 13C of the third semiconductor region 13 and the fourth semiconductor region 14 (p + collector region) respectively.

[0030] The barrier metal layer 20 is disposed above the IGBT upper surface portion F2a of the silicon substrate 10. The barrier metal layer 20 is made of a material suitable for suppressing the diffusion of Al atoms and Si atoms. Such a material is, for example, titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), titanium tungsten (TiW), or a composite material using two or more of them. The barrier metal layer 20 is ohmically joined to the first semiconductor region 11 (n emitter region) and the p + contact region 19 above the IGBT upper surface portion F2a of the silicon substrate 10 respectively. The reason for this joining being an ohmic joining is that a silicide is formed between the barrier metal layer 20 and the silicon substrate 10.

[0031] The second electrode 70 is disposed above the upper surface F2 of the silicon substrate 10 and is separated from the IGBT upper surface portion F2a by the barrier metal layer 20. The second electrode 70 includes an Al-Si layer 71 and an Al layer 72. The Al-Si layer 71 is in contact with the diode upper surface portion F2b of the silicon substrate 10. The Al layer 72 is separated from the diode upper surface portion F2b of the silicon substrate 10 by the Al-Si layer 71. The second electrode 70 has a stacked structure of the Al-Si layer 71 and the Al layer 72 at least above the diode upper surface portion F2b of the silicon substrate 10. As shown in Figure 2 , the second electrode 70 also has a stacked structure of the Al-Si layer 71 and the Al layer 72 above the IGBT upper surface portion F2a of the silicon substrate 10. In this case, the Al-Si layer 71 and the Al layer 72 may have a common pattern in the in-plane direction. Since the stacked structure of the Al-Si layer 71 and the Al layer 72 is made of an Al-based material, it has high buffer characteristics (stress relaxation characteristics). Thus, by making the thickness of this stacked structure thick enough, the buffer characteristics required for relaxing the stress generated by bonding or the like above the second electrode 70 can be sufficiently ensured. From this viewpoint, it is preferable that the total thickness of the Al-Si layer 71 and the Al layer 72, which is the thickness of the stacked structure, is greater than or equal to 3 μm. In addition, this thickness can generally be less than or equal to 7 μm.

[0032] Here, the Al-Si layer is defined as a layer composed of an alloy in which Si of 0.5 wt% or more and 3 wt% or less is added to Al as the main component. In the Al-Si layer, it is preferable that elements other than Si are substantially not added to Al as the main component. In this case, the Al-Si layer is composed of a binary alloy of Al and Si. In addition, the Al layer is defined as a layer containing Al as the main component and having an Si content of 0.3 wt% or less. If Al containing only impurity elements of 0.3 wt% or less is defined as pure Al, the Al layer may be a pure Al layer. Further, in the laminated structure of the Al-Si layer and the Al layer, a region having an intermediate composition between the composition of the Al-Si layer and the composition of the Al layer may be formed between the Al-Si layer and the Al layer due to atomic diffusion or the like.

[0033] Figure 3 is a partial cross-sectional view showing Figure 2 region III. The Al-Si layer 71 has a contact portion 71C disposed in the opening OP of the interlayer insulating film 43 in the in-plane direction ( Figure 3 the lateral direction in), and is in direct contact with the upper surface portion F2b of the diode of the silicon substrate 10. The contact portion 71C is a portion of the Al-Si layer 71 located above the interface FS between the Al-Si layer 71 and the silicon substrate 10 in the thickness direction. The Al layer 72 has a portion disposed above the contact portion 71C of the Al-Si layer 71. In other words, the Al layer 72 has a portion laminated with the contact portion 71C of the Al-Si layer 71 in the thickness direction ( Figure 3 the longitudinal direction in).

[0034] Figure 4 is a partial cross-sectional view showing the RC-IGBT 100S in the first comparative example through the field of view corresponding to Figure 3 . In this comparative example, the entire second electrode 70S is composed of an Al-Si layer. The Al-Si layer is typically formed by sputtering film formation. Preferably, this sputtering film formation is performed while heating the silicon substrate 10. In addition, heat treatment is sometimes performed after forming the Al-Si layer. In either case, the Al-Si layer is subjected to a temperature change from a high temperature to room temperature. When the temperature drops, Si in the Al-Si layer precipitates on the interface FS between the Al-Si layer and the silicon substrate 10 (in the figure, refer to the dotted arrow), thereby generating Si nodules SN. In this comparative example, since the entire second electrode 70S is an Al-Si layer, the Si content of the second electrode 70S is high, and thus, Si nodules SN are easily generated. The thickness of the Si nodules SN ( Figure 4 the longitudinal dimension in) reaches about 1 μm, for example.

[0035] When thermal expansion and contraction caused by temperature changes in the use environment or external forces caused by bonding processes on the second electrode 70S are applied, since the Si nodule SN is harder than the second electrode 70S made of an Al-based material, stress concentration is likely to occur at the site where the Si nodule SN is formed in the upper surface portion F2b of the diode on the silicon substrate 10. As a result of this stress concentration, first, local deterioration of crystallinity (local variation in the Si atomic spacing in the silicon substrate 10) sometimes occurs. Due to the deterioration of crystallinity, the bandgap structure changes, and thus, the Schottky characteristics change. As a result, the rectifying property of the Schottky barrier diode element deteriorates. Specifically, the forward voltage drop or reverse breakdown leakage current increases. Second, the flatness of the upper surface portion F2a of the IGBT on the silicon substrate 10 sometimes deteriorates, in other words, scratches are formed. At the site where the flatness deteriorates, when the IGBT element in the off state holds a high voltage, the electric field tends to concentrate. As a result, the breakdown leakage current increases. Thus, if the entire second electrode 70S is composed of an Al-Si layer, the electrical characteristics of the RC-IGBT 101 are likely to deteriorate.

[0036] Figure 5 is shown by the view corresponding to Figure 3 and is a partial cross-sectional view of the RC-IGBT 100A in the second comparative example. In this comparative example, the entire second electrode 70A is composed of an Al layer. As a result, at high temperatures, an alloying reaction between the Si atoms of the silicon substrate 10 and the Al atoms of the Al layer is likely to occur. As a result, Al spikes AS are likely to be generated at the interface FS. The Al spikes AS also deteriorate the electrical characteristics of the RC-IGBT 101 in the same way as the Si nodules SN ( Figure 4 ).

[0037] In the RC-IGBT 101 of the present embodiment, regarding the thickness of the Al-Si layer 71, in order to prevent the generation of Si nodules SN ( Figure 4 ), it is preferably not too large, and in order to prevent the generation of Al spikes AS ( Figure 5 ), it is preferably not too small. From this viewpoint, it is preferable that the thickness of the Al-Si layer 71 is greater than or equal to 0.5 μm and less than or equal to 2 μm. On the other hand, it is difficult to ensure sufficient buffering only with the Al-Si layer 71 having a thickness greater than or equal to 0.5 μm and less than or equal to 2 μm. To compensate for this, it is preferable that the thickness of the Al layer 72 is greater than or equal to 1 μm. In addition, the thickness of the Al layer 72 can generally be less than or equal to 5 μm.

[0038] Next, an example of a method for forming the second electrode 70 in the first embodiment will be briefly described. First, a silicon substrate 10 having an upper surface F2 is prepared, and an interlayer insulating film 43 is provided on the upper surface F2. At this point, doping into the silicon substrate 10 and formation of the trench TR can be completed. The imparting of the pattern shape to the interlayer insulating film 43 can be performed by a lift-off method or by a photolithography method and an etching method. Next, a barrier metal layer 20 is formed on the IGBT upper surface portion F2a of the upper surface F2. As shown in Figure 2 , the pattern of the barrier metal layer 20 is disposed above the IGBT upper surface portion F2a and is offset from at least a part of the diode upper surface portion F2b. The imparting of such a pattern shape to the barrier metal layer 20 can be performed by a lift-off method or by a photolithography method and an etching method. Next, an Al—Si layer 71 and an Al layer 72 are formed on the upper surface F2 by a sputtering method. Thereby, the second electrode 70 is formed.

[0039] According to the present embodiment, the second electrode 70 ( Figure 2 ) is ohmically joined to the IGBT upper surface portion F2a of the silicon substrate 10 via the barrier metal layer 20 and is Schottky-joined to the diode upper surface portion F2b of the silicon substrate 10 using the Al—Si layer. Thereby, the second electrode 70 can function as an ohmic electrode for the IGBT element 201 above the IGBT upper surface portion F2a of the silicon substrate 10, and can function as a Schottky electrode for the Schottky barrier diode element 202 above the diode upper surface portion F2b of the silicon substrate 10. Further, generation of Si nodules and Al spikes at the IGBT upper surface portion F2a of the silicon substrate 10 can be suppressed by the barrier metal layer 20. In addition, the Al layer 72 is separated from the diode upper surface portion F2b of the silicon substrate 10 by the Al—Si layer, whereby generation of an Al spike AS ( Figure 5 ) at the diode upper surface portion F2b of the silicon substrate 10 can be suppressed. Further, since the second electrode 70 includes the Al layer 72, the Si content of the second electrode 70 can be suppressed as compared with the case where the second electrode 70 made of an Al-based material is composed only of the Al—Si layer, and thus generation of Si nodules SN ( Figure 4 ) at the diode upper surface portion F2b of the silicon substrate 10 can be suppressed. Thereby, in the power semiconductor device in which the IGBT element 201 and the Schottky barrier diode element 202 are integrated, generation of Al spikes and Si nodules can be suppressed.

[0040] The second electrode 70 has a laminated structure including an Al-Si layer substantially containing Si atoms and an Al layer 72 substantially not containing Al atoms at least above the upper surface portion F2b of the diode on the silicon substrate 10. Thereby, the thickness of the second electrode 70 made of an Al-based material can be ensured, and the Si content in the second electrode 70 can be suppressed. Thereby, the generation of Si nodules can be suppressed. The portion of the region above the upper surface portion F2b of the diode on the silicon substrate 10 where the interlayer insulating film 43 ( Figure 2 ) is disposed does not become a diffusion source of Si atoms. Thereby, the generation of Si nodules can be further suppressed.

[0041] The Al layer 72 has a portion disposed above the contact portion 71C ( Figure 3 ) of the Al-Si layer. Thereby, the portion of the second electrode 70 above the contact portion 71C substantially does not become a diffusion source of Si atoms. Thereby, the generation of Si nodules can be further suppressed.

[0042] At each of the IGBT upper surface portion F2a and the diode upper surface portion F2b of the silicon substrate 10, a trench TR ( Figure 2 ) covered by the interlayer insulating film 43 is provided in a plan view. Thereby, not only can the interlayer insulating film 43 be used as a structure for suppressing the generation of Si nodules, but also as a structure for insulating the trench TR.

[0043] In addition, in the RC-IGBT 101, in addition to the Schottky barrier diode element 202, other diode elements can also function as freewheeling diodes. For example, in the RC-IGBT 101, a pn junction is formed by an n-type third semiconductor region 13, a p-type second semiconductor region 12, and a contact region 19, and the first electrode 60 and the barrier metal layer 20 are respectively ohmically connected to the n-type third semiconductor region and the p-type contact region 19. Thereby, a pn junction diode element reversely connected in parallel with the IGBT element 201 is formed between the first electrode 60 and the second electrode 70. This pn junction diode element can also function as a freewheeling diode together with the Schottky barrier diode element 202.

[0044] In addition, in the RC-IGBT 101, trenches TR are formed not only at the IGBT upper surface portion F2a but also at the diode upper surface portion F2b, but the trenches TR at the diode upper surface portion F2b can be omitted. In this case, the dummy insulating film 42 and the dummy electrode 52 can also be omitted.

[0045] <Embodiment 2>

[0046] Figure 6 is through Figure 3(Embodiment 1) A partial cross-sectional view schematically showing the structure of the RC-IGBT 102 (power semiconductor device) in Embodiment 2 corresponding to the field of view. In this Embodiment 2, at least a part of the Al layer 72 is directly disposed on the interlayer insulating film 43. In Figure 6 In the example shown, the Al layer 72 is directly disposed on the entire upper surface of the interlayer insulating film 43. Further, in this Embodiment 2, different from the aforementioned Embodiment 1, the Al layer 72 does not have a portion disposed above the contact portion 71C of the Al-Si layer 71 (a portion disposed above the contact portion 71C of the Al-Si layer 71 in the thickness direction). In other words, the Al layer 72 is disposed offset from the region above the interface FS between the Al-Si layer 71 and the silicon substrate 10. In Figure 6 In the example shown, the Al layer 72 is disposed in the in-plane direction only outside the region surrounded by the upper ends (ends away from the silicon substrate 10) of the side walls of the opening OP of the interlayer insulating film 43.

[0047] In addition, in Figure 6 , only the portion above the diode upper surface portion F2b in the second electrode 70 is shown. The structure of the portion above the IGBT upper surface portion F2a (refer to Figure 2 ) in the second electrode 70 is arbitrary. For example, it may be the same structure as that shown in Figure 6 . Regarding the structures other than the above, since they are substantially the same as the structures in the above Embodiment 1, the same reference numerals are assigned to the same or corresponding elements, and the description thereof will not be repeated.

[0048] Next, an example of a method for forming the second electrode 70 in this Embodiment 2 will be briefly described. First, in the same manner as in Embodiment 1, a barrier metal layer 20 is formed on the IGBT upper surface portion F2a of the upper surface F2 of the silicon substrate 10. Next, the Al-Si layer 71 is formed by film formation on the entire upper surface F2 by sputtering and patterning of the layer formed by this film formation by photolithography and etching. Next, the Al layer is formed by sputtering, and then, by chemical mechanical polishing (CMP: Chemical Mechanical Polishing), unnecessary portions of the Al layer are removed, thereby forming the Al layer 72. Thus, the second electrode 70 is formed.

[0049] At least a part of the Al layer 72 is directly disposed on the interlayer insulating film 43. Thereby, the Si content in the portion of the second electrode 70 directly disposed on the interlayer insulating film 43 is suppressed. Thereby, generation of Si nodules due to diffusion of Si atoms from this portion can be avoided.

[0050] <Embodiment 3>

[0051] Figure 7 It schematically shows a partial cross-sectional view of the structure of the RC-IGBT 103 (power semiconductor device) in Embodiment 3 through the corresponding field of view. Figure 3

[0052] In this embodiment, the Al layer 72 has a portion directly disposed on the interlayer insulating film 43. Further, the Al layer 72 has a portion disposed on the Al-Si layer 71, and in particular, has a portion disposed on the contact portion 71C.

[0053] The Al-Si layer 71 is disposed only inside the opening OP of the interlayer insulating film 43 in the thickness direction. In other words, the Al-Si layer 71 is disposed only in the region surrounded by the upper ends (ends away from the silicon substrate 10) of the side walls around the opening OP of the interlayer insulating film 43 in the in-plane direction, and the thickness is less than or equal to the thickness of the interlayer insulating film 43 at the opening OP. When the Al-Si layer 71 is observed in cross section ( Figure 7 ), it is separated from other adjacent Al-Si layers (not shown in Figure 7 ). Further, in the planar layout (not shown), it is preferable that the edge of the opening OP of the interlayer insulating film 43 has a closed shape, and in this case, the Al-Si layer 71 is separated from other adjacent Al-Si layers. In other words, the Al-Si layer 71 has a plurality of separated portions.

[0054] In addition, in Figure 7 , only the portion above the diode upper surface portion F2b in the second electrode 70 is shown. The structure of the portion above the IGBT upper surface portion F2a (refer to Figure 2 ) in the second electrode 70 is arbitrary. For example, it may be the same structure as that shown in Figure 7 . Regarding the structures other than the above, since they are substantially the same as the structures in Embodiment 2, the same reference numerals are assigned to the same or corresponding elements, and the description thereof will not be repeated.

[0055] Next, a first method for forming the second electrode 70 in this Embodiment 3 will be briefly described. First, in the same manner as in Embodiment 1, a barrier metal layer 20 is formed on the IGBT upper surface portion F2a of the upper surface F2 of the silicon substrate 10. Next, the Al-Si layer 71 is formed by film formation on the entire upper surface F2 by sputtering and patterning of the layer formed by this film formation by photolithography and etching. Next, the Al layer 72 is formed by sputtering. Thus, the second electrode 70 is formed.

[0056] ​Next, a second method for forming the second electrode 70 in the third embodiment will be briefly described. First, similarly to the above-described first method, a barrier metal layer 20 is formed on the IGBT upper surface portion F2a of the upper surface F2 of the silicon substrate 10. Next, a resist film having an opening corresponding to the opening OP of the interlayer insulating film 43 is formed. Next, an Al—Si layer 71 is formed by film formation on the entire upper surface F2 by sputtering and patterning of the layer formed by this film formation by a lift-off method (in other words, patterning achieved by removal of the resist film). Next, an Al layer 72 is formed by sputtering. Thus, the second electrode 70 is formed.

[0057] According to the present embodiment, a part of the Al layer 72 is directly disposed on the interlayer insulating film 43. Thus, the portion of the second electrode 70 directly disposed on the interlayer insulating film 43 does not substantially become a diffusion source of Si atoms. Thus, generation of Si nodules can be further suppressed. The Al—Si layer is disposed only inside the opening OP of the interlayer insulating film 43 in the thickness direction. Thus, generation of Si nodules caused by diffusion of Si atoms from the outside of the opening OP can be avoided.

[0058] <Embodiment 4>

[0059] Figure 8 is a partial cross-sectional view schematically showing the structure of an RC—IGBT 104 (power semiconductor device) in Embodiment 4 through a field of view corresponding to Figure 3 . As differences from the RC—IGBT 101 ( Figure 2 ), the RC—IGBT 104 has a second electrode 70S ( Figure 8 ) and a polysilicon layer 80 instead of the second electrode 70 ( Figure 2 ) and Figure 3 . Regarding the other structures of the RC—IGBT 104, since they are substantially the same as the structures of the first embodiment described above, their description will not be repeated.

[0060] The second electrode 70S is provided on the upper surface F2 of the silicon substrate 10 in the same manner as the second electrode 70 ( Figure 2 ) and is separated from the IGBT upper surface portion F2a of the silicon substrate 10 by the barrier metal layer 20. On the other hand, different from the second electrode 70 ( Figure 2 ), the second electrode 70S includes an Al—Si layer in contact with the diode upper surface portion F2b of the silicon substrate 10. In the structure shown in Figure 8 , the second electrode 70S is an Al—Si layer.

[0061] The polysilicon layer 80 ( Figure 8 ) is away from the upper surface F2 of the silicon substrate 10 (see Figure 2), and is in contact with the second electrode 70S. In Figure 8 In the example shown, the polysilicon layer 80 is disposed above the upper surface of the interlayer insulating film 43 (the surface opposite to the surface facing the silicon substrate 10), and is covered with the Al—Si layer serving as the second electrode 70S.

[0062] The RC-IGBT 104 may have an Si nodule SN formed by precipitation of Si from the Al—Si layer of the second electrode 70S at the interface with the polysilicon layer 80. In order to prevent the opening OP from being blocked by the Si nodule SN formed in the polysilicon layer 80, in the in-plane direction ( Figure 8 the lateral direction), the polysilicon layer 80 may also be disposed so as to be recessed from the opening OP of the interlayer insulating film 43 by an amount of the distance RT. This distance RT can generally be less than or equal to 1 μm.

[0063] In addition, in Figure 8 , only the portion above the upper surface portion F2b of the diode in the second electrode 70S is shown. The structure of the portion of the second electrode 70S located above the IGBT upper surface portion F2a (see Figure 2 ) is arbitrary. For example, it may be the same structure as that shown in Figure 8 .

[0064] Next, an example of a method for forming the polysilicon layer 80 and the second electrode 70S in the fourth embodiment will be briefly described. First, a silicon substrate 10 provided with an interlayer insulating film 43 is prepared. At this time point, doping of the silicon substrate 10 and formation of the trench TR may be completed. The imparting of the pattern shape to the interlayer insulating film 43 may be performed by a lift-off method or by a photolithography method and an etching method. Next, the polysilicon layer 80 is formed by film formation on the entire upper surface F2 and patterning of the layer formed by this film formation based on a photolithography method and an etching method. Next, a barrier metal layer 20 is formed above the IGBT upper surface portion F2a of the upper surface F2 in the same manner as in the first embodiment. Next, an Al—Si layer serving as the second electrode 70S is formed above the upper surface F2 by sputtering. Thus, the polysilicon layer 80 and the second electrode 70S are formed.

[0065] In addition, when it is not necessary to control the distance RT, after film formation of the layer including the portion that becomes the interlayer insulating film 43 and film formation of the layer including the portion that becomes the polysilicon layer 80, these two layers may be patterned together. Thereby, the manufacturing method is simplified.

[0066] In the fourth embodiment, for the same reason as in the first embodiment, the second electrode 70S can function as an IGBT element 201 (see Figure 2 ) above the IGBT upper surface portion F2a of the upper surface F2 of the silicon substrate 10.Figure 1 and Figure 2 ) the ohmic electrode functions, and above the upper surface portion F2b of the diode on the silicon substrate 10, it can function as a Schottky barrier diode element 202 (refer to Figure 1 and Figure 2 ) the Schottky electrode functions. And, similarly to Embodiment 1, the generation of Si nodules at the IGBT upper surface portion F2a of the silicon substrate 10 can be suppressed by the barrier metal layer 20 ( Figure 2 )). Figure 2 )

[0067] Moreover, according to Embodiment 4, a polysilicon layer 80 is provided which is away from the upper surface F2 of the silicon substrate 10 and in contact with the second electrode 70S. Thus, at least a part of the Si atoms diffused from the Al-Si layer 70S causes Si nodules to be generated on the surface of the polysilicon layer 80 rather than on the surface of the silicon substrate 10. Thereby, the generation of Si nodules on the surface of the silicon substrate 10 can be suppressed.

[0068] <Embodiment 5>

[0069] Figure 9 is a partial cross-sectional view schematically showing the structure of the RC-IGBT 105 (power semiconductor device) in Embodiment 5 through a view corresponding to Figure 3 . The RC-IGBT 105 has, on the basis of the structure of the RC-IGBT 101 ( Figure 2 and Figure 3 : Embodiment 1), a polysilicon layer 80. The polysilicon layer 80 is away from the upper surface F2 of the silicon substrate 10 (refer to Figure 2 ). In addition, the polysilicon layer 80 is in contact with the second electrode 70. Specifically, the polysilicon layer 80 is in contact with the Al-Si layer 71 included in the second electrode 70. In the example shown in Figure 9 , the polysilicon layer 80 is disposed above the upper surface of the interlayer insulating film 43 (the surface opposite to the surface facing the silicon substrate 10) and is covered by the Al-Si layer 71.

[0070] In addition, in Figure 9 , only the portion above the upper surface portion F2b of the diode in the second electrode 70 is shown. The structure of the portion of the second electrode 70 above the IGBT upper surface portion F2a is arbitrary. For example, it can be the same as Figure 9The same structure as shown. Additionally, a polysilicon layer may be provided on the upper surface portion F2a of the IGBT, or the polysilicon layer may be omitted. Next, an example of the method for forming the polysilicon layer 80 and the second electrode 70 in the fifth embodiment will be briefly described. First, the process is carried out up to the step of forming the Al-Si layer by the same method as in the aforementioned fourth embodiment. In this embodiment, this layer is the Al-Si layer 71. Next, an Al layer 72 is formed on the upper surface F2 by sputtering. Thus, the second electrode 70 is formed. Further, in the fifth embodiment, different from the fourth embodiment, since the Al layer 72 is formed, the thickness of the Al-Si layer 71 can be smaller than that of the Al-Si layer (i.e., the second electrode 70S) in the fourth embodiment.

[0071] The same effect as in the first embodiment is also obtained by the fifth embodiment. And according to this embodiment, on the basis of the structure in the first embodiment, a polysilicon layer 80 is further provided. Thus, at least a part of the Si atoms diffused from the Al-Si layer 71 causes Si nodules to be generated on the surface of the polysilicon layer 80 rather than on the surface of the silicon substrate 10. Thereby, the generation of Si nodules on the surface of the silicon substrate 10 can be further suppressed.

[0072] In addition, the various embodiments can be freely combined, and the various embodiments can be appropriately deformed and omitted. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It can be understood that countless deformation examples not illustrated can be conceived according to the present invention.

[0073] Description of reference numerals

[0074] 10 silicon substrate, 11 first semiconductor region, 12 second semiconductor region, 13 third semiconductor region, 14 fourth semiconductor region, 20 barrier metal layer, 41 gate insulating film, 42 dummy insulating film, 43 interlayer insulating film, 51 gate electrode, 52 dummy electrode, 60 first electrode, 70 second electrode, 70S second electrode, 71 Al-Si layer, 71C contact portion, 72 Al layer, 80 polysilicon layer, 101 - 105 RC-IGBT (power semiconductor device), 201 IGBT element, 202 Schottky barrier diode element, AS Al spike, F1 lower surface (first surface), F2 upper surface (second surface), OP opening, SN Si nodule, TR trench.

Claims

1. A semiconductor device for electric power, which has a silicon substrate having a first surface and a second surface opposite to the first surface and having a first portion and a second portion, and the silicon substrate includes: A first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type different from the first conductivity type; A third semiconductor region of the first conductivity type, which is separated from the first semiconductor region by the second semiconductor region; And A fourth semiconductor region of the second conductivity type, which is separated from the second semiconductor region by the third semiconductor region, The semiconductor device for electric power further has: A gate insulating film that extends between the first semiconductor region and the third semiconductor region and faces the second semiconductor region; A gate electrode that faces the second semiconductor region with the gate insulating film interposed therebetween; A first electrode that is provided on the first surface of the silicon substrate and is in contact with the third semiconductor region and the fourth semiconductor region; A barrier metal layer that is provided on the first portion of the second surface of the silicon substrate; and A second electrode that is provided on the second surface of the silicon substrate and is separated from the first portion of the second surface of the silicon substrate by the barrier metal layer, The second electrode includes: An Al-Si layer that is in contact with the second portion of the second surface of the silicon substrate; and An Al layer that is separated from the second portion of the second surface of the silicon substrate by the Al-Si layer, The semiconductor device for electric power further has a polysilicon layer that is away from the second surface of the silicon substrate and is in contact with the second electrode.

2. The semiconductor device for electric power according to claim 1, wherein It further has an interlayer insulating film that is disposed on the second portion of the second surface of the silicon substrate and has an opening, and the Al-Si layer has a contact portion that is disposed in the opening of the interlayer insulating film in the in-plane direction and is in direct contact with the second portion of the second surface of the silicon substrate.

3. The semiconductor device for electric power according to claim 2, wherein The Al layer has a portion disposed above the contact portion of the Al-Si layer.

4. A semiconductor device for electric power, which has a silicon substrate having a first surface and a second surface opposite to the first surface and having a first portion and a second portion, and the silicon substrate includes: A first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type different from the first conductivity type; A third semiconductor region of the first conductivity type, which is separated from the first semiconductor region by the second semiconductor region; And A fourth semiconductor region of the second conductivity type, which is separated from the second semiconductor region by the third semiconductor region, The semiconductor device for electric power further has: A gate insulating film that extends between the first semiconductor region and the third semiconductor region and faces the second semiconductor region; A gate electrode that faces the second semiconductor region with the gate insulating film interposed therebetween; A first electrode that is provided on the first surface of the silicon substrate and is in contact with the third semiconductor region and the fourth semiconductor region; A barrier metal layer, which is disposed over the first portion of the second surface of the silicon substrate; and A second electrode, which is disposed over the second surface of the silicon substrate and is spaced apart from the first portion of the second surface of the silicon substrate by the barrier metal layer, The second electrode includes: An Al-Si layer, which is in contact with the second portion of the second surface of the silicon substrate; and An Al layer, which is spaced apart from the second portion of the second surface of the silicon substrate by the Al-Si layer, The power semiconductor device further has an interlayer insulating film, which is disposed over the second portion of the second surface of the silicon substrate and has an opening. The Al-Si layer has a contact portion, which is disposed within the opening of the interlayer insulating film in the in-plane direction and is in direct contact with the second portion of the second surface of the silicon substrate, At least a portion of the Al layer is directly disposed over the interlayer insulating film.

5. The power semiconductor device according to claim 4, wherein, The Al layer has a portion disposed over the contact portion of the Al-Si layer.

6. A power semiconductor device, which has a silicon substrate having a first surface and a second surface opposite to the first surface and having a first portion and a second portion. The silicon substrate includes: A first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type different from the first conductivity type; A third semiconductor region of the first conductivity type, which is separated from the first semiconductor region by the second semiconductor region; And A fourth semiconductor region of the second conductivity type, which is spaced apart from the second semiconductor region by the third semiconductor region, The power semiconductor device further has: A gate insulating film, which extends between the first semiconductor region and the third semiconductor region and faces the second semiconductor region; A gate electrode, which faces the second semiconductor region with the gate insulating film interposed therebetween; A first electrode, which is disposed over the first surface of the silicon substrate and is in contact with the third semiconductor region and the fourth semiconductor region; A barrier metal layer, which is disposed over the first portion of the second surface of the silicon substrate; and A second electrode, which is disposed over the second surface of the silicon substrate and is spaced apart from the first portion of the second surface of the silicon substrate by the barrier metal layer, The second electrode includes: An Al-Si layer, which is in contact with the second portion of the second surface of the silicon substrate; and An Al layer, which is spaced apart from the second portion of the second surface of the silicon substrate by the Al-Si layer, The power semiconductor device further has an interlayer insulating film, which is disposed over the second portion of the second surface of the silicon substrate and has an opening. The Al-Si layer has a contact portion, which is disposed within the opening of the interlayer insulating film in the in-plane direction and is in direct contact with the second portion of the second surface of the silicon substrate, The Al layer has a portion disposed over the contact portion of the Al-Si layer, The Al—Si layer is disposed only inside the opening of the interlayer insulating film in the thickness direction.

7. The semiconductor device for power use according to any one of claims 3 to 6, wherein it further has a polysilicon layer which is away from the second surface of the silicon substrate and contacts the second electrode.

8. The semiconductor device for power use according to any one of claims 2 to 6, wherein grooves covered by the interlayer insulating film in a cross-sectional view are provided at the first portion and the second portion of the second surface of the silicon substrate, respectively.

9. The semiconductor device for power use according to any one of claims 1 to 6, wherein the second electrode has a stacked structure of the Al—Si layer and the Al layer at least over the second portion of the second surface of the silicon substrate.

10. A semiconductor device for power use, which has a silicon substrate having a first surface and a second surface opposite to the first surface and having a first portion and a second portion, the silicon substrate including: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type different from the first conductivity type; A third semiconductor region of the first conductivity type, which is separated from the first semiconductor region by the second semiconductor region; and a fourth semiconductor region of the second conductivity type, which is separated from the second semiconductor region by the third semiconductor region, the semiconductor device for power use further having: a gate insulating film extending between the first semiconductor region and the third semiconductor region and facing the second semiconductor region; a gate electrode facing the second semiconductor region with the gate insulating film therebetween; a first electrode provided over the first surface of the silicon substrate and contacting the third semiconductor region and the fourth semiconductor region; a barrier metal layer provided over the first portion of the second surface of the silicon substrate; and a second electrode provided over the second surface of the silicon substrate and separated from the first portion of the second surface of the silicon substrate by the barrier metal layer, the second electrode including an Al—Si layer contacting the second portion of the second surface of the silicon substrate, the semiconductor device for power use further having a polysilicon layer which is away from the second surface of the silicon substrate and contacts the second electrode.

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