A transmission electron microscope in-situ thermal parameter test chip and a preparation method thereof

Abstract

The application discloses a kind of transmission electron microscope in-situ thermal parameter test chip and preparation method thereof, chip is MEMS device, and two overhanging platforms of left-right symmetry are formed on silicon substrate;Overhanging platform structure includes bottom layer electric heat insulation protective layer, resistance, metal electrode, metal thermal mirror are sequentially and spaced apart on bottom layer electric heat insulation protective layer, and metal thermal mirror is located in the opposite inner side of two overhanging platforms, and resistance is covered with top layer electric heat insulation protective layer.Electric heat insulation protective layer is arranged in the upper and lower layers of resistance structure, so as to be isolated from the outside, to reduce the influence of outside environment on electrical signal when testing one side temperature measuring resistance and the probability of contact or damage in sample transfer;Meanwhile, by designing metal thermal mirror, the influence of heat radiation between two overhanging platforms during thermal conductivity test is reduced.

Description

Technical Field

[0001] This invention relates to a transmission electron microscope (TEM) in-situ thermal parameter testing chip and its fabrication method. Background Technology

[0002] With the increasing integration and density of electronic devices, heat dissipation performance has a significant impact on their performance and operational stability. Poor heat dissipation can lead to overheating during operation, potentially causing performance degradation or even burnout. Therefore, studying the thermal properties of device materials is of great importance for optimizing heat dissipation performance.

[0003] With the rise of low-dimensional materials, they have shown enormous potential applications in electronic devices. When the scale of materials shrinks to the micro- and nano-scale, their material properties differ significantly from those of macroscopic bulk materials. The thermal conductivity of macroscopic bulk materials can be described by Fourier's law; given a fixed temperature and composition, the thermal conductivity, like electrical conductivity, is a constant, independent of the material's shape and size. This is mainly because the geometric dimensions of bulk materials are much larger than the mean free path of phonons, resulting in diffusion transport. In low-dimensional materials, due to quantum confinement effects, the quantum states of phonons change significantly compared to three-dimensional bulk materials. The geometric dimensions of these materials can approach or even be smaller than the mean free path of phonons, causing phonon transport to shift from diffusion to (quasi-)ballistic transport. Simultaneously, the scattering effect of phonons by the material's surface or boundaries becomes increasingly pronounced, and the thermal conductivity changes with the material's geometric dimensions, exhibiting a strong size effect. Therefore, the thermal conductivity of low-dimensional materials cannot be calculated using the values ​​for bulk materials and must be recalculated and measured. However, current research on the properties of low-dimensional materials mainly focuses on electrical, optical, and mechanical properties, with very little research on thermal properties, especially research on in-situ thermal parameter measurement suitable for transmission electron microscopy.

[0004] Currently, the classic method for in-situ thermal parameter measurement of low-dimensional materials is the suspended thermal bridge method based on MEMS test chips. In 2001, Li et al. at the University of California, Berkeley, first used this method to measure the thermal conductivity of multi-walled carbon nanotubes in a scanning electron microscope. However, its limitations are that the resistance strip in the suspended thermal bridge structure is exposed to the environment, making the electrical signal susceptible to changes in the external environment during the test, thus affecting the accuracy of the measurement; at the same time, the resistance strip may come into contact with or be damaged during the transfer of the sample, affecting the temperature coefficient of resistance of the resistance strip; in addition, when measuring samples with low thermal conductivity, the thermal radiation at one end of the heater will cause the temperature at the other end of the sensor to rise, which limits the accuracy of the thermal properties and parameter measurement of the sample. Summary of the Invention

[0005] Purpose of the invention: To address the aforementioned existing technologies, this invention proposes a transmission electron microscope (TEM) in-situ thermal parameter testing chip and its fabrication method, thereby solving the problem of low accuracy in in-situ thermal parameter measurement of low-dimensional materials.

[0006] Technical Solution: A transmission electron microscope (TEM) in-situ thermal parameter testing chip, the chip being a MEMS device, comprising a silicon substrate, on which two symmetrical suspended platforms are formed; the suspended platform structure includes a bottom electrothermal insulating protective layer, on which a resistor, a metal electrode, and a metal thermal reflector are sequentially and spaced apart, with the metal thermal reflector located on the opposite inner sides of the two suspended platforms; the resistor is covered by a top electrothermal insulating protective layer; the resistor and the metal electrode are respectively connected to external electrodes through electrical signal paths; the metal electrodes of the two suspended platforms are used to jointly load the sample to be tested.

[0007] Furthermore, the metal thermal reflector also covers the opposite inner edges of the underlying electrothermal insulating protective layer.

[0008] Furthermore, the electrical signal paths are respectively set on the corresponding cantilever arms, which are made of silicon nitride and used to support the suspended platform.

[0009] Furthermore, the metal thermal reflector is made of Pt.

[0010] The method for fabricating the in-situ thermal parameter testing chip for transmission electron microscopy includes the following steps:

[0011] Step 1: Prepare silicon nitride thin film layers on both sides of a silicon substrate using chemical vapor deposition;

[0012] Step 2: A Pt patterned layer is prepared on the upper silicon nitride thin film layer using a lift-off process to form two symmetrical resistors;

[0013] Step 3: A silicon nitride thin film is prepared on the Pt pattern layer using a peeling process as the top electrothermal insulating protective layer of the resistor;

[0014] Step 4: Etch the upper silicon nitride thin film layer, retaining only the silicon nitride in the suspended platform and cantilever areas;

[0015] Step 5: On the upper silicon nitride thin film layer and inside the resistor, a Pt pattern layer is prepared by chemical vapor deposition to form a metal electrode, a metal thermal reflector, and an electrical signal path connecting the resistor and the metal electrode.

[0016] Step 6: Etch the lower silicon nitride thin film layer of the silicon substrate to form a mask window;

[0017] Step 7: The silicon substrate is etched on the back to form a hollow structure, releasing the suspended platform and finally completing the fabrication of the chip structure.

[0018] Beneficial effects: The advantage of in-situ transmission electron microscopy (TEM) parameter testing is that it can observe the fine structural relationships of atoms, making it particularly suitable for studying the influence of defects, doping, etc., on the thermal properties of materials. Therefore, this testing method needs to have higher measurement accuracy to detect the influence of defects, doping, etc., on thermal parameters. How to improve the measurement accuracy of in-situ thermal parameters of low-dimensional materials is one of the current hot topics and challenges in cutting-edge research fields.

[0019] This invention provides a transmission electron microscope (TEM) in-situ thermal parameter testing chip. Electrothermal insulation layers are provided on both the upper and lower layers of the two serpentine resistor structures on the suspended platform, isolating them from the external environment. This reduces the influence of the external environment on the electrical signal of the temperature-sensing resistor on one side during testing, as well as the probability of contact or damage during sample transfer. Simultaneously, a metal thermal reflector is designed to reduce the influence of thermal radiation between the two suspended platforms during thermal conductivity testing. This structural design solves the problems of the temperature-sensing resistor being affected by the external environment on the electrical signal and the probability of contact or damage during sample transfer, while not affecting the electrical signal output of the metal electrodes, thus facilitating high-precision in-situ thermal parameter measurement. The metal reflector structure reduces the influence of thermal radiation between the suspended platforms, improving the accuracy of the measurement.

[0020] The difficulty in fabricating the chip of this invention lies in the practical challenges of micro / nano fabrication of the upper and lower double-layer electrothermal insulating protective layers. Specifically, to ensure a near-perfect match in thermal expansion coefficients, the double-layer electrothermal insulating protective layers must be made of the same material during chip structure design. However, since the two layers are not exactly identical (the area of ​​the lower electrothermal insulating protective layer is larger than that of the upper layer), two different patterned masks must be used for two separate etching processes during micro / nano fabrication. Patterning different layers of the same material, whether using wet or dry etching, results in the etchant simultaneously corroding both layers. Protecting the pattern of the other layer while patterning one layer is a key challenge in micro / nano fabrication. During the fabrication process, the two layers must be completely separated by other layer materials (or mask materials). However, in the structure of the thermal test chip, the lower electrothermal insulating protective layer is the substrate of the metal structure layer, and the upper electrothermal insulating protective layer is a protective layer that isolates the resistive structure from the outside. The pattern of the metal structure must be included in the pattern structure of the upper and lower electrothermal insulating protective layers. That is, some areas of the upper and lower electrothermal insulating protective layers are in direct contact, so the fabrication of this structure is very difficult.

[0021] The thin film preparation of the electrothermal insulating protective layer above the metal structure layer is carried out by directly preparing a patterned silicon nitride protective layer through a peeling process. By using this method, the electrothermal insulating protective layer can be placed only on the metal serpentine resistor, which can avoid the metal electrode being covered by the electrothermal insulating protective layer, and at the same time avoid the use of etching process to avoid the bottom silicon nitride being accidentally etched. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall structure of the test chip of this invention;

[0023] Figure 2 This is a schematic diagram of the suspended platform in the test chip of this invention;

[0024] Figures 3 to 9 These are cross-sectional views corresponding to each step of the fabrication method of the test chip in this invention;

[0025] Figure 10 These are simulation results of a suspended platform with a metal thermal reflector structure;

[0026] Figure 11 The simulation results are for a suspended platform without a metal thermal reflector structure.

[0027] Figure 12 This is a schematic diagram of the heat flow direction for thermal conductivity measurement using the chip of this invention. Detailed Implementation

[0028] The invention will now be further explained with reference to the accompanying drawings.

[0029] like Figure 1 , Figure 2 As shown, a transmission electron microscope (TEM) in-situ thermal parameter testing chip is a MEMS device. It includes a silicon substrate 101 with a hollow structure 102 in the center. A first suspended platform structure 103 and a second suspended platform structure 106, symmetrically arranged on the hollow structure 102, are also described. Both the first and second suspended platform structures 103 and 106 include a bottom electrothermal insulating protective layer. The first suspended platform structure 103 has a first resistor 104, a first metal electrode 105, and a first metal thermal reflector 109 sequentially and spaced apart on its bottom electrothermal insulating protective layer. The second suspended platform structure 106 has a second resistor 107, a second metal electrode 108, and a second metal thermal reflector 110 sequentially and spaced apart on its bottom electrothermal insulating protective layer. The first and second metal thermal reflectors 109 and 110 are located on opposite inner sides of the two suspended platforms. On two suspended platforms, a top-layer electrothermal insulating protective layer 111 covers the resistors. The resistors and metal electrodes are connected to external electrodes via electrical signal paths, which are respectively set on corresponding cantilever arms made of silicon nitride. Each suspended platform structure is effectively supported by six cantilever arms, one below each electrical signal path and the other connecting to the first metal thermal reflector 106 and the second metal thermal reflector 110. The first metal electrode 105 and the second metal electrode 108 on the left and right suspended platforms are used to jointly load the sample to be tested, with both ends of the sample directly contacting the metal electrodes.

[0030] The resistors are encased in an electrothermal insulation protective layer to prevent them from directly contacting the outside environment. The electrothermal insulation protective layer is made of silicon nitride material, which has the characteristics of low thermal conductivity and electrical insulation.

[0031] In this invention, one side of the resistor is used for both heating and temperature measurement, while the other side is used only for temperature measurement. The metallic thermal reflector also covers the opposing inner edges of the underlying electrothermal insulating protective layer. A layer of metallic thermal reflector is fabricated on the adjacent inner sides of the two suspended platforms to reduce the thermal radiation impact on the other side, which is used solely for temperature measurement, during detection. The metallic thermal reflector is made of Pt or other materials with low absorptivity.

[0032] The above-mentioned transmission electron microscopy in-situ thermal parameter testing chip was fabricated using micro-nano fabrication technology, and the fabrication method includes the following steps:

[0033] Step 1: Prepare silicon nitride thin films with a thickness of 500 nm on both sides of the silicon substrate 101 using chemical vapor deposition, such as... Figure 3 As shown, the upper silicon nitride thin film layer 2 serves as the substrate for the electrothermal insulating protective layer and the metal layer, while the lower silicon nitride thin film 3 serves as a mask layer for etching the silicon substrate.

[0034] Step 2: A Pt patterned layer 4 is fabricated on the upper silicon nitride thin film layer 2 using a lift-off process to form two symmetrical resistors, such as... Figure 4 As shown.

[0035] Step 3: A silicon nitride thin film 5 is prepared on top of the Pt patterned layer 4 using a lift-off process, serving as the top electrothermal insulating protective layer of the resistor, such as... Figure 5 As shown.

[0036] Step 4: Etch the upper silicon nitride thin film layer 2, retaining only the silicon nitride in the suspended platform and cantilever areas;

[0037] Step 5: On the upper silicon nitride thin film layer 2, located inside the resistor, a Pt patterned layer 6 is prepared by chemical vapor deposition to form a metal electrode, a metal thermal reflector, and an electrical signal path connecting the resistor and the metal electrode, as shown below. Figure 7 As shown.

[0038] Step 6: Etch the lower silicon nitride thin film layer 3 of the silicon substrate 101 to form a mask window, such as... Figure 8 As shown.

[0039] Step 7: Etch the silicon substrate 101 on the back side to form a hollow structure, releasing the suspended platform, such as... Figure 9 As shown, the chip structure was finally fabricated.

[0040] The initial temperature of the left suspended platform is set to 300.15K, and the initial temperature of the right suspended platform is set to 293.15K. Figure 10The simulation results of the metal thermal reflector structure show that the overall average temperature of the right-side suspended platform is 293.150 K. Figure 11 The simulation results, without the metal heat reflector structure, show that the overall average temperature of the right-side suspended platform is 293.171 K. Figure 10 , Figure 11 The COMSOL simulation results show that the effect of thermal radiation can be reduced by using a metal thermal reflector structure.

[0041] Figure 12 This is a schematic diagram illustrating the heat flow direction for thermal conductivity measurement using the chip of this invention. The entire suspended device is placed in a vacuum system. After the sample is placed on the device, a direct current is used to heat the first suspended platform through the first resistor 104, generating Joule heat of Qh. The direct current also heats the two cantilever arms connected to the first resistor, generating a total Joule heat of 2Ql. Half of this heat remains on the first suspended platform, and the other half flows to the silicon nitride substrate of the cantilever arms and the environment. Therefore, the total Joule heat on the first suspended platform can be approximated as Qh + Ql. Assuming the heat transferred from the first suspended platform to the environment is Q1, and the heat transferred from the second suspended platform to the environment is Q2, then the total heat Q = Q1 + Q2 = Qh + Ql.

[0042] The heat transferred from the sample from the first suspended platform to the second suspended platform is the same as the heat transferred from the second suspended platform to the environment through the cantilever. Let the thermal conductivity of the sample be Gs, the thermal conductivity of the cantilever be Gb, the temperature of the first suspended platform be Th, the temperature of the second suspended platform be Ts, and the temperature of the environment be T0. Then:

[0043] Q1 = Gb × (Th – T0)

[0044] Q2=Gs×(Th–Ts)=Gb×(Ts–T0)

[0045] Therefore, we can conclude that:

[0046] Gs = Gb × (Ts – T0) / (Th – Ts)

[0047] and:

[0048] Q=Qh+Qs=Q1+Q2=Gb×(Th–T0)+Gb×(Ts–T0)

[0049] The thermal conductivity Gs of the sample can be calculated using the above formula, and then the thermal conductivity k can be calculated using the formula for thermal conductivity k.

[0050]

[0051] Where L is the length of the sample, w is the width of the sample, and t is the thickness of the sample. The temperature Th of the first suspended platform can be obtained by measuring the resistance change of the first resistor, and the temperature Ts of the second suspended platform can be obtained by measuring the resistance change of the second resistor.

[0052] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A transmission electron microscope in-situ thermal parameter testing chip, characterized in that, The chip is a MEMS device, comprising a silicon substrate, and two symmetrical suspended platforms formed on the silicon substrate; the suspended platform structure comprises a bottom layer of electrically heat-insulating protective layer, an electric resistor, a metal electrode and a metal heat mirror sequentially and spaced apart on the bottom layer of electrically heat-insulating protective layer, and the metal heat mirror is located at the opposite inner side of the two suspended platforms, and the electric resistor is covered with a top layer of electrically heat-insulating protective layer; the electric resistor and the metal electrode are connected with external electrodes through electric signal channels; and the metal electrodes of the left and right two suspended platforms are used for jointly loading a sample to be measured.

2. The in-situ thermal parameter testing chip for transmission electron microscope according to claim 1, wherein, The metal heat mirror also covers the opposite inner side edges of the bottom layer of electrically heat-insulating protective layer.

3. The in-situ thermal parameter testing chip for transmission electron microscope according to claim 1, wherein, The electric signal channels are respectively arranged on corresponding suspension arms made of silicon nitride and used for supporting the suspended platforms.

4. The in-situ thermal parameter testing chip for transmission electron microscope of claim 1, wherein, The metal heat mirror is made of Pt.

5. The method of claim 1-4, wherein the method further comprises: The method comprises the following steps: Step 1: preparing a silicon nitride film layer on both sides of the silicon substrate by chemical vapor deposition; Step 2: preparing a Pt pattern layer on the upper silicon nitride film layer by a stripping process to form two symmetrical electric resistors; Step 3: preparing a layer of silicon nitride film on the Pt pattern layer as a top layer of electrically heat-insulating protective layer of the electric resistor by a stripping process; Step 4: etching the upper silicon nitride film layer to only keep the silicon nitride in the suspended platform and suspension arm regions; Step 5: preparing a Pt pattern layer on the upper silicon nitride film layer and at the inner side of the electric resistor by chemical vapor deposition to respectively form a metal electrode, a metal heat mirror and an electric signal channel connecting the electric resistor and the metal electrode; Step 6: etching the lower silicon nitride film layer of the silicon substrate to form a mask window; Step 7: etching the silicon substrate from the back to form a hollow structure to release the suspended platform, and finally complete the preparation of the chip structure.

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