Electronic equipment fault detection method and detection system based on discrete sequence and asymmetric distance

Abstract

The present invention discloses a method for detecting electronic device faults based on discrete sequences and asymmetric distances, comprising the following steps: S1, selecting a fault-free circuit model as an application object; S2, applying an excitation signal generated by a test signal generation module to two different nodes on the application object through a detection module to obtain circuit response signals of the two different nodes; S3, establishing a discrete-time signal model A and a discrete-time signal model B; S4, obtaining a path K′ with a minimum distance based on a point-to-point matching method in the signal model A and the signal model B; S5, obtaining a series of distances D based on the obtained path K′. ij , select the largest distance as the fault detection threshold D f To be detected circuit model step S2-S4, the distance D ij The threshold D obtained in step S5 f Compare, if D>D f , the circuit is considered to be in a fault state, otherwise, the circuit is normal.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic equipment fault detection, and in particular relates to a method and a detection system for electronic equipment fault detection based on discrete sequences and asymmetric distances. Background Art

[0002] With the development and advancement of science and technology, electronic equipment has been widely used in various fields, such as aerospace and the military. Electronic equipment is an essential component of military equipment. Due to its integrated design and portability, it plays a vital role in daily training and combat exercises. It plays an irreplaceable role in modern warfare.

[0003] Circuit boards are key components of various electronic devices. However, failures are inevitable, whether in components, circuits, or systems, due to factors such as process technology, usage, and operating environment. Furthermore, with the increasing integration of circuits, the impact of equipment failures or accidents on various industries has significantly increased. This is particularly true in critical fields such as the military, where a circuit board failure can cause irreparable military losses and even jeopardize military advantage. Therefore, to ensure the proper operation of equipment, proactive fault detection is essential.

[0004] However, the traditional detection method that relies solely on manual and instrumentation is becoming increasingly inadequate and inefficient. Furthermore, the manufacturer and user of a circuit board are usually different people. Therefore, when users are unfamiliar with the circuit structure and lack basic technical information, it is very difficult to use instruments such as multimeters to determine whether a circuit board is faulty. The main shortcomings of traditional detection methods are as follows:

[0005] (1) The detection method is simple and inefficient

[0006] Inspectors usually use a multimeter to manually adjust and repeatedly measure the voltage or current of each node to see if it is normal. They detect circuit board faults through manual measurement, visual observation, and repeated comparison. This method is labor-intensive, time-consuming, and inefficient.

[0007] (2) Fault detection results rely on prior knowledge

[0008] Previous testing methods primarily focused on circuits with clear structural principles. This meant that the component parameters, circuit structure, and operating status were all known. Therefore, prior testing required extensive knowledge, such as component parameters and their normal ranges. Test results were largely dependent on the tester's circuit maintenance experience. Consequently, traditional methods were ineffective for testing circuits with unknown structures.

[0009] (3) Fault detection relies on personal subjectivity

[0010] In the past, actual fault detection often relied on visually identifying and comparing signal differences. No specific method was used in the signal analysis process, resulting in a high degree of personal subjectivity in the resulting fault determination. Therefore, fault detection capabilities were largely dependent on the technician's skill level and extensive testing experience.

[0011] Therefore, it is very necessary to study the means and methods of circuit board fault detection under new technological conditions, improve the speed of equipment maintenance, reduce the equipment support cost, and improve the combat capability of the troops, and to conduct timely detection and maintenance of circuit boards. Summary of the Invention

[0012] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide an electronic equipment fault detection method and a detection system based on discrete sequence and asymmetric distance.

[0013] A first object of the present invention is to provide a method for detecting electronic device faults based on discrete sequences and asymmetric distances, comprising the following steps:

[0014] S1. Select a fault-free circuit model as the application object;

[0015] S2. The excitation signal generated by the test signal generation module is applied to two different nodes on the application object in step S1 through the detection module to obtain circuit response signals of the two different nodes;

[0016] S3, using a response signal feature extraction module to collect a number of response instantaneous values at equal time intervals from the response signals of the two different node circuits obtained in step S2 to form a signal feature curve, that is, to obtain a discrete-time signal model A and a discrete-time signal model B;

[0017] S4, construct a continuous path K=k1, k2...k according to the point-to-point matching method in the signal model A and the signal model B obtained in step S3 m , where line segment k i The two ends correspond to the data points in X and Y respectively, and define a mapping function f i :(x,y)→K, map the relationship between point pairs to path K, and then find the path K' with the minimum distance;

[0018] S5. Calculate a series of distances D based on the path K' obtained in step S4 ij , select the largest distance as the fault detection threshold D f , that is, D f =max{D ij};

[0019] S6, applying the same excitation signal as in step S2 to the circuit model to be tested through the detection module to obtain a circuit response signal;

[0020] S7, collecting a number of response instantaneous values at equal time intervals in the circuit response signal obtained in step S6 to form a signal feature vector, that is, obtaining a discrete-time signal model C;

[0021] S8, construct a continuous path N=n1, n2...n according to the point-to-point matching method in the signal model C obtained in step S7 and the signal model A obtained in step S3 m , where line segment n i The two ends correspond to the data points in X and Y respectively, and define a mapping function f i :(x,y)→N, map the relationship between point pairs to the path N, and then find the path N' with the minimum distance;

[0022] S9, according to the path N' obtained in step S8, a series of distances D are obtained, and the distance D is compared with the threshold D obtained in step S5. f Compare, if D>D f , the circuit is considered to be in a fault state, otherwise, the circuit is normal.

[0023] Preferably, in step S4, the data points in the path K are matched according to the following two constraints:

[0024] (1) Endpoint alignment: the first point a1 of sequence A is aligned with the first point b1 of sequence B, and the last point a m and b m Alignment, that is:

[0025]

[0026] (2) Monotonicity: the path moves monotonically along the time axis, that is:

[0027]

[0028] A second object of the present invention is to provide an electronic equipment fault detection system, comprising:

[0029] A test signal generation module is used to generate test excitation signal data according to external input signal parameters and send it to the detection module;

[0030] A response signal feature extraction module is used to collect the circuit response signal of the circuit under test output by the analog-to-digital converter, and extract features from a number of response instantaneous values at equal time intervals in the obtained circuit response signal to obtain a characteristic curve, and send it to the display module and the characteristic curve similarity comparison module;

[0031] The characteristic curve similarity comparison module is used to compare the unknown board curve obtained by the response signal characteristic extraction module with the normal board curve to determine whether the board to be tested is within the tolerance range;

[0032] The detection module is used to obtain the excitation signal generated by the test signal generation module, apply the obtained excitation signal to the circuit under test, and convert it into a circuit response signal of the circuit under test and then output it;

[0033] An analog-to-digital converter, used to perform analog-to-digital conversion on the circuit response signal acquired by the detection module and then send the result to the response signal feature extraction module;

[0034] The adapter is used to match the source resistance and the impedance of the device under test, balance the voltage distribution, and make the signal curve obtained by the response signal feature extraction module convenient for subsequent comparison.

[0035] The display module is used to display the characteristic curve obtained by the response signal feature extraction module.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention establishes a signal model based on discrete time through the sampling theorem, facilitating comparison, calculation, and storage. It then selects Euclidean distance as the similarity distance metric and proposes an improved asymmetric distance detection method. The detection method provided by the present invention can complete detection without obtaining the parameters of circuit device components, reducing the difficulty of detection. The calculation conditions are no longer overly stringent, and the calculation does not require that the points in the discrete sequence must correspond one-to-one in time, thus reducing the detection conditions. Furthermore, the algorithm has a low level of complexity and is relatively simple and easy to understand, making it more convenient to apply to detection systems. The length of the detection sequence does not need to remain the same, thus expanding the detection range and increasing the accuracy of the algorithm calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a normal circuit model diagram;

[0039] Figure 2 For improved distance performance diagram;

[0040] Figure 3 This is a framework diagram of the electronic equipment fault detection system provided by the present invention;

[0041] Figure 4 Generate a flow chart for the signal;

[0042] Figure 5 This is the voltage and current acquisition circuit diagram;

[0043] Figure 6 This is the source resistance control circuit diagram. DETAILED DESCRIPTION

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth above. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] An embodiment of the present invention provides a method for detecting electronic device faults based on discrete sequences and asymmetric distances, which specifically includes the following steps:

[0046] S1. Select a fault-free circuit model, such as Figure 1 As shown, as the application object, where T is the test node;

[0047] S2. The excitation signal generated by the test signal generation module is applied to two different nodes on the application object in step S1 through the detection module to obtain circuit response signals of the two different nodes;

[0048] S3, using the response signal feature extraction module to collect a number of response instantaneous values of equal time intervals in the response signals of the two different node circuits obtained in step S2 to form a signal feature curve, that is, to obtain discrete time signal model A and discrete time signal model B. a1, a2, b1, and b2 are discrete points on the signal sequence, and the Euclidean distance must meet the following conditions, that is, a1b1=a2 b2=a i b j And the sequence points must correspond one to one, which is a symmetric distance algorithm. The improved asymmetric distance algorithm only needs to ensure that the first data point and the last data point between the two sequences are aligned and matched, and supports similarity calculations for sequences of different lengths, which meets the asymmetric requirements. Figure 2 As shown;

[0049] As long as a1 and b1 are aligned, the last point a m 、b m If the discrete time interval is smaller, the distance between a2b1 and a2b3 will be smaller, and the accuracy of the algorithm will be higher.

[0050] S4, construct a continuous path K=k1, k2...k according to the point-to-point matching method in the signal model A and the signal model B obtained in step S3 m , where line segment k i The two ends correspond to the data points in X and Y respectively, and define a mapping function f i :(x,y)→K, map the relationship between point pairs to path K, and then find the path K' with the minimum distance, that is

[0051] The data points in the path K are matched according to the following two constraints:

[0052] (1) Endpoint alignment: the first point a1 of sequence A is aligned with the first point b1 of sequence B, and the last point a m and b m Alignment, that is:

[0053]

[0054] (2) Monotonicity: the path moves monotonically along the time axis, that is:

[0055]

[0056] S5. Calculate a series of distances D based on the path K' obtained in step S4 ij , select the largest distance as the fault detection threshold D f , that is, D f =max{D ij};

[0057] S6, applying the same excitation signal as in step S2 to the circuit model to be tested through the detection module to obtain a circuit response signal;

[0058] S7, collecting a number of response instantaneous values at equal time intervals in the circuit response signal obtained in step S6 to form a signal feature vector, that is, obtaining a discrete-time signal model C;

[0059] S8, construct a continuous path N=n1, n2...n according to the point-to-point matching method in the signal model C obtained in step S7 and the signal model A obtained in step S3 m , where line segment n i The two ends correspond to the data points in X and Y respectively, and define a mapping function f i :(x,y)→N, map the relationship between point pairs to the path N, and then find the path N' with the minimum distance;

[0060] S9, according to the path N' obtained in step S8, a series of distances D are obtained, and the distance D is compared with the threshold D obtained in step S5. f Compare, if D>D f , the circuit is considered to be in a fault state, otherwise, the circuit is normal.

[0061] like Figure 3 As shown, an embodiment of the present invention further provides an electronic equipment fault detection system, specifically comprising:

[0062] A test signal generation module is used to generate test excitation signal data according to external input signal parameters and send it to the detection module;

[0063] The test signal generation module controls test signal generation in the hardware, generating test stimulus signal data based on externally input signal parameters. The test signal generation module is responsible for generating test stimulus signals. The automatic sensitivity adjustment option utilizes the test signal generation techniques described in Chapter 2, specifically test stimulus for circuit fault sensitivity models. Key test waveforms, such as sine and square waves, determine the signal generation function. Parameters such as the voltage amplitude and frequency of the stimulus signal can be set by the user, automatically adjusting and optimizing the set stimulus parameters to improve test efficiency.

[0064] a response signal feature extraction module, configured to collect the circuit response signal of the circuit under test output by the analog-to-digital converter, perform feature extraction on a number of response instantaneous values at equal time intervals in the obtained circuit response signal, obtain a characteristic curve, and send the result to the display module and the characteristic curve similarity comparison module;

[0065] The response signal feature extraction module is primarily responsible for collecting response signals. It extracts the response signal characteristic curve of the circuit under test and displays it on the screen using a display device. Actual circuit board fault detection often extracts the voltage response signals of key nodes on the board as the basis for fault determination. As mentioned in the previous section, at the hardware level, the data acquisition port is responsible for signal acquisition, while at the software level, response signal data is acquired through the acquisition channel. Therefore, the response signal feature extraction module first establishes the data acquisition channel and then configures the channel, primarily including the sampling trigger mode (rising edge trigger or falling edge trigger), sampling mode (continuous sampling or limited sampling), and the number of sampling times. The resulting signal data is stored as response signal characteristics by the upper-level software and output as a curve to the display control.

[0066] The characteristic curve similarity comparison module is used to compare the unknown board curve obtained by the response signal characteristic extraction module with the normal board curve to determine whether the board under test is within the tolerance range; if so, the board under test is normal, otherwise, there is a fault.

[0067] The detection module is used to obtain the excitation signal generated by the test signal generation module, apply the obtained excitation signal to the circuit under test, and convert it into a circuit response signal of the circuit under test and then output it;

[0068] An analog-to-digital converter, used to perform analog-to-digital conversion on the circuit response signal acquired by the detection module and then send the result to the response signal feature extraction module;

[0069] The adapter is used to match the source resistance and the impedance of the device under test, balance the voltage distribution, and make the signal curve obtained by the response signal feature extraction module convenient for subsequent comparison.

[0070] The display module is used to display the characteristic curve obtained by the response signal feature extraction module.

[0071] External test signals can reveal the impedance characteristics of circuit nodes and indicate whether the circuit is functioning properly. Different test signals will also alter the corresponding response signal. Since square waves and sawtooth waves contain many harmonic components, they can cause self-excitation during testing, resulting in an unstable response signal curve. Therefore, the platform uses a sine wave as its test signal.

[0072] The test signal mainly affects the quality of the test from three variables: frequency, phase and voltage amplitude. The wider the voltage range and frequency range, the better the test quality. The specific implementation process is as follows: Figure 4 As shown, first the upper-layer software generates a set of voltage data, and then sends the data to the signal buffer. These digital signals are sent out under the control of the output clock and converted into discrete test signals by the DAC.

[0073] The quality of signal data acquisition is a key aspect of hardware design, as the voltage response signal acquired is the basis for forming the signal characteristic curve. In order to prevent the voltage at the measured point from being too high, which may damage the data acquisition device or sensor, a voltage follower can be added between the acquisition device and the measured point. This is because the output voltage of the follower is the same as the input voltage, and it has buffering and isolation functions and good load capacity, which can play a certain protective role. Figure 5 As shown, the voltage at the measured point A is connected to the AI8 port of the data acquisition card through the voltage follower LM324.

[0074] Most existing testers use special circuits to measure current, which is very expensive. The embodiment of the present invention converts the current collection into voltage collection, collects the voltage across the standard resistor, and then converts it into current, thereby reducing the corresponding hardware cost. Figure 5 As shown in the figure, the tester is internally designed with a high-precision reference resistor Rr. The voltage difference between its two ends is amplified by the instrument amplifier AD620AN and sent to the data acquisition card AI1 port for acquisition. The circuit current is then converted by the upper-level software.

[0075] To adapt the platform hardware to different test objects, adaptive development is required. Before developing the adapter, the design of the adapter must be determined. This invention addresses this adaptation issue by adding a control circuit to the circuit. The USB-6211 data acquisition interface meets the voltage requirements of various integrated circuits, ensuring a wide test voltage and frequency band and stable signal output. The source resistance can be used to match the impedance of the device under test, balancing voltage distribution and facilitating subsequent comparison of the acquired signal curve, thus enhancing the system's testing capabilities.

[0076] For nonlinear devices, if the source resistance is too large, the response voltage and current signals will be too small, which will increase the test error. If the source resistance is too small, the phase difference between the response voltage and current signals will be smaller, which will not fully describe the impedance characteristics of the device under test. The system uses four types of resistors (10, 100, 1k and 10k) as source resistance components. Three relay switches control the connection of the three resistors to change the size of the source resistance. Figure 6 shown.

[0077] Taking Relay 1 as an example, closing the relay downward connects the 10kΩ resistor to the circuit; closing the relay upward disconnects the 10kΩ resistor. The relay's control signal is connected to the USB-6211's digital output control terminal. By feeding different signals to the control terminal, different source resistor values can be generated. This solution distributes the voltage appropriately by varying the resistance, allowing the adapter to condition the signal to fit within the platform's input range.

[0078] The working principle of the detection system provided by the present invention is to obtain a suitable test stimulus, set the excitation signal parameters of the circuit, and directly apply the sensor or detection device to the fault-free circuit. The sensor or detection device can convert the obtained signal into the same or other type of quantitative value output according to a certain rule, usually an electrical signal. The measured signal is converted by the sensor into a corresponding electrical signal. The hardware part of the detection system is responsible for collecting relevant raw data, conditioning and amplifying the data, and then effectively inputting the data into a computer. After the data is input, it must be processed by the computer. To this end, an improved distance algorithm program must be input into the computer in advance. The computer processes the data according to the instructions and requirements of the program, obtains the voltage signal model of the detection point, uses the threshold determination method to obtain the threshold, and uses this as the fault-free distance judgment standard. The transient response signal of the circuit under normal conditions is obtained as a time series reference. Then, the response of the suspected fault circuit is directly measured. The excitation signal remains unchanged. The transient response signal of the circuit under suspicious conditions is obtained. The computer calculates the two signal models according to a pre-designed program to obtain the distance, which is compared with the threshold. If , the circuit is considered to be in a fault state. Otherwise, the circuit is normal.

[0079] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A method for detecting electronic device faults based on discrete sequences and asymmetric distances, characterized in that: The following steps are involved: S1. Select a fault-free circuit model as the application object; S2. The excitation signal generated by the test signal generation module is applied to two different nodes on the application object in step S1 through the detection module to obtain circuit response signals of the two different nodes; S3, using a response signal feature extraction module to collect a number of response instantaneous values at equal time intervals from the response signals of the two different node circuits obtained in step S2 to form a signal feature curve, that is, to obtain a discrete-time signal model A and a discrete-time signal model B; S4, construct a continuous path K=k1, k2…k according to the point-to-point matching method in the signal model A and the signal model B obtained in step S3 m , where line segment k i The two ends correspond to the data points in X and Y respectively, and define a mapping function f i :(X,Y)→K, map the relationship between point pairs to path K, and then find the path K' with the minimum distance; The data points in the path K are matched according to the following two constraints: (1) Endpoint alignment: the first point a1 of sequence A is aligned with the first point b1 of sequence B, and the last point a m and b m Alignment, that is: (2) Monotonicity: the path moves monotonically along the time axis, that is: ； S5. Calculate a series of distances D based on the path K' obtained in step S4 ij , select the largest distance as the fault detection threshold D f , that is, D f =max{D ij }; S6, applying the same excitation signal as in step S2 to the circuit model to be tested through the detection module to obtain a circuit response signal; S7, collecting a number of response instantaneous values at equal time intervals in the circuit response signal obtained in step S6 to form a signal feature vector, that is, obtaining a discrete-time signal model C; S8, construct a continuous path N=n1, n2…n according to the point-to-point matching method in the signal model C obtained in step S7 and the signal model A obtained in step S3 m , where line segment n i The two ends correspond to the data points in X and Y respectively, and define a mapping function f i :(X,Y)→N, map the relationship between point pairs to the path N, and then find the path N' with the minimum distance; S9, according to the path N' obtained in step S8, a series of distances D are obtained, and the distance D is compared with the threshold D obtained in step S5. f Compare, if D>D f , the circuit is considered to be in a fault state, otherwise, the circuit is normal.

2. An electronic equipment fault detection system, characterized in that: The method for detecting electronic device faults based on discrete sequences and asymmetric distances according to claim 1 is implemented, comprising: A test signal generation module is used to generate test excitation signal data according to external input signal parameters and send it to the detection module; a response signal feature extraction module, configured to collect the circuit response signal of the circuit under test output by the analog-to-digital converter, perform feature extraction on a number of response instantaneous values at equal time intervals in the obtained circuit response signal, obtain a characteristic curve, and send the result to the display module and the characteristic curve similarity comparison module; The characteristic curve similarity comparison module is used to compare the unknown board curve obtained by the response signal characteristic extraction module with the normal board curve to determine whether the board to be tested is within the tolerance range; The detection module is used to obtain the excitation signal generated by the test signal generation module, apply the obtained excitation signal to the circuit under test, and convert it into a circuit response signal of the circuit under test and then output it; An analog-to-digital converter, used to perform analog-to-digital conversion on the circuit response signal acquired by the detection module and then send the result to the response signal feature extraction module; The adapter is used to match the source resistance and the impedance of the device under test, balance the voltage distribution, and make the signal curve obtained by the response signal feature extraction module convenient for subsequent comparison; The display module is used to display the characteristic curve obtained by the response signal feature extraction module.

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