Low-power FFT implementation method based on signal group sampling and hardware accelerator

Abstract

The present invention is a low-power FFT implementation method based on signal group sampling and hardware accelerator. It uses a single-chip microcomputer integrated with a low-power digital signal processing accelerator (LEA) and a multi-channel analog-to-digital converter (ADC) as the signal sampling and processing core. It adopts signal hardware group sampling, FFT hardware accelerated calculation and result software synthesis technology to realize multi-point, low-power FFT operation. The multi-channel ADC, LEA and CPU integrated on the single-chip microcomputer work together to complete the operation. In response to the multi-point FFT operation requirements, the single-chip microcomputer first controls the ADC to perform multi-channel hardware grouping equal-interval continuous cyclic sampling on the signal. The hardware group sampling is used to divide the signal into multiple groups of small-point sampling sequences according to the time parity method; then, the small-point sampling sequences are sent to the LEA group by group for FFT hardware accelerated calculation to obtain the FFT results of each group of small-point sampling sequences; finally, the CPU performs software synthesis on the FFT results of multiple groups of small-point sampling sequences to obtain the multi-point FFT results of the signal.

Description

Technical Field

[0001] The present invention relates to the field of signal processing and is a low-power FFT implementation method based on group sampling and hardware accelerator. A single-chip microcomputer integrating a low-power digital signal processing accelerator and a multi-channel analog-to-digital converter is used as the signal sampling and processing core. Hardware group sampling and hardware accelerated computing technology are used to improve the calculation speed of FFT, thereby realizing low-power embedded FFT operation. Background Art

[0002] The Fast Fourier Transform (FFT) is a classic digital signal processing algorithm widely used for signal analysis in engineering. Many embedded digital instruments also employ FFT algorithms to perform spectral analysis on signals, thereby obtaining signal characteristics or measuring physical quantities. In embedded applications, FFT algorithms require processors with high digital signal processing capabilities to meet the demands of fast analysis and calculation. Consequently, specialized digital signal processors (DSPs) are often used to perform FFT operations. However, DSPs typically consume high power, making them difficult to meet the requirements of low-power applications. In applications requiring low power, low-power microcontrollers are often used as processors. However, their efficiency in executing FFT algorithms is relatively limited. While they can meet the analysis requirements of some applications, they limit the potential for algorithm improvement and enhancement. While selecting a low-power microcontroller with higher CPU performance can provide greater computing power to meet the requirements of complex signal processing involving FFT operations, it also increases cost and power consumption. Currently, microcontroller technology and various hardware-accelerated computing technologies are developing rapidly. Low-power microcontrollers with digital signal processing hardware acceleration modules have also been introduced, such as Texas Instruments' MSP430 microcontroller with a low-energy digital signal processing accelerator (LEA). This further enhances the digital signal processing capabilities of low-power microcontrollers and provides a better choice for low-cost, low-power embedded FFT calculations. However, the number of points supported by digital signal processing accelerators integrated in microcontrollers is limited. For example, the LEA integrated in the MSP430FR5994 microcontroller can only support a 512-point real FFT operation or a 512-point complex FFT operation at a time, which often cannot meet the needs of practical applications for FFT operations with larger points.

[0003] The present invention is based on a single-chip microcomputer that integrates a low-energy digital signal processing accelerator (LEA) and a multi-channel analog-to-digital converter (ADC). It uses hardware group sampling, hardware accelerated calculation and software synthesis technology to improve the speed of multi-point FFT operations to meet the low-power, multi-point FFT operation requirements of different applications. Summary of the Invention

[0004] The present invention aims to solve the problem that single-chip microcomputers in current low-power embedded system applications are difficult to perform fast FFT operations due to limited performance or power consumption. The present invention provides a multi-point, low-power FFT implementation method that uses a single-chip microcomputer with an integrated low-power digital signal processing accelerator and a multi-channel analog-to-digital converter as the signal sampling and processing core, and adopts signal group sampling, hardware accelerated calculation and software synthesis technology to further reduce system power consumption while improving the low-power embedded FFT operation performance.

[0005] The technical solution adopted by the present invention is: a single-chip microcomputer integrating a low-power digital signal processing accelerator (LEA) and a multi-channel analog-to-digital converter (ADC) is used as the signal sampling and processing core; in response to the multi-point FFT operation requirements, the single-chip microcomputer controls the ADC to perform multi-channel hardware grouping and equal-interval continuous cyclic sequential sampling on the signal, and automatically divides the signal into multiple groups of small-point sampling sequences according to the time parity through hardware grouping sampling, thereby avoiding the need for the single-chip microcomputer CPU to perform software grouping on the data sequence; then, the small-point sampling sequences are sent group by group to the LEA on the single-chip microcomputer for FFT hardware accelerated calculation to obtain the FFT results of each group of small-point sampling sequences; finally, the CPU on the single-chip microcomputer performs software synthesis on the FFT results of multiple groups of small-point sampling sequences through software program calculation to obtain the multi-point FFT results of the signal. Based on this, the FFT operations of multi-point data groups and group sequences are all completed by hardware, and only the software synthesis of the FFT results of the group sequence is executed by the CPU of the microcontroller. The parallel processing of hardware and software can reduce the power consumption of the microcontroller, accelerate the calculation speed of multi-point FFT, and improve the task capability of the microcontroller.

[0006] The low power consumption FFT implementation method of the present invention is as follows: Figure 1 As shown, the process includes hardware group sampling 1, FFT hardware accelerated calculation 2, and FFT result software synthesis 3, which are collaboratively completed by a multi-channel ADC module 4, a LEA module 5, and a CPU module 6 integrated on the single chip.

[0007] The hardware group sampling 1 is that the multi-channel ADC module 4 on the single-chip microcomputer performs multi-channel hardware group sampling on the signal x on the analog channel connected to the ADC module 4; the number of groups Q = N / M, N is the total length of the sequence to be FFT-operated on the signal x, M is the number of points supported by the LEA module 5 in the single-chip microcomputer for a single real FFT operation or twice the number of points supported by the LEA module 5 in the single-chip microcomputer, N, Q, and M are all integer powers of 2, and Q ≥ 1; the number of groups Q is preferably such that M is equal to the larger value of the number of points supported by the LEA module 5 for a single real FFT operation or twice the number of points supported by the LEA module 5 for a single complex FFT operation, so as to reduce the number of groups and the amount of computation required for the FFT result software synthesis 3; according to the different working principles of the multi-channel ADC modules on different single-chip microcomputers, one of the following schemes is selected to implement the hardware group sampling of the signal:

[0008] Hardware group sampling solution 1: The analog signal x to be analyzed is connected to the Q analog input channels of the multi-channel ADC module 4 of the single-chip microcomputer. The multi-channel ADC module 4 is controlled by the single-chip microcomputer to perform continuous and cyclical sampling of the Q analog input channels connected to the signal x at equal intervals, thus realizing hardware group sampling of the signal x. This solution requires more ADC analog input channels, but it is more versatile.

[0009] Hardware Group Sampling Solution 2: The analog signal x to be analyzed is connected to only one analog input channel of the MCU's multi-channel ADC module 4. The MCU software configures each of the Q conversion channels of the multi-channel ADC module 4 to be bound to the same analog input channel to which signal x is connected. The MCU then performs hardware group sampling of signal x by controlling the Q conversion channels of the multi-channel ADC module 4 to perform continuous, cyclical sampling at equal intervals. This solution is the preferred option, as it does not occupy any additional ADC analog input channels, offers flexible configuration of the group number Q, and places low impedance matching requirements on the signal source. It is therefore suitable for MCUs that support this operating mode.

[0010] The above-mentioned equal-interval continuous cyclic sequential sampling method is to perform equal-interval sampling on the signals of Q channels in a continuous cyclic manner of channel 0 → channel 1 → channel 2 → … → channel Q-1 → channel 0 → channel 1 → channel 2 → … → channel Q-1 → channel 0 → channel 1 → channel 2 → …, the sampling interval time Ts between channels is the sampling period of the analog signal x, and fs = 1 / Ts is the sampling rate of the analog signal x.

[0011] Based on the above group sampling scheme, we can obtain the real number sampling sequences x0(m), x1(m), x2(m)...x of signal x in Q groups with length M. Q-1 (m), m=0,1,2,3,…,M-1.

[0012] The FFT hardware accelerated calculation 2 is to convert the Q sampling sequences x0(m), x1(m), x2(m) ... x of the signal x into Q-1 (m) are sequentially sent to the LEA module 5 on the single-chip microcomputer for FFT operation; if the sequence length M is equal to the number of single real FFT operation points supported by the LEA module 5, the LEA module 5 preferably performs real FFT operation and may also select complex FFT operation; if the sequence length M exceeds the number of single real FFT operation points supported by the LEA module 5 but is equal to twice the number of single complex FFT operation points supported by the LEA module 5, the LEA module 5 selects complex FFT operation to calculate the real FFT; according to the FFT operation results of the LEA module 5, Q groups of sampling sequences x0(m), x1(m), x2(m) ... x are directly obtained respectively. Q-1 (m) FFT results X0(k), X1(k), X2(k) ... X Q-1 The first half of (k), that is, k = 0, 1, 2, 3, ..., M / 2-1.

[0013] The FFT result software synthesis 3 is to perform the FFT operation results X0(k), X1(k), X2(k) ... X of the Q group sampling sequences in the CPU module 6 of the single chip computer by software. Q-1 (k) Perform R-level step-by-step synthesis, R = log2Q, i.e. Q = 2 R , obtain the FFT result X(k) of the N-point sequence of signal x under the sampling rate of fs, k = 0, 1, 2, 3, ..., N-1; the synthesis steps are as follows:

[0014] Step 1: FFT result X for each set of sampling sequences q (k), calculate

[0015] Step 2: Let r = R;

[0016] Step 3: Sort by bits in reverse order, let X ri (k) = X q (k); i,q=0,1,2,…,Q-1, i and q are in the order of binary bits, so we get X r0 (k), X r1 (k), X r2 (k)……X r(Q-1) (k), k=0,1,2,3,…,M / 2;

[0017] Step 4: Calculate the FFT result of the r-1th level sequence based on the FFT results of each group of sequences at the rth level:

[0018]

[0019] Where i is the sequence group number of the r-1th level, i = 0, 1, 2, ..., 2 r-1 -1; L is the length of each sequence of the r-th level group, L = N / 2 r , when r=R, L=M; U=N / 2 r-1 , The symbol “j” represents the complex imaginary part, and the symbol “*” represents the conjugate;

[0020] Step 5: Let r = r-1, and loop to step 4 until r = 1, and get X 00 (k), k=0,1,2,3,…N / 2;

[0021] Step 6: Based on the synthesis result X of step 5 00 (k) and the circular conjugate characteristics of the real sequence FFT result to obtain the FFT result X(k) of the N-point real sequence of the signal x when the sampling rate is fs:

[0022]

[0023] In the spectrum analysis of real signals, only the first N / 2 points of X(k) are needed, and there is no need to calculate the values ​​of the last half of X(k) according to the above formula.

[0024] The advantages of the present invention are as follows: a single-chip microcomputer integrating a low-power digital signal processing accelerator (LEA) and a multi-channel analog-to-digital converter (ADC) is used as the signal sampling and processing core; for multi-point FFT situations, a multi-channel ADC module is used to perform hardware group sampling on the signal, achieving parity grouping of the signal upon completion of signal sampling, saving CPU resources of the single-chip microcomputer and reducing power consumption requirements; then, the LEA performs FFT acceleration calculations on each group sequence, improving FFT execution efficiency and also reducing power consumption; finally, the CPU performs software synthesis of the LEA calculation results to obtain multi-point FFT results. The present invention adopts a hardware and software combination approach, which not only significantly saves the CPU overhead of the single-chip microcomputer, leaving more computing power space for other complex tasks, but also reduces the power consumption of the system by leveraging the low power consumption characteristics of the LEA and the reduction in CPU overhead, thereby significantly improving the energy efficiency ratio of digital signal processing in low-power embedded systems and providing a new optimization solution for low-power signal processing applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a technical flow chart of the method of the present invention;

[0026] Figure 2 This is a block diagram of a low-power single-chip FFT function implementation based on multi-channel ADC analog input channel group sampling according to a specific embodiment of the present invention;

[0027] Figure 3This is a block diagram of a low-power single-chip FFT function implementation based on multi-channel ADC internal conversion channel grouping sampling according to a specific embodiment of the present invention;

[0028] Figure 4 2. It is a schematic diagram of a multi-channel ADC hardware equally spaced continuous cyclic sequential sampling method and results according to a specific embodiment of the present invention;

[0029] Figure 5 It is a schematic diagram of the mapping relationship of the reverse order grouping before the software synthesis of the FFT results of the group sequence in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below with reference to the accompanying drawings:

[0031] The design concept of the present invention is: based on the low-power single-chip microcomputer technology that integrates a low-power digital signal processing accelerator (LEA) and a multi-channel analog-to-digital converter (ADC), the digital signal processing hardware acceleration capability of the LEA and the sampling control characteristics of the multi-channel ADC are fully utilized to improve the energy efficiency of multi-point FFT operations through hardware and software coordination, thereby realizing low-power, multi-point embedded FFT operations; specifically, when the length of the signal sequence exceeds the length limit of the direct FFT operation of the LEA on the single-chip microcomputer, the multi-channel ADC on the single-chip microcomputer is used to perform hardware group sampling on the signal, and the parity grouping of the signal is completed during the signal sequence sampling process, and the required multi-point signal sequence is divided into the required number of points according to the FFT operation length supported by the LEA. The method restricts the signal sequence into multiple groups of small-point signal sequences, thereby avoiding the CPU's requirement for signal grouping in the case of single-channel sampling and saving CPU overhead. Then, the sampled multiple groups of small-point signal sequences are fed into the LEA one by one, and the hardware acceleration technology and low-power characteristics of the LEA are used to implement energy-efficient FFT operations on the multiple groups of signal sequences. Finally, the FFT results of the multiple groups of small-point signal sequences calculated by the LEA are software-synthesized by the CPU of the single-chip microcomputer to obtain the FFT results of the entire multi-point signal sequence. Thus, this method saves most of the CPU overhead in the multi-point FFT calculation process by leveraging hardware group sampling and LEA hardware acceleration calculation technology, while also improving the FFT operation speed and reducing system energy consumption. Therefore, the method of the present invention can provide a solution with a high energy efficiency ratio for low-power embedded signal processing applications.

[0032] The technical solution process of the present invention is as follows Figure 1 The low-power FFT implementation process includes hardware group sampling 1, FFT hardware accelerated calculation 2, and FFT result software synthesis 3; its corresponding low-power microcontroller function implementation block diagram is shown in Figure 2 and Figure 3 As shown, the multi-channel ADC module 4, LEA module 5, and CPU module 6 integrated on the single chip are coordinated to complete the operation.

[0033] The hardware group sampling 1 is that the multi-channel ADC module 4 on the single-chip microcomputer performs multi-channel hardware group sampling on the signal x on the analog channel connected to the ADC module 4; the number of groups Q = N / M, N is the total length of the sequence to be FFT-operated on the signal x, M is the number of points supported by the LEA module 5 in the single-chip microcomputer for a single real FFT operation or twice the number of points supported by the LEA module 5 in the single-chip microcomputer, N, Q, and M are all integer powers of 2, and Q ≥ 1; the number of groups Q is preferably such that M is equal to the larger value of the number of points supported by the LEA module 5 for a single real FFT operation or twice the number of points supported by the LEA module 5 for a single complex FFT operation, so as to reduce the number of groups and the amount of computation required for the FFT result software synthesis 3; according to the different working principles of the multi-channel ADC modules on different single-chip microcomputers, one of the following schemes is selected to implement the hardware group sampling of the signal:

[0034] Hardware group sampling scheme 1: The analog signal x to be analyzed is connected to the Q analog input channels of the multi-channel ADC module 4 of the microcontroller. Figure 2 As shown; the single-chip microcomputer controls the multi-channel ADC module 4 to perform equal-interval continuous cyclic sequential sampling on the Q analog input channels connected to the signal x, thereby realizing hardware group sampling of the signal x; this solution requires occupying more ADC analog input channels, but it has strong versatility;

[0035] Hardware group sampling solution 2: The analog signal x to be analyzed is connected to only one analog input channel of the multi-channel ADC module 4 of the single-chip microcomputer in the hardware. The Q conversion channels of the multi-channel ADC module 4 are all bound to the same analog input channel connected to the signal x by the single-chip microcomputer software configuration, such as Figure 3 As shown in FIG. 1 , the single-chip microcomputer controls the Q conversion channels of the multi-channel ADC module 4 to perform continuous and cyclical sampling at equal intervals, thereby realizing hardware group sampling of the signal x. This solution is the preferred solution because it does not occupy any additional analog input channels of the ADC, and the number of groups Q can be flexibly configured. It has low impedance matching requirements for the signal source and is suitable for single-chip microcomputers that support this working mode, such as TI's MSP430 series low-power single-chip microcomputers.

[0036] The above-mentioned equal-interval continuous cyclic sequential sampling method is to perform equal-interval sampling on the signals of Q channels in a continuous cyclic manner of channel 0 → channel 1 → channel 2 → … → channel Q-1 → channel 0 → channel 1 → channel 2 → … → channel Q-1 → channel 0 → channel 1 → channel 2 → …, the sampling interval time Ts between channels is the sampling period of the analog signal x, and fs = 1 / Ts is the sampling rate of the analog signal x.

[0037] Based on the above group sampling scheme, we can obtain the real number sampling sequences x0(m), x1(m), x2(m)...x of signal x in Q groups with length M. Q-1(m), m=0,1,2,3,…,M-1.

[0038] Figure 4 The figure shows a hardware group sampling method and a result diagram of using 4 channels to perform equal-interval continuous cyclic sequential sampling on the signal x at time intervals Ts.

[0039] The FFT hardware accelerated calculation 2 is to convert the Q sampling sequences x0(m), x1(m), x2(m) ... x of the signal x into Q-1 (m) are sequentially sent to the LEA module 5 on the single-chip microcomputer for FFT operation; if the sequence length M is equal to the number of single real FFT operation points supported by the LEA module 5, the LEA module 5 preferably performs real FFT operation and may also select complex FFT operation; if the sequence length M exceeds the number of single real FFT operation points supported by the LEA module 5 but is equal to twice the number of single complex FFT operation points supported by the LEA module 5, the LEA module 5 selects complex FFT operation to calculate the real FFT; according to the FFT operation results of the LEA module 5, Q groups of sampling sequences x0(m), x1(m), x2(m) ... x are directly obtained respectively. Q-1 (m) FFT results X0(k), X1(k), X2(k) ... X Q-1 The first half of (k), that is, k = 0, 1, 2, 3, ..., M / 2-1.

[0040] The FFT result software synthesis 3 is to perform the FFT operation results X0(k), X1(k), X2(k) ... X of the Q group sampling sequences in the CPU module 6 of the single chip computer by software. Q-1 (k) Perform R-level step-by-step synthesis, R = log2Q, i.e. Q = 2 R , obtain the FFT result X(k) of the N-point sequence of signal x under the sampling rate of fs, k = 0, 1, 2, 3, ..., N-1; the synthesis steps are as follows:

[0041] Step 1: FFT result X for each set of sampling sequences q (k), calculate

[0042] Step 2: Let r = R;

[0043] Step 3: Sort by bits in reverse order, let X ri (k) = X q (k); i,q=0,1,2,…,Q-1, i and q are in the order of binary bits, so we get X r0 (k), X r1 (k), X r2 (k)……X r(Q-1)(k), k=0,1,2,3,…,M / 2; the FFT result bit reverse order mapping relationship of the group sequence in the case of 2 groups, 4 groups, and 8 groups is as follows Figure 5 shown.

[0044] Step 4: Calculate the FFT result of the r-1th level sequence based on the FFT results of each group of sequences at the rth level:

[0045]

[0046] Where i is the sequence group number of the r-1th level, i = 0, 1, 2, ..., 2 r-1 -1; L is the length of each sequence of the r-th level group, L = N / 2 r , when r=R, L=M; U=N / 2 r-1 , The symbol “j” represents the complex imaginary part, and the symbol “*” represents the conjugate;

[0047] Step 5: Let r = r-1, and loop to step 4 until r = 1, and get X 00 (k), k=0,1,2,3,…N / 2;

[0048] Step 6: Based on the synthesis result X of step 5 00 (k) and the circular conjugate characteristics of the real sequence FFT result to obtain the FFT result X(k) of the N-point real sequence of the signal x when the sampling rate is fs:

[0049]

[0050] In the spectrum analysis of real signals, only the first N / 2 points of X(k) are needed, and there is no need to calculate the values ​​of the last half of X(k) according to the above formula.

[0051] In summary, the present invention's low-power FFT implementation method based on signal group sampling and hardware accelerator can significantly improve the energy efficiency of digital signal processing in low-power embedded systems and can be applied to complex industrial measurements with high low-power requirements. Suitable low-power microcontrollers for the present method include the MSP430 series MCUs with LEA produced by Texas Instruments (TI), such as the MSP430FR599x, MSP430FR504x, and MSP430FR604x MCUs.

Claims

1. A low-power FFT implementation method based on signal group sampling and hardware accelerator uses a single-chip microcontroller (MCU) integrated with a low-power digital signal processing accelerator and a multi-channel analog-to-digital converter (ADC) as the signal sampling and processing core. Signal group sampling, hardware accelerated computing, and software synthesis techniques are used to implement multi-point, low-power FFT operations, thereby improving the performance of low-power embedded FFT operations while further reducing system power consumption. Hereinafter, the low-power digital signal processing accelerator is referred to as LEA, and the analog-to-digital converter is referred to as ADC. The method's technical process is hardware group sampling → FFT hardware accelerated computing → FFT result software synthesis, and is accomplished collaboratively by the multi-channel ADC, LEA, and CPU integrated on the MCU. The method is characterized by: To meet the requirements of multi-point FFT operations, the MCU first controls the multi-channel ADC to perform hardware group sampling on the signal. That is, the signal is sampled in a continuous and cyclical sequence with equal intervals in multi-channel hardware grouping. Through hardware group sampling, the signal is automatically divided into multiple groups of small-point sampling sequences according to the time parity. Then, the small-point sampling sequences are sent to the LEA on the MCU for FFT hardware accelerated calculation, and the FFT results of each group of small-point sampling sequences are obtained. Finally, the CPU on the MCU performs software synthesis of the FFT results of multiple groups of small-point sampling sequences through software program calculation to obtain the multi-point FFT result of the signal. The hardware group sampling is to perform multi-channel hardware group sampling on the signal x on the analog channel connected to the ADC by the multi-channel ADC on the single-chip microcomputer; the number of groups Q = N / M, where N is the total length of the sequence to be FFT-operated on the signal x, and M is the number of points of a single real FFT operation or twice the number of points of a single complex FFT operation supported by the LEA in the single-chip microcomputer, and N, Q, and M are all integer powers of 2, and Q ≥ 1; the number of groups Q is such that M is equal to the larger value of the number of points of a single real FFT operation and twice the number of points of a single complex FFT operation supported by the LEA, so as to reduce the number of groups and reduce the computational complexity of software synthesis of the FFT results; The FFT hardware accelerated calculation is to convert the Q sampling sequences x0(m), x1(m), x2(m) ... x of the signal x into Q-1 (m) are sequentially sent to the LEA on the single-chip microcomputer for FFT operation; if the sequence length M is equal to the number of single real FFT operation points supported by LEA, LEA selects real FFT operation or complex FFT operation; if the sequence length M exceeds the number of single real FFT operation points supported by LEA but is equal to twice the number of single complex FFT operation points supported by LEA, LEA selects complex FFT operation to calculate the real FFT; Q groups of sampling sequences x0(m), x1(m), x2(m) ... x are directly obtained according to the FFT operation results of LEA. Q-1 (m) FFT results X0(k), X1(k), X2(k) ... X Q-1 The first half of (k), that is, k = 0, 1, 2, 3, ..., M / 2-1.

2. The low-power FFT implementation method based on signal group sampling and hardware accelerator according to claim 1, characterized in that: Depending on the operating principles of the multi-channel ADCs on different MCUs, hardware group sampling of signals can be implemented using one of the following solutions: Hardware group sampling solution 1: The analog signal x to be analyzed is connected to the Q analog input channels of the multi-channel ADC of the microcontroller. The multi-channel ADC is controlled by the microcontroller to perform continuous and cyclic sampling of the Q analog input channels at equal intervals, thus realizing hardware group sampling of signal x. Hardware group sampling solution 2: The analog signal x to be analyzed is connected to only one analog input channel of the MCU's multi-channel ADC. The MCU software is configured to bind all Q conversion channels of the multi-channel ADC to the same analog input channel connected to signal x. The MCU controls the Q conversion channels of the multi-channel ADC to perform continuous, cyclical sampling at equal intervals, thereby achieving hardware group sampling of signal x. It does not occupy any additional analog input channels of the ADC, and the group number Q configuration is flexible and variable. It has low impedance matching requirements for the signal source and is suitable for microcontrollers that support this working mode. The above-mentioned equal-interval continuous cyclic sequential sampling method is to sample the signals of Q channels at equal intervals in a continuous cyclic manner of channel 0 → channel 1 → channel 2 → ... → channel Q-1 → channel 0 → channel 1 → channel 2 → ... → channel Q-1 → channel 0 → channel 1 → channel 2 → .... The sampling interval time Ts between channels is the sampling period of the analog signal x, and fs = 1 / Ts is the sampling rate of the analog signal x; Based on the above group sampling scheme, we can obtain the real number sampling sequences x0(m), x1(m), x2(m)...x of signal x in Q groups with length M. Q-1 (m), m=0,1,2,3,…,M-1.

3. The low-power FFT implementation method based on signal group sampling and hardware accelerator according to claim 1, characterized in that: The FFT result software synthesis is to use software to perform the FFT operation results X0(k), X1(k), X2(k)...X on the Q group of sampling sequences in the CPU of the single chip microcomputer. Q-1 (k) Perform R-level step-by-step synthesis, R = log2Q, i.e. Q = 2 R , obtain the FFT result X(k) of the N-point sequence of signal x under the sampling rate of fs, k = 0, 1, 2, 3, ..., N-1; the synthesis steps are as follows: Step 1: FFT result X for each set of sampling sequences q (k), calculate Step 2: Let r = R; Step 3: Sort by bits in reverse order, let X ri (k) = X q (k); i,q=0,1,2,…,Q-1, i and q are in the order of binary bits, so we get X r0 (k), X r1 (k), X r2 (k)……X r(Q-1) (k), k=0,1,2,3,…,M / 2; Step 4: Calculate the FFT result of the r-1th level sequence based on the FFT results of each group of sequences at the rth level: Where i is the sequence group number of the r-1th level, i = 0, 1, 2, ..., 2 r-1 -1; L is the length of each sequence of the r-th level group, L = N / 2 r , when r=R, L=M; U=N / 2 r-1 , The symbol "j" represents the complex imaginary part, and the symbol "*" represents the conjugate; Step 5: Let r = r-1, and loop to step 4 until r = 1, and get X 00 (k), k=0,1,2,3,…N / 2; Step 6: Based on the synthesis result X of step 5 00 (k) and the circular conjugate characteristics of the real sequence FFT result to obtain the FFT result X(k) of the N-point real sequence of the signal x when the sampling rate is fs: In the spectrum analysis of real signals, only the first N / 2 points of X(k) are needed, and there is no need to calculate the values ​​of the last half of X(k) according to the above formula.

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