A SRAM single-event hardening circuit simulation method based on HSPICE and Weibull function

Abstract

The present invention relates to a method for simulating an SRAM single-particle reinforcement circuit based on HSPICE and a Weibull function. The method comprises: constructing a read / write simulation circuit structure for an SRAM reinforcement unit, the read / write simulation circuit structure comprising the SRAM reinforcement unit and two tri-state gates, wherein the output ends of the two tri-state gates are correspondingly connected to a first bit line and a second bit line of the SRAM reinforcement unit, and an external word line control voltage is input to the word line of the SRAM reinforcement unit; performing read and write operation simulation verification on the SRAM reinforcement unit by controlling the outputs of the tri-state gates and the external word line control voltage; obtaining a Weibull function current source, and performing single-particle effect simulation on the SRAM reinforcement unit based on the Weibull function current source and the read / write simulation circuit structure; wherein the Weibull function current source is obtained by fitting the single-particle effect data using the Weibull function. The present invention can effectively and quickly evaluate the function and performance of an SRAM circuit reinforcement unit.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an SRAM single particle reinforcement circuit simulation method based on HSPICE and Weibull function. Background Art

[0002] Radiation effects are the main cause of spacecraft failures, with single-event effects (SEPs) dominating the radiation-induced failures, accounting for up to 80% of them. Static Random Access Memory (SRAM) is an essential component of aerospace electronics systems.

[0003] Classic 6T-SRAM features high per-bit sensitivity, low node capacitance, and low power consumption, requiring no refresh circuitry to preserve data. However, its radiation resistance is weak, making it susceptible to single-event upset (SEE) errors, which can lead to stored data errors. Therefore, in practical applications, SEE hardening testing of SRAM cells is necessary, and appropriate simulation solutions are required during SEE testing of these hardened cells.

[0004] In the existing technology, CADENCE software is often used to inject corresponding voltages into each port of the reinforcement circuit and add a double exponential current source for simulation. However, this solution has the problems of complex addition of voltage and current sources, and the current source model itself has reduced accuracy as the process size decreases. Summary of the Invention

[0005] To address the above-mentioned problems in the prior art, the present invention provides a method for simulating SRAM single-event hardening circuits based on HSPICE and Weibull functions. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a SRAM single-particle hardening circuit simulation method based on HSPICE and Weibull function, comprising:

[0007] Step 1: Construct a read / write simulation circuit structure of the SRAM reinforcement unit, the read / write simulation circuit structure includes an SRAM reinforcement unit and two tri-state gates, wherein the output ends of the two tri-state gates are correspondingly connected to the first bit line and the second bit line of the SRAM reinforcement unit, and the word line of the SRAM reinforcement unit inputs an external word line control voltage;

[0008] Step 2: Performing read and write operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage;

[0009] Step 3: Obtain a Weibull function current source, and perform a single event effect simulation on the SRAM reinforcement unit based on the Weibull function current source and the read-write simulation circuit structure;

[0010] The Weibull function current source is obtained by fitting the single event effect data using the Weibull function.

[0011] In one embodiment of the present invention, the tri-state gate is used to generate three control signals: high level, low level and high impedance state.

[0012] In one embodiment of the present invention, step 2 includes:

[0013] Step 2.1: Performing a write operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage, including:

[0014] controlling the external word line control voltage to set the word line to a high level, controlling the output of the tri-state gate to set the first bit line and the second bit line to two opposite levels, observing potential changes of the first storage node and the second storage node of the SRAM reinforcement unit, and determining whether the write operation is successful based on the observation results;

[0015] Step 2.2: Performing a read operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage, including:

[0016] After controlling the output of the tri-state gate to set the first bit line and the second bit line to a high level, controlling the outputs of the two tri-state gates to be high-impedance control signals, controlling the external word line control voltage to set the word line to a high level, observing the potential changes of the first bit line and the second bit line, and judging whether the read operation is successful based on the observation results.

[0017] In one embodiment of the present invention, in step 3, obtaining a Weibull function current source includes:

[0018] The single event effect data obtained from experimental simulation;

[0019] The single event effect data is fitted with a Weibull function to obtain the Weibull function current source. The fitting formula of the Weibull function current source is expressed as:

[0020]

[0021] Wherein, t represents the time variable, a represents the first fitting parameter, b represents the second fitting parameter, and c represents the third fitting parameter.

[0022]

[0023] Where AP represents the pulse current at 0-t p Integral over time, t p It represents the time corresponding to the peak value of the pulse current, A represents the integral of the current pulse and time, and H represents the peak value of the pulse current.

[0024] In one embodiment of the present invention, in step 3, performing a single event effect simulation on the SRAM reinforcement unit according to the Weibull function current source and the read / write simulation circuit structure includes:

[0025] Changing the energy of the Weibull function current source to obtain Weibull function current sources with different energies;

[0026] Using the HSPICE tool, all sensitive nodes of the SRAM reinforcement unit in the read-write simulation circuit structure are sequentially added with the Weibull function current sources of different energies;

[0027] Verify whether each sensitive node can resist the single event upset effect when adding a Weibull function current source with different energy, and realize the single event effect simulation of the SRAM reinforcement unit.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The SRAM single-particle reinforcement circuit simulation method based on HSPICE and Weibull function of the present invention can flexibly control the read and write operations of the SRAM cell by controlling the bit line of the SRAM reinforcement unit with the output end of the tri-state gate and combining it with the voltage control of the word line, thereby realizing the read and write function verification of the proposed SRAM reinforcement unit.

[0030] 2. The SRAM single-particle reinforcement circuit simulation method based on HSPICE and Weibull function of the present invention performs curve fitting on the experimental data or simulation data of the single-particle effect through the Weibull function, thereby forming a Weibull function current source and obtaining a circuit-level single-particle effect simulation model. Compared with the traditional double exponential function simulation model, it improves the accuracy without reducing the circuit simulation speed.

[0031] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of a SRAM single-particle hardening circuit simulation method based on HSPICE and Weibull function provided by an embodiment of the present invention;

[0033] Figure 2 This is a flow chart of a method for simulating an SRAM single-particle hardening circuit based on HSPICE and Weibull function provided by an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of a read-write simulation circuit structure provided by an embodiment of the present invention;

[0035] Figure 4 This is a circuit diagram of an SRAM single-particle hardening circuit simulation based on HSPICE and Weibull function provided by an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of a read-write simulation result provided by an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a single event effect simulation result provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of an SRAM single-particle hardening circuit simulation method based on HSPICE and Weibull function proposed in accordance with the present invention, in combination with the accompanying drawings and specific implementation methods.

[0039] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0040] Example 1

[0041] Please refer to Figure 1 、 Figure 2 and Figure 3 , Figure 1 Schematic diagram of a SRAM single-particle hardening circuit simulation method based on HSPICE and Weibull function provided by an embodiment of the present invention; Figure 2 This is a flow chart of a method for simulating an SRAM single-particle hardening circuit based on HSPICE and Weibull function provided by an embodiment of the present invention; Figure 3This is a schematic diagram of a read-write simulation circuit structure provided by an embodiment of the present invention.

[0042] As shown in the figure, the SRAM single-event hardening circuit simulation method based on HSPICE and Weibull function in this embodiment includes:

[0043] Step 1: Construct the read / write simulation circuit structure of the SRAM reinforcement unit, which includes the SRAM reinforcement unit and two tri-state gates;

[0044] like Figure 3 As shown, the output ends of the two tri-state gates are correspondingly connected to the first bit line BL and the second bit line BLN of the SRAM reinforcement unit, and the word line of the SRAM reinforcement unit inputs the external word line control voltage WL, wherein the tri-state gate is used to generate three control signals: high level, low level and high impedance state.

[0045] Step 2: By controlling the output of the tri-state gate and the external word line control voltage, the read and write operations of the SRAM hardened cell are simulated and verified;

[0046] In this embodiment, step 2 includes:

[0047] Step 2.1: Perform a write operation simulation on the SRAM hardened cell by controlling the output of the tri-state gate and the external word line control voltage, including:

[0048] Control the external word line control voltage WL to set the word line to a high level, control the output of the three-state gate to set the first bit line BL and the second bit line BLN to two opposite levels, observe the potential changes of the first storage node Q and the second storage node QN of the SRAM reinforcement unit, and judge whether the write operation is successful based on the observation results.

[0049] Specifically, if it is observed that the potentials of the first storage node Q and the second storage node QN of the SRAM reinforcement unit have both changed, it indicates that the write operation is successful.

[0050] Step 2.2: Performing a read operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage, including:

[0051] After controlling the output of the three-state gate to set the first bit line and the second bit line to a high level, the outputs of the two three-state gates are controlled to be high-impedance control signals, the external word line control voltage WL is controlled to set the word line to a high level, and the potential changes of the first bit line BL and the second bit line BLN are observed. Based on the observation results, it is determined whether the read operation is successful.

[0052] Specifically, during the read operation simulation, the potential of the first bit line BL and the second bit line BLN will be affected by the potential of the storage node (the first storage node Q and the second storage node QN) and be pulled down or up. If it is observed that the potential of the first bit line BL and the second bit line BLN of the SRAM reinforcement unit have both changed, it indicates that the read operation is successful.

[0053] For example, Figure 5 The figure shows a read / write simulation result. As can be seen, the write-1 and write-0 operations on the SRAM hardened cell are completed at 100ns and 300ns, respectively. The first storage node Q and the second storage node QN also change to 1 and 0, and other nodes also undergo corresponding changes. During the read operation at 200ns and 400ns, the potentials of the first and second bit lines BL and BLN also change accordingly.

[0054] Step 3: Obtain a Weibull function current source, and perform single event effect simulation on the SRAM reinforcement unit based on the Weibull function current source and the read / write simulation circuit structure;

[0055] In this embodiment, a Weibull function is used to fit the single event effect data to obtain a Weibull function current source. Specifically, obtaining the Weibull function current source includes the following steps:

[0056] Step a: Single event effect data obtained from experimental simulation;

[0057] In an optional embodiment, experimental data or simulation data of the single event effect of a device or circuit may be obtained through experiments or high-precision simulations as the single event effect data.

[0058] Step b: Fit the single event effect data with a Weibull function to obtain a Weibull function current source. The fitting formula of the Weibull function current source is expressed as:

[0059]

[0060] Wherein, t represents the time variable, a represents the first fitting parameter, b represents the second fitting parameter, and c represents the third fitting parameter.

[0061]

[0062] Where AP represents the pulse current at 0-t p Integral over time, t p It represents the time corresponding to the peak value of the pulse current, A represents the integral of the current pulse and time, and H represents the peak value of the pulse current.

[0063] In this embodiment, based on the Weibull function current source and the read-write simulation circuit structure, a single event effect simulation is performed on the SRAM reinforcement unit, specifically including:

[0064] Step (1): changing the energy of the Weibull function current source to obtain Weibull function current sources with different energies;

[0065] Step (2): using the HSPICE tool to sequentially add Weibull function current sources of different energies to all sensitive nodes of the SRAM reinforcement unit in the read-write simulation circuit structure;

[0066] Step (3): Verify whether each sensitive node can resist the single-particle upset effect when adding Weibull function current sources with different energies, and realize the single-particle effect simulation of the SRAM reinforcement unit.

[0067] Among them, sensitive nodes are nodes in the circuit structure that are prone to flipping due to single event effects. Figure 4 The circuit diagram of the SRAM single-particle hardening circuit simulation based on HSPICE and Weibull function is shown. In this embodiment, the sensitive nodes are the first storage node Q, the second storage node QN, the node S0 and the node S1. It is necessary to add Weibull function current sources with different energies to the first storage node Q, the second storage node QN, the node S0 and the node S1 in turn to perform a single-particle upset effect test.

[0068] like Figure 6 As shown in the figure, a schematic diagram of the single-particle effect simulation results is shown. As can be seen from the figure, the second storage node QN first flips under the Weibull function current of different energies, and then returns to its initial state, indicating that the node can resist the single-particle upset effect with strong resistance.

[0069] In this embodiment, by extracting the potential level of each node of the SRAM reinforcement unit, it is possible to determine whether the read and write operations are correctly implemented. By adding Weibull function currents of different energies to different sensitive nodes of the SRAM reinforcement unit, it is possible to determine whether the SRAM reinforcement unit can resist the single particle upset effect and the strength of its resistance.

[0070] This embodiment of the SRAM single-particle reinforcement circuit simulation method based on HSPICE and Weibull functions, on the one hand, controls the read and write operations of the SRAM reinforcement unit by using the output of a tri-state gate to control the bit line of the SRAM reinforcement unit, combined with voltage control of the word line, to flexibly control the read and write operations of the SRAM unit, thereby verifying the read and write functions of the proposed SRAM reinforcement unit. On the other hand, the Weibull function is used to perform curve fitting on the experimental data or simulation data of the single-particle effect, thereby forming a Weibull function current source and obtaining a circuit-level simulation model of the single-particle effect. The Weibull current source is added to the sensitive nodes of the SRAM reinforcement unit to implement circuit-level single-particle simulation. Compared with the traditional double exponential function simulation model, it improves the accuracy without reducing the simulation speed of the circuit.

[0071] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0072] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A SRAM single-event hardening circuit simulation method based on HSPICE and Weibull function, characterized in that: include: Step 1: Construct a read / write simulation circuit structure of the SRAM reinforcement unit, the read / write simulation circuit structure includes an SRAM reinforcement unit and two tri-state gates, wherein the output ends of the two tri-state gates are correspondingly connected to the first bit line and the second bit line of the SRAM reinforcement unit, and the word line of the SRAM reinforcement unit inputs an external word line control voltage; Step 2: performing read and write operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage; Step 2 includes: Step 2.1: Performing a write operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage, including: controlling the external word line control voltage to set the word line to a high level, controlling the output of the tri-state gate to set the first bit line and the second bit line to two opposite levels, observing potential changes of the first storage node and the second storage node of the SRAM reinforcement unit, and determining whether the write operation is successful based on the observation results; Step 2.2: Performing a read operation simulation verification on the SRAM reinforcement unit by controlling the output of the tri-state gate and the external word line control voltage, including: controlling the output of the tri-state gate to set both the first bit line and the second bit line to a high level, then controlling the outputs of both tri-state gates to be high-impedance control signals, controlling the external word line control voltage to set the word line to a high level, observing potential changes of the first bit line and the second bit line, and determining whether the read operation is successful based on the observation results; Step 3: Obtain a Weibull function current source, and perform a single event effect simulation on the SRAM reinforcement unit based on the Weibull function current source and the read-write simulation circuit structure; Wherein, the single event effect data is fitted using the Weibull function to obtain the Weibull function current source; In step 3, obtaining a Weibull function current source includes: The single event effect data obtained from experimental simulation; The single event effect data is fitted with a Weibull function to obtain the Weibull function current source. The fitting formula of the Weibull function current source is expressed as: ； Wherein, t represents the time variable, a represents the first fitting parameter, b represents the second fitting parameter, and c represents the third fitting parameter. ； Where, AP Indicates that the pulse current is at 0-t p Integral over time, t p Indicates the time corresponding to the peak value of the pulse current, A represents the integral of the current pulse and time, H Indicates the peak value of the pulse current; In step 3, a single event effect simulation is performed on the SRAM reinforcement unit according to the Weibull function current source and the read-write simulation circuit structure, including: Changing the energy of the Weibull function current source to obtain Weibull function current sources with different energies; Using the HSPICE tool, all sensitive nodes of the SRAM reinforcement unit in the read-write simulation circuit structure are sequentially added with the Weibull function current sources of different energies; Verify whether each sensitive node can resist the single event upset effect when adding a Weibull function current source with different energy, and realize the single event effect simulation of the SRAM reinforcement unit.

2. The SRAM single-event hardening circuit simulation method based on HSPICE and Weibull function according to claim 1, characterized in that: The tri-state gate is used to generate three control signals: high level, low level and high impedance state.

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