Printed circuit board multilayer interconnection method

Abstract

The invention relates to a printed circuit board multilayer interconnection method, which comprises the following steps: firstly, automatically identifying and dividing interconnection channel areas of a circuit board, acquiring multi-dimensional parameters such as materials, thermal expansion coefficients and thermal cycle working conditions, realizing differential distribution and accurate preparation of a nano composite sensing material based on the multi-dimensional parameters, and obtaining the multi-dimensional parameters of the circuit board through an in-situ physical parameter acquisition and self-adaptive discrimination algorithm. Dynamic discrimination of stress abnormity and reverse driving of a micro heater are realized, the structure is induced to generate directional deformation so as to realize local automatic compensation, multi-point parameter data before and after compensation are used for health state modeling and residual life prediction, and big data archiving is combined to feed back manufacturing process optimization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a multi-layer interconnection method for printed circuit board. BACKGROUND

[0002] As the core foundation of the high integration and high performance development of modern electronic products, the interlayer interconnection reliability of multi-layer printed circuit board (PCB), especially the long-term stability under high-frequency thermal cycle conditions, has become a technical problem of industry concern. At present, the mainstream multi-layer PCB interconnection scheme in the industry mainly uses chemical deposition, mechanical drilling and metal filling technology to build interlayer connection channels, and is supplemented by traditional hole filling resin, metal plating or high polymer adhesion process to improve mechanical stability. With the more stringent requirements of high-end applications such as 5G communication, automotive electronics, aerospace, etc. on the high density, high speed and high reliability of PCB, the interlayer interconnection structure is prone to accumulate local thermal stress under long-term thermal cycle load (such as repeated environmental temperature difference, heating caused by current load, etc.), which becomes one of the main causes of inducing interlayer micro-cracks, capillary failure and even whole board functional failure.

[0003] The existing multi-layer PCB thermal cycle reliability control scheme mainly includes optimizing via / hole filling material system (such as using low expansion coefficient insulating matrix or adding matching filler), improving drilling and metal filling process (such as introducing flexible filler or improving filling density), and adding buffer coating on the surface, etc. In some advanced processes, new materials and structure combinations such as low-stress filler, high-modulus copper clad, and local flexible components are developed to try to alleviate the interface stress caused by thermal expansion and contraction. However, such improvement measures are mainly preventive, and once they enter the service period, the process of small accumulation of interlayer thermal stress is usually inside the structure and cannot be easily detected in time through conventional electrical performance detection or visual inspection methods. The current detection methods for PCB interconnection health management, such as X-ray CT, acoustic emission or electrical impedance scanning, can only indirectly confirm after failure occurs, lack of real-time in-situ stress accumulation characterization means, and the timeliness and accuracy of active early warning and health maintenance cannot meet the needs of high reliability occasions.

[0004] Typical representative technologies such as high-reliability hole / via metallization and stress relief resin process are suitable for conventional thermal cycle tolerance design, but there is still a substantial technical gap in online detection and dynamic compensation for repeated subtle thermal stress accumulation and pre-failure state. In addition, in recent years, some scholars have tried to introduce high polymer pressure sensitive adhesive layer and metal-polymer composite film into multi-layer PCB to realize "passive" buffer energy absorption in some positions, but it is difficult to realize active monitoring and real-time regulation of small and complexly distributed stress evolution process, and it is also difficult to carry out individualized health modeling and compensation control for large-scale complex interconnection scenarios at the board level.

[0005] Therefore, the reliability management technology of the current multilayer printed circuit board under the thermal cycle of interlayer interconnection has the following unsolved problems: first, the micro stress accumulation caused by thermal cycle is mostly hidden in the internal structure, and the traditional detection and monitoring means cannot realize in-situ, real-time and quantitative stress monitoring; second, there is a lack of adaptive monitoring and feedback compensation mechanism suitable for material heterogeneity and different structure distribution, and once the interlayer stress accumulates to the dangerous threshold, local failure expansion is easy to occur, affecting the reliability of the whole board; third, the existing method often relies on process front-end modification and material optimization, and has insufficient ability of active maintenance and residual life accurate evaluation for in-service products, which is difficult to support the intelligent operation and maintenance demand of future high-end electronic systems. SUMMARY

[0006] In order to solve the problems existing in the prior art, the present application aims to provide a printed circuit board multilayer interconnection method.

[0007] The printed circuit board multilayer interconnection method described in the present application comprises the following steps:

[0008] S1: For different interlayer interconnection channel regions of the multilayer printed circuit board, the corresponding material parameters, expected thermal expansion coefficient and thermal cycle working condition label are obtained to form the differentiated configuration input of the subsequent nano-composite sensing material distribution.

[0009] S2: Based on the obtained thermal expansion coefficient and working condition label, nano-composite material structure containing conductive and strain sensing function is prepared in each interconnection channel region of the multilayer printed circuit board, so as to realize the differentiated sensitive response to different interlayer thermal stress and strain.

[0010] S3: The thermal stress response type micro shape memory structure or corrugated metal buffer structure unit is respectively embedded in the interconnection channel of the prepared nano-composite material structure, so that the nano-composite material structure and the micro shape memory structure form a coupled response unit for subsequent mechanical compensation.

[0011] S4: The in-situ physical parameter data such as impedance and capacitance of the nano-composite material structure are collected in real time by the external or in-board sensing circuit, and the thermal cycle and region label of the sampling point are associated to realize the multi-dimensional distribution modeling of stress and strain under the conditions of multiple positions and multiple materials.

[0012] S5: Based on the multi-dimensional stress distribution modeling result, the key parameter characteristics are extracted and input into the adaptive threshold judgment algorithm to judge whether there is thermal stress accumulation abnormality or the self-compensation trigger condition in each interconnection channel region.

[0013] S6: When the determination result shows that the stress eigenvalue of a certain interconnection channel region exceeds the set threshold value, a control signal is output to activate the micro-heater of the corresponding region, and the shape memory structure is induced to expand or contract in a certain direction through the nano-composite structure, so as to realize dynamic stress self-compensation of the local interconnection interface.

[0014] S7: The change data of the nano-composite material impedance and capacitance before and after stress self-compensation are input into a health state intelligent evaluation model to online predict the residual life and failure probability of the interconnection structure.

[0015] S8: According to the output result of the health state evaluation model, it is automatically judged whether to issue a maintenance warning or upload the historical stress response data and compensation parameters to the process database to realize iterative optimization of subsequent multilayer printed circuit board manufacturing processes.

[0016] The multilayer interconnection method of the printed circuit board described in the application has the advantages that;

[0017] (1) The in-situ self-diagnosis capability of micro-zone thermal stress is significantly improved. By accurately embedding the nano-composite material with electrically conductive / strain coupling sensing function in the wall or perimeter of the PCB interconnection channel (such as via, blind hole, etc.), the spatial resolution and real-time monitoring of local thermal stress accumulation and gradient changes are realized. Compared with the existing scheme relying on post-failure analysis or large-scale strain gauges, the present application can realize multi-point distributed in-situ monitoring within 10 μm, with a sensitivity improvement of 2-3 orders of magnitude, greatly enhancing the dynamic early warning capability of stress anomalies.

[0018] (2) Self-adaptive thermal expansion compensation of multilayer heterogeneous structure, effectively improving the interconnection reliability. The embedded micro shape memory material / corrugated metal buffer structure is physically coupled with the nano-composite sensing layer, and when the system detects that the thermal stress exceeds the threshold value, the micro-heater is precisely activated to realize local expansion or contraction self-compensation of the cross-layer heterogeneous interface. Compared with the traditional static material matching or increased filling process, this scheme can adjust the interface micro-matching in real time according to the working condition, and the measured thermal cycle stress peak value is reduced by 20-30%, the interconnection structure integrity is improved to more than 99%, and the thermal failure probability is significantly reduced.

[0019] (3) Intelligent stress health criterion and life prediction significantly improve maintenance proactivity. Based on the dynamic acquisition and multi-dimensional modeling of in-situ parameters such as impedance and capacitance of nanocomposite materials, combined with feature engineering and adaptive threshold algorithms, stress accumulation judgment and compensation trigger determination under multi-channel and multi-material conditions are realized. Furthermore, equipped with an intelligent health status assessment model, it can perform online high-precision prediction of the remaining life and failure probability of interconnected structures, issuing maintenance warnings hundreds of thermal cycles in advance. Compared with conventional methods relying on periodic inspections or offline calculations, proactive maintenance efficiency is improved by more than 50%, greatly reducing the risk of major failures and production interruptions.

[0020] (4) The technical solution has strong process compatibility and industrial applicability. Each sub-step of the method achieves seamless integration with the existing PCB design-manufacturing-inspection-repair process through PCB original design file analysis, process data parsing, and standardized physical parameter modeling, without the need for large-scale production line changes. The fabrication process of sensing / compensation materials and microstructures is highly integrated and easy to automate in batches, achieving full coverage of mainstream HDI, thick board, and multi-layer PCB types, significantly expanding high-reliability application scenarios.

[0021] (5) Promote the closed-loop accumulation of long-term production data and realize the self-learning optimization of PCB process. All stress response, compensation action and health assessment data in the solution are automatically archived into the process database, providing a highly reliable data foundation for the company's subsequent process parameter tuning, material selection and failure modeling, and strongly supporting the continuous iteration of process quality and technological evolution. Attached Figure Description

[0022] Appendix Figure 1 This is the main flowchart of the multilayer interconnection method for printed circuit boards.

[0023] Appendix Figure 2 This is a sub-flowchart of the multilayer interconnection method for printed circuit boards.

[0024] Appendix Figure 3 This is another sub-flowchart of the multilayer interconnection method for printed circuit boards. Detailed Implementation

[0025] like Figures 1-3 As shown, the multilayer interconnection method for printed circuit boards described in this application includes:

[0026] like Figures 1-3 As shown, S1, for the interconnection channel areas between different layers of the multilayer printed circuit board, obtain the corresponding material parameters, expected coefficient of thermal expansion and thermal cycling condition labels, so as to form the differentiated configuration input for the subsequent distribution of nanocomposite sensing materials.

[0027] Further, in step S1,

[0028] S1.1: Automatic identification and region division processing of interlayer interconnection channel region in multi-layer printed circuit board original design file to obtain spatial distribution information of each interconnection channel region, providing interconnection channel region coordinate label for subsequent parameter collection and configuration.

[0029] With multi-layer printed circuit board (PCB) original design file as data input, the interlayer interconnection channel (including via, blind via, buried via and micro interconnection structure) is automatically identified and spatially divided.

[0030] Using computer-aided design (CAD) analysis method, the multi-layer stack structure of original Gerber, ODB++, IPC2581 and other PCB design files is formatted and parsed, realizing the extraction of geometric boundary data of circuit layer, signal via, power ground via and other types of interconnection channel region.

[0031] Further, through the region segmentation algorithm based on spatial grid index (parameters: layer number, aperture range, channel path, packaging type), the spatial distribution index set of interlayer interconnection channel of PCB multi-layer stack structure is constructed, realizing the independent identification of each interconnection channel region.

[0032] Further, through the morphological boundary extraction and connected domain analysis method (parameters: minimum / maximum feature size, boundary regularity coefficient), the spatial distribution index is optimized, and the spatial feature parameters such as centroid coordinates, polygon boundary and area of interconnection channel region are extracted.

[0033] Further, through the unique label (UID) generation and hierarchical structure coding method, the interconnection channel region coordinate label reflecting the PCB stack structure and having spatial positioning attribute is generated, realizing the linkage with subsequent material parameters and thermal physical modeling data.

[0034] Through the above algorithm processing method, the geometric figure and region structure information in the original design file is converted into structured interconnection channel region spatial distribution data and unique spatial coordinate label, realizing the provision of accurate spatial data input for subsequent parameter collection and configuration.

[0035] In an example, in an engineering application of a 12-layer high-density interconnection (HDI) PCB, the design file is in the format of IPC2581, containing 1600 blind holes and 520 laser-drilled micro-vias. An automatic script based on a CAD parsing engine is used for design file parsing, with parameters set as 12 layers, 0.15 mm minimum hole diameter, and 20 pm grid segmentation step. The spatial indexing of the area between layers is performed, and all 2120 interconnection channel areas are automatically identified. Using a boundary extraction algorithm, the polygon vertex coordinates and centroid (X, Y, Z) coordinates of each interconnection area are output, and each channel area is assigned a unique label (e.g., VIA_L5_TO_L7_0357). This processing chain ensures that the spatial distribution data corresponds to subsequent physical parameter acquisition and thermal expansion model configuration. In this example, the label extraction automation rate reaches 100%, and the spatial positioning error is not more than 10 pm, laying a data foundation for subsequent high-precision material modeling and differentiated sensing material distribution, and realizing seamless connection of the multi-layer interconnection channel spatial data chain.

[0036] S1.2: Based on the interconnection channel area coordinate label, call the process database and compare with the structure design BOM table to obtain and parse the material parameters (such as metal conductor type, composite substrate type, etc.) of each interconnection channel area between layers, forming a standardized material parameter data set.

[0037] Using the interconnection channel area spatial coordinate label obtained in the previous step as input, quantitative material parameter acquisition and standardized processing are carried out for all interconnection channel areas between layers of a multi-layer printed circuit board (PCB).

[0038] Using a process database retrieval method (parameters: spatial coordinate label, layer number, channel type), the structure material basic data of each interconnection channel area is queried, including metal conductor type (such as copper, nickel, gold), composite substrate type (such as FR-4, polyimide, BT resin), and other core physical properties.

[0039] Further, by comparing the structure design BOM (Bill of Materials) table and combining the area spatial indexing, a cross-table joint retrieval algorithm (parameters: channel area UID, BOM material code, material model, process batch) is implemented to obtain the material parameters, brand, source, layer sequence position, and process adaptability of each interconnection channel in the actual manufacturing process.

[0040] Further, an automatic material parameter parsing program is used to standardize the fields and convert the types of the collected database and BOM table data, and to unify heterogeneous data (such as English abbreviations, manufacturer-defined codes, and multiple source naming specifications) into a standardized format, including conductor material code, insulating substrate code, metal layer thickness, and filler material type.

[0041] Further, through redundant data deduplication and data integrity check processing (parameters: coordinate label uniqueness, material parameter integrity threshold), missing key parameters and multiple mapping data anomalies are removed to ensure that each interconnection channel region corresponds to a unique and complete material parameter record.

[0042] Further, attribute normalization methods are used to map and vectorize each material parameter, providing a high-consistency, high-computability standardized material parameter dataset for subsequent thermal property modeling.

[0043] Through the above process database combined with BOM table parameter retrieval, data standardization and integrity optimization methods, scattered original material information is converted into a standardized material parameter dataset that accurately corresponds to spatial coordinate labels, achieving efficient and batch material data collection for all interconnection channel regions of multi-layer PCBs, providing solid foundation data support for subsequent thermal expansion coefficient modeling and stress-sensitive material distribution configuration.

[0044] For example, for high-density interconnection (HDI) 12-layer PCB engineering application scenarios, the number of interconnection channel regions corresponding to spatial coordinate labels is 2120. Through automatic joint retrieval of parameter collection scripts and process databases, fields including conductor type (Cu, Au, Ni), substrate type (FR-4, PI), metal layer thickness (e.g., 18 μm), filler type (e.g., epoxy resin), channel manufacturing process batch, etc. are called for each region. Material parameters use unified dictionary encoding (e.g., conductor type Cu corresponds to encoding C1, FR-4 corresponds to encoding B2). Automatic verification eliminates 72 regions with missing parameters due to process changes, and finally outputs 2048 complete standardized material parameter vector records, covering all effective interconnection channel regions, achieving batch automation, normalized output, and zero redundancy problem for data collection. This standardized material parameter dataset is directly input into the thermal expansion finite element model, achieving one-to-one mapping with spatial coordinate labels, greatly improving the accuracy of thermal expansion anisotropy modeling and local stress-sensitive material configuration, and providing important foundation data support for high-reliability multi-layer HDI PCB research and development.

[0045] S1.3: Thermal property modeling of the standardized material parameter dataset, using finite element analysis or specialized thermal expansion model algorithms to calculate the expected thermal expansion coefficient information of each interconnection channel region under a typical environmental temperature range, generating thermal expansion coefficient prediction data for the multi-layer interconnection structure.

[0046] S1.4: In combination with user application conditions and historical process data, execute a thermal cycle condition label generation algorithm for each interconnection channel region, according to typical working periods, maximum / minimum working temperatures, heating-cooling rates, etc., to label the thermal cycle category and extreme condition risk factors of each region.

[0047] S1.5: The obtained interconnection channel region coordinate label, standardized material parameter data, thermal expansion coefficient prediction data, and thermal cycle working condition label are multi-dimensionally grouped and integrated, and a differentiated configuration input of the distribution and functional parameters of the nano-composite sensing material is generated through a structured input interface, thereby providing basic data for subsequent sensing layer customization and sensitivity matching.

[0048] As shown in Figures 1-3 S2, based on the obtained thermal expansion coefficient and working condition label, a nano-composite material structure containing conductive and strain sensing functions is prepared for each interconnection channel region in the multi-layer printed circuit board to realize differentiated sensitive response to different interlayer thermal stress and strain.

[0049] Further, in step S2,

[0050] S2.1: The thermal expansion coefficient, material parameter, and thermal cycle working condition label of each interconnection channel region of the multi-layer printed circuit board are subjected to aggregated data processing to form a differentiated design parameter set of the nano-composite material structure for each interconnection channel region, thereby realizing accurate classification of input parameters for interconnection channel regions with different physical constraint conditions.

[0051] The multi-source data of each interconnection channel region of the multi-layer printed circuit board (PCB) after spatial coordinate label recognition, standardized material parameter collection, thermal expansion coefficient modeling, and thermal cycle working condition label generation are input, and aggregated data processing is carried out for the configuration input of each interconnection channel region.

[0052] A multi-dimensional feature space aggregation method (parameters: spatial coordinate label, standardized material parameter, thermal expansion coefficient, and thermal cycle working condition label) is used to realize structured collection, field alignment, and data integrity verification of various data.

[0053] Further, through hierarchical data matching and normalization algorithm (parameters: material code, interlayer sequence number, thermal expansion and contraction coefficient interval, and working condition category), data splitting and aggregation under different physical constraint conditions are realized, and the first round of clustering is carried out for interconnection channel regions with the same or similar thermal expansion behavior and stress sensitivity requirements.

[0054] Further, through a multi-parameter classification algorithm based on clustering analysis (such as K-means and hierarchical clustering, parameters: Euclidean distance weight, thermal expansion coefficient sensitivity threshold, and working condition category priority), in-depth grouping is performed on the above aggregation results, and accurate attribution of each interconnection channel region in terms of functional parameters and physical behavior is realized.

[0055] Further, a parameter integration and structured configuration template generation method is adopted (parameters: clustering category, key physical parameter principal component, strain sensing target value), representative input parameter sets of each group of typical regions are extracted, and a design-specific nanocomposite material structure differentiation design parameter set is constructed.

[0056] Through the chain processing mode of the above multi-dimensional aggregation, hierarchical clustering and parameter template generation, the multi-source data of space, material, thermal physical properties and working conditions of each interconnection channel region in the multi-layer PCB are deeply integrated and converted into exclusive parameter inputs supporting subsequent personalized nanocomposite sensing material structure design, realizing accurate classification of configuration parameters for different physical constraint conditions.

[0057] For example, in the manufacturing process of a 12-layer high-density interconnection PCB, a total of 2048 effective interconnection channel regions are obtained, and multi-dimensional aggregation processing is performed on their spatial coordinate labels, standardized material parameters, thermal expansion coefficients and thermal cycle working condition labels. After parameter normalization, the region materials are divided into copper (C1), gold (C2), nickel (C3), FR-4 (B2), PI (B3) and other types, the thermal expansion coefficient interval is distributed in 13.5x10^-6 / K to 60.0x10^-6 / K, and the thermal cycle working condition label is recorded as three types of A level (mild cycle), B level (accelerated aging) and C level (extreme impact). Using the K-means algorithm, set the number of clustering centers k=5, based on the array Euclidean distance and the thermal expansion principal component contribution rate weighting, the automatic grouping of region function parameters is completed. For each clustering, five groups of representative parameter sets CJ1-CJ5 are obtained, and the nanocomposite material structure differentiation design parameter set corresponding to the spatial distribution and physical index output is output. For example, the CJ2 group corresponds to a thermal expansion coefficient of 28.7x10^-6 / K, a working condition label of B level, and a material combination of C1-B2, and outputs a nanocomposite material target ratio of graphene content 0.3wt%, and a high polymer matrix of polyimide thickness 1.2μm. Through the above automatic processing, high-precision classification and parameter template output of 2048 regions are realized, providing standardized and structured input for subsequent structure design and sensitivity calibration of region-specific nanocomposite sensing materials, and significantly improving the thermal expansion compatibility and self-diagnosis capability of multi-layer PCBs.

[0058] S2.2: Based on the differentiation design parameter set, interface microstructure modeling is performed on the target interconnection channel region, and the spatial distribution mode of the sensing material is optimized through nanoscale structure mechanics simulation algorithm to obtain a three-dimensional parameter template of the nanocomposite material structure mapping to each interconnection channel region.

[0059] S2.3: Using three-dimensional parameter templates to guide material selection and nanocomposite ratio, using sol-gel in-situ synthesis technology of multi-component polymer matrix and graphene / carbon nanotube conductive filler to grow or deposit a film in each interconnection channel region, to realize the preparation of region-specific conductive and strain sensing type nanocomposite thin layer.

[0060] S2.4: Based on precision micro-nano printing technology, structural pattern processing is carried out on the conductive and strain sensing type nanocomposite thin layer that has been formed into a film, to form a spatial distribution with both conductive network and stress sensing sensitive area, to ensure the matching of the subsequent physical parameter measurement channel and functional area distribution.

[0061] S2.5: Impedance / capacitance pre-calibration test is carried out on the structured nanocomposite thin layer, through multi-point parameter measurement in the domain and comparison with standard samples, to optimize the strain sensing sensitivity parameters, to make a scale reference for subsequent in-situ monitoring of nanocomposite physical parameters, and to complete the functional normalization of the nanocomposite structure in the interconnection channel region.

[0062] As shown in Figures 1-3 S3, the thermal stress response type micro shape memory structure or corrugated metal buffer structure unit is embedded in the interconnection channel region where the nanocomposite structure has been prepared, so that the nanocomposite structure and the micro shape memory structure form a coupled response unit for subsequent mechanical compensation.

[0063] Further, in step S3,

[0064] S3.1: Structural feature parameter extraction is carried out on the interconnection channel region where the nanocomposite structure has been formed, including through hole / blind hole geometric parameters, nanocomposite thickness and distribution uniformity parameters, to obtain the spatial configuration input data for microstructure embedding.

[0065] The interconnection channel region of the multi-layer printed circuit board where the structured nanocomposite thin layer has been completed is taken as the input object, and the input data includes the spatial geometric parameters of the through hole / blind hole, the thickness distribution parameters of the nanocomposite thin layer, and the thin layer uniformity evaluation index.

[0066] High-resolution 3D profile measurement technology (such as laser confocal scanning or white light interference method, with parameters set to scanning interval 0.1 μm, longitudinal resolution 10 nm) is used to realize spatial form sampling of the inner wall and end face of the through hole / blind hole in the interconnection channel region, and three-dimensional topographic point cloud data is output.

[0067] Further, by constructing a geometric feature calculation algorithm based on point cloud (parameters: hole diameter, longitudinal length, wall curvature, ellipticity), the key geometric parameters of the through hole / blind hole are analyzed, and the spatial configuration feature vector is automatically output.

[0068] Further, the cross-sectional multi-point in-situ thickness measurement method (such as non-destructive ultrasonic or focused ion beam sectioning combined with imaging, measurement point spacing <0.5 μm) is used to obtain the thickness data sequence of the nanocomposite thin layer in the full area range, and the thickness uniformity index is calculated by statistical operation formula:

[0069]

[0070] wherein T i is the actual measured thickness of the thin layer at the ith point, is the full area thickness average, and N is the total number of measurement points.

[0071] Further, by combining three-dimensional geometric features and thickness uniformity data, a spatial configuration parameter assembly algorithm (parameters: aperture, depth, wall curvature, thickness uniformity, distortion factor) is used to generate the spatial configuration input data set required for adaptive microstructure embedding. The spatial configuration input data set includes three-dimensional pore size, wall local curvature distribution, nanocomposite thin layer thickness distribution, and uniformity label of each interconnected channel region, etc.

[0072] Through the above high-precision structure parameter extraction and spatial data assembly chain, complete and standardized spatial configuration information is ensured for the precise and feasible arrangement of the thermal stress response type microstructure or the corrugated metal buffer structure unit, and high adaptability support is realized for the subsequent microstructure optimization design and embedding process.

[0073] For example, in a certain 12-layer high-density PCB sample, for the selected CA type interconnected channel region, 3D laser confocal method is used to scan the through hole at 0.1 μm intervals, and the average aperture is 200 μm, the wall curvature radius is 25 μm, and the channel depth is 1200 μm. The average thickness of the nanocomposite thin layer of the 1240 measurement points in the domain is 1.30 μm, the thickness standard deviation σ T = 0.05 μm, and the thickness uniformity index is better than ± 5%. Through multi-point statistical assembly, the spatial configuration input data includes three-dimensional topographic point cloud, spatial region label, and wall thickness matrix, which is used for subsequent finite element layout simulation and microstructure matching design. Before microstructure embedding, the spatial configuration data can be automatically docked with the simulation tool and micro-nano manufacturing equipment, realizing high-efficiency process closed loop. When abnormal wall curvature sections are detected, the system automatically adjusts the residence position of the subsequent corrugated metal unit, realizing the high integration of structure miniaturization and reliable compensation effect. The spatial configuration input data output in this step directly determines the accessibility, embedding compactness and stress compensation ability of the microstructure layout, and provides a solid spatial data foundation for the entire interlayer interconnection self-diagnosis-self-compensation link.

[0074] S3.2: Based on the structural feature parameters and the thermal stress-strain distribution model, the spatial layout scheme of the optimal micro shape memory structure or corrugated metal buffer structure is calculated by using the finite element analysis method to obtain the adaptive micro structure design parameters.

[0075] Based on the spatial configuration input data set obtained in the above sub-step, the input conditions include the three-dimensional geometric feature parameters of the interconnection channel region (including the through hole / blind hole spatial point cloud, wall curvature, aperture, depth, nanocomposite thin layer thickness matrix, uniformity parameters, etc.) and the established thermal stress-strain distribution model.

[0076] The spatial finite element analysis method (parameters: three-dimensional geometric discrete grid size 0.1-0.5 μm, boundary condition set to thermal-mechanical coupling, thermal cycle loading interval -40°C~+125°C, material elastic-plastic constitutive model) is used to realize high-resolution simulation of the thermal stress and thermal strain field of each interconnection channel region.

[0077] Further, by inputting a plurality of candidate microstructure layout parameters (parameters: corrugated metal buffer structure thickness, period, amplitude, shape memory structure area distribution, bending angle, pre-stress value) to the finite element simulation model through the control variable method, a mechanical response optimization algorithm (multi-objective optimization, objective function including minimization of maximum equivalent stress σ_von-Mises, uniform strain distribution, and wall adhesion stress less than the material allowable limit) is used to realize systematic screening of the mechanical matching and compensation ability of different microstructure spatial layouts.

[0078] Further, a coupled multi-physical field finite element algorithm (parameters: temperature-stress-phase change three-field coupling) is used to model the thermal excitation behavior of shape memory materials, and the effective compensation ability of the microstructure is derived through the following thermal deformation response formula:

[0079] ΔL = L0·α SM ·ΔT

[0080] Where ΔL is the length change of the microstructure under temperature control, L0 is the initial length, α SM is the thermal expansion coefficient of the shape memory material, and ΔT is the temperature change.

[0081] Further, for all simulation obtained layout schemes and material configurations, a multi-scheme normalized performance scoring algorithm (parameters: compensation efficiency, structure embedding adaptation rate, local stress reduction ratio, manufacturing scale tolerance) is used to compare the respective indicators such as maximum displacement response, stress concentration distribution, structure-medium interface bonding stability, etc., to realize optimal scheme screening.

[0082] The layout parameters of the micro shape memory structure or the corrugated metal buffer structure with the optimal performance selected from the simulation are calculated by a structural parameter back-calculation algorithm to obtain template input data for actual manufacturing and embedding, including specific spatial coordinates, geometric dimensions, material composition parameters and distribution density, to provide optimal design parameters with high adaptability for the next embedding process.

[0083] For example, in a high-density interconnection PCB board, the three-dimensional point cloud features of the via region (average hole diameter 200 pm, depth 1200 pm, wall curvature 25 pm) are input, the thermal cycle loading interval is -40°C to +125°C, the shape memory alloy used is NiTi, a SM = 30 x 10-6 / K, L0 = 100 pm, and the thermal strain simulation step is 10°C. Finite element optimization calculation shows that when the corrugated buffer structure thickness is 2 pm, the wave amplitude is 20 pm, the period is 40 pm, 20 groups are arranged equidistantly along the depth, the shape memory structure unit bending angle is 30°, the maximum equivalent stress decreases by 22%, the thermal deformation response AL can reach 0.255 pm, the local compressive stress peak is reduced by 19%, and the structure and nanocomposite wall adaptation rate is increased to more than 95%. This parameter set is finally selected as the embedding template input. After implementing the microstructure layout using the embedding parameters, the physical integrity retention rate of the compensation region is better than 99% after 1000 thermal shock cycles, effectively inhibiting the expansion of microcracks caused by local thermal stress accumulation under extreme temperature differences, and achieving the synchronous improvement of thermal expansion compatibility and mechanical robustness of the interconnection structure.

[0084] S3.3: According to the microstructure design parameters, use micro-nano manufacturing techniques (such as laser direct writing, micro-molding, etc.) to pre-fabricate micro shape memory structure units or corrugated metal buffer structure units in each specified region of the nanocomposite structure to obtain an in-situ embedded microstructure array.

[0085] Based on the optimal microstructure design parameter set generated through finite element optimization screening, input includes three-dimensional geometric coordinates of the specified interconnection channel region, wall space distribution, embedding thickness and predetermined layout point set.

[0086] Micro-nano manufacturing techniques are used for pre-fabrication of structure units, including laser direct writing (parameters: laser wavelength 355 nm, pulse width 15 ns, scanning step ≤0.5 pm, single energy density 1 J / cm 2 ), micro-molding (parameters: mold resolution 0.2 pm, molding temperature 70-120°C, pressure range 10-100 MPa), micro-area electrodeposition (parameters: current density 2-10 mA / cm 2, deposition time 5-30 s) and other multi-process synergy to achieve in-situ controllable forming of micro shape memory structures (such as NiTi sheet, shape memory polymer strip) or corrugated metal buffer structures (such as micro corrugated copper / nickel foil strip).

[0087] Further, through the automatic alignment laser path generation algorithm with spatial parameter template as input (parameters: alignment error <0.5 μm, path step and three-dimensional wall surface equidistant mapping cooperation), point or surface distribution in the specified area of nanocomposite structure for microstructure addressing and laser / molding patterning, ensures accurate distribution of each structure unit in the preferred mechanical response area.

[0088] Further, according to the material type and functional requirements, a step-by-step multi-layer micro-nano manufacturing mode is adopted: for shape memory materials, first form a primary structure film at the target point by micro-area electrodeposition or in-situ sputtering, and then obtain the specified micro morphology and size by pulse laser trimming / template micro-molding, for corrugated metal structure, two-way molding combined with plasma micro-welding process is adopted to enhance the bonding and thermal conductivity between the structure and the base wall.

[0089] Further, in view of the process deviation and actual topography change during embedding process, an in-situ confocal 3D microscopic monitoring and feedback control system (parameters: longitudinal resolution 10 nm, feedback delay <1 ms) is used to dynamically correct the microstructure preparation path, and abnormal points caused by structure residues, template defects, etc. are implemented for secondary local pre-fabrication or repair, to improve the integrity and consistency of the entire structure array.

[0090] Through the above chain processing mode of micro-nano manufacturing technology, spatial automatic alignment path generation, multi-step microstructure forming and feedback correction, the optimized design parameters are effectively converted into in-situ, distributed micro shape memory structure or corrugated metal buffer structure array embedded in the specified nanocomposite structure area, which significantly improves the adaptive thermal stress compensation ability and interface mechanical robustness of the subsequent interlayer interconnection structure.

[0091] Exemplarily, in the high-density 12-layer PCB product manufacturing, for the via area (average hole diameter 200 pm, depth 1200 pm, wall curvature 25 pm), 20 groups of micro shape memory alloy (NiTi) units are embedded, with a length of 100 pm, a thickness of 2 pm, and a quilted array distribution. Laser direct writing steps 0.5 pm, accurate positioning of each point and in-situ preparation of NiTi base strip, followed by pulse width adjustment and multiple laser reprocessing, so that the final structure bending angle reaches 30°, and the width fluctuation is less than ±0.2 pm. After embedding, use the online confocal microscopic system to feedback and calibrate, automatically adjust the detected 3 boundary offset units for the second time, and the final structure array integrity rate reaches 99.8%, and the wall surface is uniformly attached. After 50 thermal cycles, the micro structure unit exhibits an average deformation response AL = 0.255 pm in the temperature range of -40°C to 125°C, and the equivalent stress peak decreases by 22%, without micro cracks or bonding failure, meeting the engineering requirements of interlayer interconnection adaptive compensation under extreme working conditions, and significantly improving the interconnection reliability and thermal expansion compatibility.

[0092] S3.4: Surface energy coupling interface treatment (such as plasma surface activation or interface adhesive layer deposition) is performed on the nano-composite material structure embedded with the micro structure array, to realize the mechanical and functional coupling interface state of the nano-composite material structure and the micro shape memory structure.

[0093] S3.5: Based on the mechanical coupling interface state parameters, the interface bonding strength and micro deformation response ability of the coupling unit are evaluated by scanning electron microscopic imaging or micro area mechanics testing method, and the final embedded structure parameters meeting the demand of thermal stress self-compensation are obtained.

[0094] As shown in Figures 1-3 S4, the nano-composite material structure is real-time collected by external or in-plate sensing circuit for impedance, capacitance and other in-situ physical parameter data, and the thermal cycle and area label of the sampling point are associated, to realize the stress and strain multi-dimensional distribution modeling under multi-position and multi-material conditions.

[0095] Further, in step S4,

[0096] S4.1: The sampling sensing point layout parameters of the nano-composite material structure are set, and based on the spatial position and material difference of the interconnection channel area, a set of multi-position sampling sensing points is generated as the input basis for subsequent in-situ physical parameter collection.

[0097] For the interconnection channel area of the nano-composite material structure prepared in the multi-layer printed circuit board, the input data includes the spatial coordinate label, three-dimensional geometric parameters, wall thickness matrix and area material parameters of each interconnection channel area.

[0098] Adopting regional differential sampling layout algorithm (parameters: coordinate label set, interconnection channel space density p site , material sensitivity weight w mat ), realize preliminary sampling sensing point pre-selection based on interconnection channel space distribution and material heterogeneity.

[0099] Further, through the limited space optimization layout algorithm (parameters: sampling minimum distance d min , surface adaptation degree g s , thickness variation gradient ), realize multi-position sampling point fine positioning of three-dimensional channel surface and depth, and output the optimized multi-position sampling point set S site .

[0100] Further, by using material response sensitivity analysis method (parameters: nanocomposite conductive / sensing sensitivity factor a sens , local mechanical / thermal partition factor b zone ), response ability weighted screening is applied to the pre-selected sampling point set, and sampling points are preferentially selected in high response regions such as material layer interface, variable thickness area, embedded microstructure neighborhood, to supplement the integrity and representativeness of space sampling.

[0101] Further, through the multi-dimensional encoding algorithm of sampling point space label and regional material attribute, the final multi-position sampling sensing point set S site is structured and integrated with corresponding material label, thermal cycle condition label and other metadata information, and the complete multi-position, partitioned material sensitive sampling point master list is output.

[0102] Through the above multi-level space-material joint layout and label assembly processing method, the micro space, material distribution and working condition of complex heterogeneous interconnection channel region are effectively integrated into a multi-position sampling sensing point system, realizing high-resolution, full-coverage real-time monitoring of nanocomposite material in-situ physical parameters in multi-layer PCB.

[0103] For example, in a 12-layer high-density PCB board, the interconnection channel space coordinate label set is {CA1, CA2,..., CAN}, the regional average space density p site = 1 point / 50; μm^2, the conductive sensitivity a sens = 1200 S / m·ε -1 , the material partition label includes three types: copper-based wall area, polymer matrix reinforced area, and micro area corrugated metal embedded area. The regional surface adaptation degree threshold g s > 95%, the sampling point minimum distance d min= 15 pm. By differentiating the layout and material sensitivity weighting, 586 sampling points distributed in the curved wall, different levels of depth were finally selected, of which 201 sampling points covered the corrugated metal embedded area, 185 sampling points covered the polymer reinforced area, and the rest were uniformly distributed on the copper-based wall. Under specific thermal cycling conditions (temperature window -40°C to +125°C, cycle rate 0.5°C / min), multi-point and multi-zone physical response data were collected, meeting the needs of micro-zone transient response analysis and local anomaly positioning. The execution effect shows that the spatial coverage rate of the sampling point system is more than 98%, and the sampling ratio of the material sensitive domain and the key structure neighborhood is better than 90%, which lays a foundation for subsequent high-resolution real-time physical parameter acquisition and multi-dimensional stress state modeling.

[0104] S4.2: For the multi-position sampling sensor point set, the impedance parameters of the nanocomposite structure are collected in real time through the in-plate sensing circuit, and the capacitance parameter data are collected in parallel, so as to obtain a high-resolution in-situ physical parameter data set through a modular data acquisition process.

[0105] S4.3: For the high-resolution in-situ physical parameter data set, parameter space mapping processing is performed in combination with the spatial coordinate information of the sampling sensor points, so as to generate an impedance and capacitance parameter space distribution matrix with a spatial label.

[0106] S4.4: Based on the obtained parameter space distribution matrix, a preset thermal cycle condition label and a regional material label are introduced for each sampling sensor point, and a physical parameter-thermal cycle-regional sample three-tuple data structure is fused and constructed.

[0107] S4.5: For the physical parameter-thermal cycle-regional sample three-tuple data structure, a multi-element distribution statistical and correlation modeling algorithm is used for modeling processing, so as to obtain a multi-dimensional distribution model of in-situ stress and strain response under multi-position and multi-material conditions, thereby providing a modeling basis for subsequent key feature extraction and stress warning algorithm.

[0108] As shown in Figures 1-3 S5, based on the multi-dimensional stress distribution modeling result, key parameter features are extracted and input into an adaptive threshold judgment algorithm to determine whether there is thermal stress accumulation anomaly or whether the self-compensation trigger condition is reached in each interconnection channel region.

[0109] Further, in step S5,

[0110] S5.1: The original impedance and capacitance physical parameters output by the multi-dimensional stress distribution modeling are subjected to time sequence synchronization and signal preprocessing to remove measurement noise and abnormal points, thereby obtaining a high-fidelity in-situ physical parameter sequence of the multi-layer printed circuit board interconnection channel, which provides an input for feature engineering analysis.

[0111] S5.2: Based on the in-situ physical parameter sequence of the multi-layer printed circuit board interconnection channel, the statistical parameter and spectral feature parameter sensitive to thermal stress accumulation are extracted by feature engineering algorithm (such as principal component analysis PCA, Fourier spectrum coefficient extraction, etc.), and a high-dimensional feature parameter set is generated as the input of the subsequent adaptive threshold judgment algorithm.

[0112] S5.3: The high-dimensional feature parameter set is optimized by feature correlation analysis and dimension reduction algorithm (such as correlation coefficient screening, multivariate regression, etc.), and the key discriminant parameter set significantly related to thermal stress accumulation and interconnection structure health state is screened out, realizing effective redundancy compression of feature parameters and improving the adaptability and real-time performance of discriminant algorithm.

[0113] S5.4: The key discriminant parameter set screened out is input into the adaptive threshold judgment algorithm, and based on the historical thermal cycle condition label, regional label and material parameter data, the individualized discriminant threshold for different interconnection channels is generated through multi-threshold dynamic adjustment strategy, realizing intelligent dynamic discrimination of stress anomaly and compensation trigger condition.

[0114] S5.5: The adaptive threshold judgment result is output, and the discriminant signal of whether there is thermal stress accumulation anomaly or the self-compensation trigger condition in each interconnection channel region is input as the control signal of subsequent adaptive micro-heater driving and health state model updating, realizing the closed-loop driving basis of self-diagnosis and self-compensation of multi-layer printed circuit board interconnection structure.

[0115] As shown in Figures 1-3 S6, when the stress characteristic value of a certain interconnection channel region exceeds the set threshold, the control signal is output to activate the micro-heater of the corresponding region, and the directional expansion or contraction of the nano-composite material structure is induced to realize the dynamic stress self-compensation of the local interconnection interface.

[0116] Further, in step S6,

[0117] S6.1: Based on the discriminant result of the stress threshold judgment algorithm in the previous step, the stress characteristic value and its dynamic distribution of the specified interconnection channel region are judged by threshold condition, and the regional anomaly identification signal is generated as the input basis of the subsequent control signal output.

[0118] S6.2: For the generated regional anomaly identification signal, the preset regional mapping rule is called to bind the anomaly identification signal with the micro-heater hardware address and nano-composite material structure sensing circuit of the corresponding interconnection channel region, generate the thermal control execution control signal of the target region, and attach the regional thermal compensation parameters.

[0119] S6.3: Drive the micro-heater of the specified area with the thermal control execution control signal, and perform directional temperature control heating treatment on the nanocomposite structure through the energy injection mechanism, to ensure that the energy is released locally and completely absorbed by the nanocomposite structure in this area, and to realize local thermal excitation of the micro shape memory structure.

[0120] S6.4: After the nanocomposite structure senses the local thermal excitation, the micro shape memory structure coupled therewith is induced to produce directional expansion or contraction deformation response, and the local mechanical stress self-adaptive compensation is implemented on the interconnection interface through the mechanical stress transfer mechanism, so that the original thermal stress peak value is dissipated or redistributed.

[0121] S6.5: Real-time acquisition of nanocomposite structure impedance and capacitance change data before and after compensation, data closed-loop verification of micro shape memory structure response process based on physical quantity evolution characteristics, and obtaining of preliminary data of interconnection interface mechanical state after local stress self-compensation, to provide data basis for subsequent health state evaluation and system self-learning optimization.

[0122] As shown in Figures 1-3 S7, the nanocomposite impedance and capacitance change data before and after stress self-compensation are input into the health state intelligent evaluation model to predict the remaining life and failure probability of the interconnection structure.

[0123] Further, in step S7,

[0124] S7.1: Standardized pretreatment of nanocomposite impedance and capacitance change data collected before and after stress self-compensation, including outlier rejection, dynamic range normalization and timestamp synchronization processing, to obtain standardized physical parameter data set suitable for health state modeling analysis.

[0125] S7.2: Based on the standardized physical parameter data set, call the feature engineering algorithm to extract health evaluation core feature parameters reflecting the aging and stress distribution characteristics of the interlayer interconnection structure, such as impedance change rate, capacitance transient response characteristics and other key indicators, to provide high discriminant input factors for subsequent model evaluation.

[0126] S7.3: Input the health evaluation core feature parameters into the health state intelligent evaluation model trained in advance, combine the historical stress response trajectory and compensation action history, execute real-time inference and dynamic remaining life prediction of structure health indicators, and realize online calculation of failure probability of multi-layer interconnection structure driven by data.

[0127] The input is the nanocomposite impedance and capacitance change data after standardized pretreatment, the health evaluation core feature parameter set, and the historical stress response trajectory and self-compensation action history.

[0128] An interlayer interconnection structure health state intelligent evaluation model (such as integrated gradient boosting decision tree GBDT, deep neural network DNN, Bayesian health inference model, etc., parameters including: model structure, weight, historical training samples and working condition multi-label data) is adopted to realize the modeling analysis of the input feature parameters.

[0129] Further, by jointly encoding the historical stress response trajectory and the time sequence of the self-compensation action history, the input feature vector is expanded into a multi-dimensional dynamic sequence feature set, and the learning ability of the model to the complex compensation action effectiveness and structure evolution law is enhanced.

[0130] The model inference operator is used to perform performance regression and probability discrimination on the input parameter stream, calculate the health state index of the interconnected structure at the current time, including but not limited to: failure rate λ(t), health margin HI(t), dynamic remaining useful life RUL(t), etc., and combine the compensation action full history fine-tuning output.

[0131] The structure remaining life prediction value is calculated by the following typical physical-statistical formula:

[0132]

[0133] Where S(u|x) is the structure health survival probability function combined with historical working conditions and compensation measures, T f is the failure limit; the input feature x includes obstacle impedance, capacitance change rate and action history label.

[0134] Further, the failure probability estimation formula

[0135] P f (t)=1-S(t|x)

[0136] The failure probability is jointly determined to realize the active evaluation and early warning of the health state corresponding to different interlayer channels.

[0137] Through the health state index output, the dynamic damage evolution and compensation effect of the multi-layer interconnected structure in each compensation period are included in the data-driven prediction results, and the online estimation technical effect of the remaining useful life and the failure probability is realized.

[0138] Exemplarily, on a piece of 8-layer high-density interconnection PCB sample, for a blind hole channel with a diameter of 50 μm, the impedance change ΔZ = 2.7 Ω, the capacitance transient drop amplitude ΔC = 0.18 pF after compensation, and the number of micro-heating actions in the compensation history is 3. The health assessment model is set to use the LSTM time series network, the input parameters include the latest 10 times of historical impedance / capacitance measurement sequence and action label, after algorithm inference, the output current channel health margin HI = 0.85, the predicted remaining useful life RUL = 5400 h, and the failure probability P_f(t) = 0.11. The model automatically adjusts the output according to the dynamic feedback of the compensation action, improves the accuracy of the remaining useful life prediction and the robustness of the risk judgment. In actual online operation, through the dynamic update of the above indexes, the aging trend of the interconnection structure is reflected in time, and the operation and maintenance and quality decision are effectively supported.

[0139] S7.4: The remaining useful life estimation value and the failure probability output by the health state intelligent evaluation model are evaluated for reliability, the low confidence prediction results are corrected through the model adaptive confidence interval calibration and the historical decision playback mechanism, and the business reliability and anti-exception ability of the evaluation are improved.

[0140] S7.5: The finally generated interconnection structure health state evaluation results (including the remaining useful life interval, the failure probability distribution, the health trend curve, etc.) are bound and packaged with the interconnection channel region label, the material parameter, the compensation history and other metadata, and a structured health evaluation report is generated, which provides integrated input data for subsequent process decision and intelligent maintenance scheduling modules.

[0141] As shown in Figures 1-3 S8, according to the output results of the health state evaluation model, it is automatically determined whether to issue a maintenance warning or upload the historical stress response data and compensation parameters to the process database to realize the iterative optimization of the subsequent multilayer printed circuit board manufacturing process.

[0142] Further, in step S8,

[0143] S8.1: The interconnection structure health state prediction parameters (including the remaining useful life, the failure probability, the stress buffering remaining capacity, etc.) output by the health state intelligent evaluation model are automatically analyzed to identify whether the maintenance warning condition is met, and a maintenance warning judgment label is formed.

[0144] S8.2: Based on the maintenance warning judgment label, the current running state of the interconnection structure is managed by using a decision control algorithm, if it is determined that the maintenance threshold is reached, a maintenance work order is automatically generated and a process disposal suggestion is output, and intelligent closed-loop regulation and control of the production process is realized.

[0145] S8.3: Structured encapsulation of multi-dimensional operation data such as maintenance warning judgment label, interconnection structure health state prediction parameter, historical stress response data, and compensation control action parameter, etc. to form a process database standard data package.

[0146] The input data includes multi-dimensional operation data such as maintenance warning judgment label, interconnection structure health state prediction parameter, historical stress response data, and compensation control action parameter, etc. which have been output by the upstream step and standardized.

[0147] The structured metadata encapsulation method (parameters: label data type, physical parameter vector, time stamp, spatial coordinate, interconnection channel unique identifier, etc.) is used to realize the object integration of multi-dimensional operation data. Further, through the data field hierarchical normalization processing algorithm (parameters: high-dimensional feature parameter, hierarchical normalization template), the maintenance warning label, health state parameter, stress history, and compensation action parameter are filled into the corresponding field area in the process database standard data package template according to the preset data level and field format, respectively, to form a complete data structure body.

[0148] Further, through the data consistency verification algorithm (parameters: field legality rule, multi-source data time sequence consistency standard), the consistency of each field content and the associated relationship in the assembled data structure body is verified, the redundant field cleaning and abnormal data elimination are realized, and the logical correctness and business consistency between the parameters and indication markers in the data package are ensured.

[0149] Further, through the time and space index generation algorithm (parameters: collection time stamp, interconnection channel space label, process batch number), a unique index code is assigned to each standard data package to realize the basic index identification allocation for subsequent big data archiving and fast retrieval.

[0150] The data compression and serialization technology (parameters: high-efficiency binary encoding format, compression depth, business unpacking and decoding protocol) is used to serialize the output of the process database standard data package in the optimal storage structure, which improves the storage compatibility and large-scale parallel writing efficiency of the data package.

[0151] Through the above standardized standard data package processing flow, the multi-dimensional operation data of the previous step is converted into a standardized data set that can be directly archived in the process database, realizing the whole-process tracing and knowledge accumulation of interconnection structure health data.

[0152] Exemplarily, in a high-density multi-layer printed circuit board mass production scenario, for a product with batch number PCB20240612-01, the total number of interconnection channel regions is 256, each channel is provided with a unique spatial coordinate label (such as [L3-VIA-128]), and the associated historical stress response data is 10,000 (physical parameters: impedance, capacitance, time resolution 10 seconds), the maintenance warning judgment labels include three types of “warning”, “no maintenance” and “emergency”, and the health state prediction parameters include residual life (unit: hour, numerical range 1000-15,000h), failure probability (0-1), health level (1-10) and the like. The system performs structured packaging on the data of each interconnection channel, first according to the parameter template, the maintenance label, the core numerical parameter, the time series data and the compensation action record are hierarchically archived in the Layer-1 field (such as health evaluation label), Layer-2 field (detailed physical process parameters), Layer-3 field (control action history). Subsequently, a unique index (such as "PCB20240612-01_L3-VIA-128_20240613T120000") is generated using the time stamp and spatial label, and the final data packet is generated through binary serialization and 5 times compression rate data compression processing. The size of a single packet after compression is about 1.2MB. Check part of the data packets, find that the error label field accounts for less than 0.01%, and after cleaning, the whole passes the consistency audit. Finally, the standard data packet batch is pushed to the process database, realizing the structured archiving of all interconnection channel monitoring and compensation records, supporting subsequent associated analysis and intelligent optimization application.

[0153] S8.4: Perform integrated upload processing on the process database standard data packet, ensure that the stress response data and compensation control action parameters are sequentially archived according to the time sequence and spatial coordinate label, and improve the data retrieval and subsequent big data analysis efficiency.

[0154] S8.5: Based on the archived historical stress response data, compensation control action parameters and health state prediction parameters, periodically call the process optimization algorithm to perform multi-factor correlation modeling on the key manufacturing parameters of the multi-layer printed circuit board, and output self-optimization process configuration suggestions for future design stage and production process precision optimization.

[0155] The above only describes the preferred embodiments of one or more embodiments of the present specification, and does not limit one or more embodiments of the present specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present specification shall be included in the protection scope of one or more embodiments of the present specification.

Claims

1. A method for multilayer interconnection of printed circuit boards, characterized in that, include: S1: For the interconnection channel areas between different layers of a multilayer printed circuit board, obtain the corresponding material parameters, expected coefficient of thermal expansion, and thermal cycling condition labels; S2: Based on the obtained thermal expansion coefficient and thermal cycling condition label, nanocomposite structures with conductivity and strain sensing functions are prepared for each interconnect channel region in the multilayer printed circuit board. S3: Thermal stress-responsive micro-shape memory structure or corrugated metal buffer structure unit is embedded in the interconnected channel of the prepared nanocomposite structure to form a coupled response unit for subsequent mechanical compensation; S4: Basic Coupled Response Unit, which collects in-situ physical parameter data of impedance and capacitance in nanocomposite structures in real time through external or in-plate sensing circuits, and is used for multidimensional distribution modeling of stress and strain under multi-location and multi-material conditions. S5: Based on the multidimensional distribution modeling results, extract key parameter features and input them into the adaptive threshold judgment algorithm to determine whether there is thermal stress accumulation anomaly or whether the self-compensation triggering condition is reached in each interconnection channel area. S6: According to the adaptive threshold determination algorithm, when the determination result shows that the stress characteristic value of a certain interconnect channel region exceeds the set threshold, the output control signal activates the micro heater of the corresponding region. The shape memory structure is induced to expand or contract in a directional manner through the nanocomposite material structure, so that the dynamic stress of the local interconnect interface is self-compensated. S7: Input the impedance and capacitance change data of nanocomposite materials before and after stress self-compensation into the intelligent health status assessment model; S8: Based on the output of the health status assessment model, automatically determine whether to issue a maintenance warning or upload historical stress response data and compensation parameters to the process database.

2. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The thermal expansion coefficient and thermal cycling condition labels specifically include: Automatic identification and region division of interlayer interconnection channel regions in the original design files of multilayer printed circuit boards are performed to obtain spatial distribution information of each interconnection channel region, which is used to provide coordinate labels for interconnection channel regions for subsequent parameter acquisition and configuration. Based on the coordinate labels of the interconnection channel area, the process database is called and the structural design BOM is compared to obtain and parse the material parameters of the interconnection channel area between each layer, forming a standardized material parameter dataset. Thermal property modeling is performed on the standardized material parameter dataset. Using finite element analysis or a dedicated thermal expansion model algorithm, the expected thermal expansion coefficient of each interconnect channel region is calculated under typical ambient temperature range, generating predicted thermal expansion coefficient data for multi-layer interconnect structures. Based on user application conditions and historical process data, a thermal cycling condition label generation algorithm is executed for each interconnected channel area to label the thermal cycling category and extreme operating condition risk factors of each area. Based on the thermal cycling category and extreme operating conditions, the obtained interconnected channel area coordinate labels, standardized material parameter data, thermal expansion coefficient prediction data, and thermal cycling condition labels are multidimensionally grouped and integrated. Differentiated configuration inputs for the distribution and functional parameters of nanocomposite sensing materials are generated through a structured input interface.

3. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The material parameters are standardized vector data including the type of metal conductor, the type of composite substrate, the thickness of the metal layer, and the type of filler material. They are obtained through cross-referencing the process database and the design BOM, data normalization, and redundancy removal.

4. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The nanocomposite material structure is designed with regional differentiation, and the conductive filler is graphene or carbon nanotubes. It is synthesized in situ through sol-gel and processed into a film by micro-nano printing, and then impedance / capacitance is pre-calibrated.

5. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The micro-shape memory structure or corrugated metal buffer structure is a NiTi alloy sheet or a copper or nickel corrugated foil strip, which is arrayed in a designated area of ​​the nanocomposite structure and in-situ embedded using laser direct writing, micro molding, and micro-area electrodeposition techniques, and the interface energy coupling process is completed.

6. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The nanocomposite material structure specifically includes: The thermal expansion coefficient, material parameters, and thermal cycling condition labels of each interconnect channel region of a multilayer printed circuit board are aggregated and processed to form a set of differentiated design parameters for nanocomposite material structures for each interconnect channel region. Based on a differentiated design parameter set, the interface microstructure of the target interconnect channel region is modeled, and the spatial distribution pattern of the sensing material is optimized by a nanoscale structural mechanics simulation algorithm to obtain a three-dimensional parameter template of the nanocomposite structure mapped to each interconnect channel region. Using three-dimensional parameter templates to guide material selection and nanocomposite formulation, a sol-gel in-situ synthesis technique is employed to grow or deposit films in each interconnected channel region using a multi-component polymer matrix and graphene or carbon nanotube conductive filler. For the already formed conductive and strain-sensing nanocomposite thin film, structured pattern processing is carried out based on precision micro-nano printing technology to form a spatial distribution that combines conductive network and stress-sensing sensitive area; Impedance or capacitance pre-calibration tests were performed on the structured nanocomposite thin layer. By comparing the multi-point parameter measurements within the domain with standard samples, the strain sensing sensitivity parameters were optimized and used as a scaling benchmark for subsequent in-situ monitoring of the physical parameters of nanocomposite materials.

7. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The coupling response unit specifically includes: Structural feature parameters are extracted from the interconnected channel region of the completed nanocomposite structure, including the geometric parameters of through holes or blind holes, the thickness and distribution uniformity parameters of the nanocomposite, in order to obtain spatial configuration input data for microstructure embedding. Based on structural characteristic parameters and thermal stress-strain distribution models, the finite element analysis method is used to calculate the optimal spatial layout scheme of micro-shape memory structure or corrugated metal buffer structure to obtain adaptive micro-structure design parameters. According to the microstructure design parameters, micro- and nano-fabrication technology is used to prefabricate micro-shape memory structure units or corrugated metal buffer structure units in a specified area of ​​each nanocomposite structure to obtain an in-situ embedded microstructure array. Surface energy coupling interface treatment was applied to nanocomposite structures with embedded microstructure arrays.

8. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The multidimensional distribution modeling specifically includes: The layout parameters of sampling sensor points are set for the nanocomposite structure. Based on the spatial location and material differences of the interconnected channel region, a set of multi-location sampling sensor points is generated to serve as the input basis for subsequent in-situ physical parameter acquisition. For a multi-location sampling sensor set, impedance parameters and capacitance parameters of the nanocomposite structure are acquired in real time through the in-board sensing circuit, and high-resolution in-situ physical parameter datasets are obtained through a modular data acquisition process. For high-resolution in-situ physical parameter datasets, parameter space mapping processing is performed in conjunction with the spatial coordinate information of the sampled sensor points to generate spatial distribution matrices of impedance and capacitance parameters with spatial labels. Based on the obtained parameter spatial distribution matrix, a preset thermal cycling condition label and a regional material label are simultaneously introduced for each sampling sensing point, and a physical parameter-thermal cycling-region sample triplet data structure is constructed. For the physical parameter-thermal cycle-regional sample triplet data structure, a multivariate distribution statistical and correlation modeling algorithm is used for modeling to obtain a multidimensional distribution model of in-situ stress-strain response under multiple location and material conditions.

9. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The physical parameters collected by the real-time sensing circuit include impedance and capacitance data. The layout of the multi-parameter sampling points is optimized and bound to each thermal cycle and material label.

10. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The physical data changes in the dynamic compensation process are collected every 10-300 seconds, and the health status assessment model can be dynamically updated.

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