Layout simulation method and layout simulation apparatus

Abstract

A layout simulation method and a layout simulation apparatus are disclosed. The layout simulation method includes: providing a first rule model, which includes several different first devices, each first device including several different types of first device structures; obtaining several inspection models corresponding to each first device based on the first rule model; providing a process design kit, which includes several different second devices; obtaining to-be-inspected information from the process design kit through an extraction module, the to-be-inspected information including all second devices; using the first rule model, obtaining several different types of second device structures for each second device from the to-be-inspected information; and determining whether the different types of second device structures in each second device overlap in position based on the inspection models. This invention improves the accuracy of layout simulation extraction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to layout simulation methods and apparatus. Background Technology

[0002] Accurate post-layout simulation extraction is a crucial step in integrated circuit design. Within the Process Design Kit (PDK), Layout-Schematic Comparison (LVS), Parasitic Parameter Extraction (PEX), and Device Model (SPICE Model) are important components of post-layout simulation verification.

[0003] The connection relationships of different device structures are defined in the Layout Schematic Comparison (LVS). Ensuring that the positions of each device structure do not overlap is the key to accurate parasitic parameter extraction (PEX).

[0004] However, in the existing technology, there is no effective method to ensure that the structural positions of each device do not overlap, which leads to repeated extraction in the post-simulation and greatly affects the simulation accuracy. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a layout simulation method and a layout simulation device. By checking the model, it ensures that the structures of devices from the same conductor do not overlap, thereby improving the accuracy of post-layout simulation extraction.

[0006] To address the aforementioned technical problems, the present invention provides a layout simulation method, comprising: providing a first rule model, the first rule model including several different first devices, each first device including several different types of first device structures, each type of first device structure having first structural information; obtaining several inspection models corresponding to each first device according to the first rule model, each inspection model including several groups of devices and inspection condition information corresponding to each group of devices, each group of devices including two different types of first device structures in the first device corresponding to the inspection model and the first structural information of the first device structures; providing a process design kit, the process design kit including several different second devices, each second device having device information; obtaining information to be detected in the process design kit through an extraction module, the information to be detected including all second devices, each second device corresponding one-to-one with each first device; using the first rule model, obtaining several different types of second device structures of each second device in the information to be detected, and each type of second device structure having second structural information; determining whether the different types of second device structures in each second device overlap in position according to the inspection model.

[0007] Optionally, each of the first structural information includes: first device structure position information corresponding to the first device structure, several different types of first device layers, a first graphic relationship between the first device structure and the several different types of first device layers, several first device layer position information corresponding to the several different types of first device layers, and positional relationship between the first device structure position information and the several first device layer position information.

[0008] Optionally, the first graphical relationship includes: the types of first device layers included in each first device structure, and the types of first device layers not included in each first device structure.

[0009] Optionally, the first device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0010] Optionally, the device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

[0011] Optionally, each of the second structural information includes: the location information of the second device structure corresponding to the second device structure, several different types of second device layers, and the second graphic relationship between the second device structure and the several different types of second device layers. Each of the second device structures corresponds one-to-one with each of the first device structures, each of the second structural information corresponds one-to-one with each of the first structural information, and the second graphic relationship of each of the second device structures is the same as the first graphic relationship of each of the first device structures corresponding to each of the second device structures.

[0012] Optionally, the method for obtaining several different types of second device structures of each second device includes: obtaining each first device corresponding to each second device based on several different types of second device layers of each second device in the information to be detected; obtaining several different types of first device layers corresponding to several different types of second device layers in each second device; and obtaining several different types of second device structures of each second device based on the first graphic relationship of the corresponding several different types of first device layers.

[0013] Optionally, the second graphical relationship includes: the types of second device layers included in each of the second device structures, and the types of second device layers not included in each of the second device structures.

[0014] Optionally, the second device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0015] Optionally, it further includes: after determining whether the second device structures of different types in each second device overlap in position according to the inspection model, when the second device structures of different types in the second device overlap in position, modifying the first structure information of the first device structure corresponding to the overlapping second device structure in the first rule model.

[0016] Optionally, it also includes: after determining whether the different types of second device structures in each second device overlap in position according to the inspection model, the overlap check is completed when there is no positional overlap in each type of second device structure in each second device.

[0017] Optionally, the first device includes one or more of the following: an N-type MOSFET, a P-type MOSFET, an NPN transistor, and an NPN transistor.

[0018] Optionally, the second device includes one or more of the following: an N-type MOSFET, a P-type MOSFET, an NPN transistor, and an NPN transistor.

[0019] Optionally, the first device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0020] Optionally, the second device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0021] Accordingly, the technical solution of the present invention provides a layout simulation device, the layout simulation device comprising: a first rule model, the first rule model including a plurality of different first devices, each first device including a plurality of different types of first device structures, each type of first device structure of each first device having first structural information; an inspection module, configured to obtain a plurality of inspection models corresponding to each first device according to the first rule model, each inspection model including a plurality of device groups and inspection condition information corresponding to each device group, each device group including two different types of first device structures in the first device corresponding to the inspection model and the first structural information of the first device structures; a process design kit, the process design kit including a plurality of different second devices, each second device having device information; an extraction module, configured to obtain information to be detected from the process design kit, the information to be detected including all second devices, each second device corresponding one-to-one with each first device; a structure module, configured to use the first rule model to obtain a plurality of different types of second device structures of each second device from the information to be detected, and each type of second device structure having second structural information; and a judgment module, configured to judge whether the different types of second device structures in each second device overlap in position according to the inspection model.

[0022] Optionally, each of the first structural information includes: first device structure position information corresponding to the first device structure, several different types of first device layers, a first graphic relationship between the first device structure and the several different types of first device layers, several first device layer position information corresponding to the several different types of first device layers, and positional relationship between the first device structure position information and the several first device layer position information.

[0023] Optionally, the first graphical relationship includes: the types of first device layers included in each first device structure, and the types of first device layers not included in each first device structure.

[0024] Optionally, the first device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0025] Optionally, the device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

[0026] Optionally, each of the second structural information includes: the location information of the second device structure corresponding to the second device structure, several different types of second device layers, and the second graphic relationship between the second device structure and the several different types of second device layers. Each of the second device structures corresponds one-to-one with each of the first device structures, each of the second structural information corresponds one-to-one with each of the first structural information, and the second graphic relationship of each of the second device structures is the same as the first graphic relationship of each of the first device structures corresponding to each of the second device structures.

[0027] Optionally, the method for obtaining several different types of second device structures of each second device includes: obtaining each first device corresponding to each second device based on several different types of second device layers of each second device in the information to be detected; obtaining several different types of first device layers corresponding to several different types of second device layers in each second device; and obtaining several different types of second device structures of each second device based on the first graphic relationship of the corresponding several different types of first device layers.

[0028] Optionally, the second graphical relationship includes: the types of second device layers included in each of the second device structures, and the types of second device layers not included in each of the second device structures.

[0029] Optionally, the second device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0030] Optionally, it also includes: a modification module, used to modify the first structure information of the first device structure corresponding to the overlapping second device structure in the first rule model after the judgment module, when there is positional overlap between different types of second device structures in the second device.

[0031] Optionally, it also includes: a termination module, used after the judgment module, when there is no positional overlap in each type of second device structure in each second device, the overlap check is completed.

[0032] Optionally, the first device includes one or more of the following: an N-type MOSFET, a P-type MOSFET, an NPN transistor, and an NPN transistor.

[0033] Optionally, the second device includes one or more of the following: an N-type MOSFET, a P-type MOSFET, an NPN transistor, and an NPN transistor.

[0034] Optionally, the first device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0035] Optionally, the second device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] In the layout simulation method provided by this invention, an extraction module obtains detection information from the process design kit. This detection information includes all second devices, each with device information. A first rule model is used to obtain several different types of second device structures for each second device from the detection information. Then, a check model is used to determine whether the different types of second device structures in each second device overlap. By using the check model to determine whether the different types of second device structures in all the second devices of the process design kit overlap, the first rule model can be modified based on the overlap of the second device structures, thereby ensuring that the positions of all types of second device structures in all the second devices of the process design kit do not overlap, thus improving the accuracy of post-layout simulation extraction.

[0038] Accordingly, in the layout simulation device provided by the present invention, an extraction module obtains the information to be detected from the process design kit. The information to be detected includes all the second devices, each of which has device information. A structure module obtains several different types of second device structures for each second device from the information to be detected. A judgment module determines whether the different types of second device structures in each second device overlap. By using the inspection model to determine whether the different types of second device structures in all the second devices of the process design kit overlap, the first rule model can be modified by the modification module based on the overlap of the second device structures. This ensures that the positions of all types of second device structures in all the second devices of the process design kit do not overlap, thereby improving the accuracy of post-layout simulation extraction. Attached Figure Description

[0039] Figure 1 This is a flowchart illustrating the layout simulation method in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the layout simulation device in an embodiment of the present invention. Detailed Implementation

[0041] As described in the background section, there is no effective method in the prior art to ensure that the structural positions of each device do not overlap, which leads to repeated extraction in the post-simulation and greatly affects the simulation accuracy.

[0042] To address the aforementioned technical problem, the present invention provides a layout simulation method and a layout simulation device. By checking the model, it ultimately ensures that the structural positions of all types of second devices in the process design kit do not overlap, thereby improving the accuracy of post-layout simulation extraction.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figure 1 This is a flowchart illustrating the layout simulation method in an embodiment of the present invention, including:

[0045] Step S100: Provide a first rule model, the first rule model includes several different first devices, each first device includes several different types of first device structures, and each type of first device structure of each first device has first structure information;

[0046] Step S200: According to the first rule model, obtain several inspection models corresponding to each first device. Each inspection model includes several device groups and inspection condition information corresponding to each device group. Each device group includes two different first device structures in the first device corresponding to the inspection model and the first structure information of the first device structure.

[0047] Step S300: Provide a process design kit, the process design kit including several different second devices, each second device having device information;

[0048] Step S400: Obtain the information to be tested from the process design kit through the extraction module. The information to be tested includes all the second devices, and each second device corresponds one-to-one with each first device.

[0049] Step S500: Using the first rule model, obtain several different types of second device structures for each second device from the information to be detected, and each type of second device structure has second structure information;

[0050] Step S600: Based on the inspection model, determine whether the structures of different types of second devices in each second device overlap in position;

[0051] Step S700: When the condition in step S600 is met, modify the first structure information of the first device structure corresponding to the overlapping second device structure in the second device in the first rule model.

[0052] Step S800: If the condition in step S600 is not met, the overlap check is complete.

[0053] The following is a detailed explanation.

[0054] Execute step S100 to provide a first rule model, the first rule model including a number of different first devices, each first device including a number of different types of first device structures, and each type of first device structure of each first device having first structure information.

[0055] In this embodiment, each of the first structural information includes: first device structure position information corresponding to the first device structure, several different types of first device layers, a first graphic relationship between the first device structure and the several different types of first device layers, several first device layer position information corresponding to the several different types of first device layers, and positional relationship between the first device structure position information and the several first device layer position information.

[0056] In this embodiment, the first device includes one or more of the following: an N-type MOS transistor, a P-type MOS transistor, an NPN transistor, and an NPN transistor.

[0057] In this embodiment, the first device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0058] In this embodiment, the first device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0059] In this embodiment, the first graphical relationship includes: the types of first device layers included in each first device structure, and the types of first device layers not included in each first device structure.

[0060] The first rule model defines the categories of first device structures included in each first device, and, through the first graphical relationship, defines the types of first device layers included and excluded by each category of first device structures in each first device. During layout simulation, parasitic parameter extraction (PEX) needs to be performed according to the definitions in the first rule model, and then layout simulation is performed based on the extracted parasitic parameters.

[0061] In step S200, based on the first rule model, several inspection models corresponding to each of the first devices are obtained. Each inspection model includes several groups of devices and inspection condition information corresponding to each group of devices. Each group of devices includes two different types of first device structures in the first device corresponding to the inspection model and the first structure information of the first device structure.

[0062] The function of the inspection condition information is to determine whether the positions of two different types of first device structures in the device group overlap based on the position information of the first device structure corresponding to the first device structure in the first device information.

[0063] In this embodiment, the inspection model is used to check whether there is any overlap in the various types of first device structures in the first device corresponding to the inspection model.

[0064] Step S300 is performed to provide a process design kit, which includes several different second devices, each of which has device information.

[0065] In this embodiment, the device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

[0066] In this embodiment, the process design kit refers to the Process Design Kit (PDK) kit in integrated circuit design, which is used to provide the design layout of the second device.

[0067] In this embodiment, the second device includes one or more of the following: an N-type MOS transistor, a P-type MOS transistor, an NPN transistor, and an NPN transistor.

[0068] In this embodiment, the second device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0069] In this embodiment, the second device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

[0070] In step S400, the information to be tested is obtained from the process design kit through the extraction module. The information to be tested includes all the second devices, and each second device corresponds one-to-one with each first device.

[0071] It should be noted that all the second devices extracted by the extraction module include the device information of the second devices, and each device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

[0072] In step S500, the first rule model is used to obtain several different types of second device structures for each second device from the information to be detected, and each type of second device structure has second structure information.

[0073] In this embodiment, each of the second structural information includes: the location information of the second device structure corresponding to the second device structure, several different types of second device layers, and the second graphic relationship between the second device structure and the several different types of second device layers. Each of the second device structures corresponds one-to-one with each of the first device structures, each of the second structural information corresponds one-to-one with each of the first structural information, and the second graphic relationship of each of the second device structures is the same as the first graphic relationship of each of the first device structures corresponding to each of the second device structures.

[0074] In this embodiment, the method for obtaining several different types of second device structures of each second device includes: obtaining each first device corresponding to each second device and obtaining several different types of first device layers corresponding to several different types of second device layers of each second device based on several different types of second device layers of each second device in the information to be detected; then, obtaining several different types of second device structures of each second device based on the first graphical relationship between the first device structure of each first device and the several different types of first device layers in the first rule model.

[0075] In this embodiment, the second graphical relationship includes: the types of second device layers included in each second device structure, and the types of second device layers not included in each second device structure.

[0076] Step S600 is executed, and based on the inspection model, it is determined whether the structures of different types of the second device overlap in position.

[0077] When different types of second device structures in the second device have overlapping positions, step S700 is executed to modify the first structure information of the first device structure corresponding to the overlapping second device structure in the first rule model.

[0078] When there is no positional overlap in each type of second device structure in each second device, step S800 is executed, and the overlap check is completed.

[0079] In this embodiment, steps S100 to S700 are a cyclical process. The inspection model determines whether there is overlap in the various types of second device structures within each second device. If there is overlap, the first structure information in the first device structure corresponding to the overlapping second device structure needs to be modified in the first rule model. This means re-determining the types of first device layers included and excluded from the first device structure within the first device. By continuously modifying the first rule model, it is ensured that there are no overlapping second device structures in each second device, thereby ensuring that the parasitic parameters extracted subsequently based on the first rule model are more accurate and improving the layout simulation accuracy.

[0080] Figure 2 This is a schematic diagram of the layout simulation device in an embodiment of the present invention.

[0081] Accordingly, embodiments of the present invention also provide a layout simulation device. Please refer to [link / reference needed] for details. Figure 2 The layout simulation device includes:

[0082] First rule model 200, the first rule model includes several different first devices, each first device includes several different types of first device structures, and each type of first device structure of each first device has first structure information;

[0083] Inspection module 210 is used to obtain several inspection models corresponding to each of the first devices according to the first rule model. Each inspection model includes several groups of devices and inspection condition information corresponding to each group of devices. Each group of devices includes two different types of first device structures in the first device corresponding to the inspection model and the first structure information of the first device structure.

[0084] Process design kit 220, the process design kit including several different second devices, each second device having device information;

[0085] The extraction module 230 obtains the information to be tested from the process design kit. The information to be tested includes all the second devices, and each second device corresponds to each first device.

[0086] The structure module 240 is used to obtain several different types of second device structures for each second device from the information to be detected using the first rule model, and each type of second device structure has second structure information.

[0087] The judgment module 250 is used to determine whether the structures of different types of the second device overlap in position.

[0088] Modification module 260 is used, after the judgment module, to modify the first structure information of the first device structure corresponding to the overlapping second device structure in the first rule model when there is positional overlap between different types of second device structures in the second device.

[0089] End module 270 is used after the judgment module to complete the overlap check when there is no positional overlap in each type of second device structure in each second device.

[0090] In this embodiment, each of the first structural information includes: first device structure position information corresponding to the first device structure, several different types of first device layers, a first graphic relationship between the first device structure and the several different types of first device layers, several first device layer position information corresponding to the several different types of first device layers, and positional relationship between the first device structure position information and the several first device layer position information.

[0091] In this embodiment, the first graphical relationship includes: the types of first device layers included in each first device structure, and the types of first device layers not included in each first device structure.

[0092] In this embodiment, the device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

[0093] In this embodiment, each of the second structural information includes: the location information of the second device structure corresponding to the second device structure, several different types of second device layers, and the second graphic relationship between the second device structure and the several different types of second device layers. Each of the second device structures corresponds one-to-one with each of the first device structures, each of the second structural information corresponds one-to-one with each of the first structural information, and the second graphic relationship of each of the second device structures is the same as the first graphic relationship of each of the first device structures corresponding to each of the second device structures.

[0094] In this embodiment, the method for obtaining several different types of second device structures of each second device includes: obtaining each first device corresponding to each second device and obtaining several different types of first device layers corresponding to several different types of second device layers of each second device based on several different types of second device layers of each second device in the information to be detected; then, obtaining several different types of second device structures of each second device based on the first graphical relationship between the first device structure of each first device and the several different types of first device layers in the first rule model.

[0095] In this embodiment, the second graphical relationship includes: the types of second device layers included in each second device structure, and the types of second device layers not included in each second device structure.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A layout simulation method, characterized in that, include: A first rule model is provided, which includes several different first devices, each first device including several different types of first device structures, and each type of first device structure of each first device having first structural information; Based on the first rule model, several inspection models corresponding to each first device are obtained. Each inspection model includes several groups of devices and inspection condition information corresponding to each group of devices. Each group of devices includes two different first device structures in the first device corresponding to the inspection model and the first structure information of the first device structure. A process design kit is provided, the process design kit including several different second devices, each second device having device information; The extraction module obtains the information to be tested from the process design kit. The information to be tested includes all the second devices, and each second device corresponds one-to-one with each first device. Using the first rule model, several different types of second device structures for each second device are obtained from the information to be detected, and each type of second device structure has second structure information; Based on the inspection model, determine whether the structures of different types of second devices in each second device overlap in position; After determining whether the second device structures of different types in each second device overlap in position according to the inspection model, when the second device structures of different types in the second device overlap in position, the first structure information of the first device structure corresponding to the overlapping second device structure in the second device is modified in the first rule model.

2. The layout simulation method as described in claim 1, characterized in that, Each of the first structural information includes: the first device structure position information corresponding to the first device structure, several different types of first device layers, the first graphic relationship between the first device structure and the several different types of first device layers, the position information of several first device layers corresponding to the several different types of first device layers, and the positional relationship between the first device structure position information and the several first device layer position information.

3. The layout simulation method as described in claim 2, characterized in that, The first graphical relationship includes: the types of first device layers included in each first device structure, and the types of first device layers not included in each first device structure.

4. The layout simulation method as described in claim 2, characterized in that, The first device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

5. The layout simulation method as described in claim 2, characterized in that, The device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

6. The layout simulation method as described in claim 5, characterized in that, Each of the second structural information includes: the location information of the second device structure corresponding to the second device structure, several different types of second device layers, and the second graphic relationship between the second device structure and the several different types of second device layers. Each second device structure corresponds one-to-one with each first device structure, each second structural information corresponds one-to-one with each first structural information, and the second graphic relationship of each second device structure is the same as the first graphic relationship of each first device structure corresponding to each second device structure.

7. The layout simulation method as described in claim 6, characterized in that, The method for obtaining several different types of second device structures of each second device includes: obtaining each first device corresponding to each second device based on several different types of second device layers of each second device in the information to be detected; obtaining several different types of first device layers corresponding to several different types of second device layers in each second device; and obtaining several different types of second device structures of each second device based on the first graphic relationship of the corresponding several different types of first device layers.

8. The layout simulation method as described in claim 6, characterized in that, The second graphical relationship includes: the types of second device layers included in each second device structure, and the types of second device layers not included in each second device structure.

9. The layout simulation method as described in claim 6, characterized in that, The second device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

10. The layout simulation method as described in claim 1, characterized in that, Also includes: After determining whether the different types of second device structures in each second device overlap in position according to the inspection model, the overlap check is completed when there is no positional overlap in each type of second device structure in each second device.

11. The layout simulation method as described in claim 1, characterized in that, The first device includes one or more of the following: an N-type MOS transistor, a P-type MOS transistor, an NPN transistor, and an NPN transistor.

12. The layout simulation method as described in claim 1, characterized in that, The second device includes one or more of the following: an N-type MOSFET, a P-type MOSFET, an NPN transistor, and an NPN transistor.

13. The layout simulation method as described in claim 1, characterized in that, The first device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

14. The layout simulation method as described in claim 1, characterized in that, The second device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

15. A layout simulation device, characterized in that, include: The first rule model includes several different first devices, each first device includes several different types of first device structures, and each type of first device structure of each first device has first structure information. The inspection module is used to obtain several inspection models corresponding to each of the first devices according to the first rule model. Each inspection model includes several groups of devices and inspection condition information corresponding to each group of devices. Each group of devices includes two different types of first device structures in the first device corresponding to the inspection model and the first structure information of the first device structure. A process design kit, the process design kit comprising several different second devices, each second device having device information; The extraction module obtains the information to be tested from the process design kit. The information to be tested includes all the second devices, and each second device corresponds one-to-one with each first device. The structure module is used to obtain several different types of second device structures for each second device from the information to be detected using the first rule model, and each type of second device structure has second structure information. The judgment module is used to determine, based on the inspection model, whether the structures of different types of second devices in each second device overlap in position; The modification module is used, after the judgment module, to modify the first structure information of the first device structure corresponding to the overlapping second device structure in the first rule model when there is positional overlap between different types of second device structures in the second device.

16. The layout simulation device as described in claim 15, characterized in that, Each of the first structural information includes: the first device structure position information corresponding to the first device structure, several different types of first device layers, the first graphic relationship between the first device structure and the several different types of first device layers, the position information of several first device layers corresponding to the several different types of first device layers, and the positional relationship between the first device structure position information and the several first device layer position information.

17. The layout simulation device as described in claim 16, characterized in that, The first graphical relationship includes: the types of first device layers included in each first device structure, and the types of first device layers not included in each first device structure.

18. The layout simulation apparatus as described in claim 16, characterized in that, The first device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

19. The layout simulation device as described in claim 16, characterized in that, The device information includes: several different types of second device layers, and several second device layer position information corresponding to the several different types of second device layers.

20. The layout simulation device as described in claim 19, characterized in that, Each of the second structural information includes: the location information of the second device structure corresponding to the second device structure, several different types of second device layers, and the second graphic relationship between the second device structure and the several different types of second device layers. Each second device structure corresponds one-to-one with each first device structure, each second structural information corresponds one-to-one with each first structural information, and the second graphic relationship of each second device structure is the same as the first graphic relationship of each first device structure corresponding to each second device structure.

21. The layout simulation device as described in claim 20, characterized in that, The method for obtaining several different types of second device structures of each second device includes: obtaining each first device corresponding to each second device based on several different types of second device layers of each second device in the information to be detected; obtaining several different types of first device layers corresponding to several different types of second device layers in each second device; and obtaining several different types of second device structures of each second device based on the first graphic relationship of the corresponding several different types of first device layers.

22. The layout simulation device as described in claim 20, characterized in that, The second graphical relationship includes: the types of second device layers included in each second device structure, and the types of second device layers not included in each second device structure.

23. The layout simulation device as described in claim 20, characterized in that, The second device layer includes one or more of the following: a polysilicon layer, an active region, an N-type implant, a P-type implant, an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

24. The layout simulation device as described in claim 15, characterized in that, Also includes: The termination module is used after the judgment module to complete the overlap check when there is no positional overlap in each type of second device structure in each second device.

25. The layout simulation device as described in claim 15, characterized in that, The first device includes one or more of the following: an N-type MOS transistor, a P-type MOS transistor, an NPN transistor, and an NPN transistor.

26. The layout simulation device as described in claim 15, characterized in that, The second device includes one or more of the following: an N-type MOSFET, a P-type MOSFET, an NPN transistor, and an NPN transistor.

27. The layout simulation device as described in claim 15, characterized in that, The first device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

28. The layout simulation device as described in claim 15, characterized in that, The second device structure includes one or more of the following: an N-type gate layer, an N-type polysilicon layer, an N-type diffusion region, a P-type gate layer, a P-type polysilicon layer, and a P-type diffusion region.

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