Semiconductor package structure and packaging method

Abstract

The application provides a semiconductor packaging structure and a packaging method. The semiconductor packaging structure comprises two semiconductor devices which are stacked, and a metal isolation layer between the semiconductor devices. In the semiconductor packaging structure, the two semiconductor devices are stacked, so that the total volume after packaging is reduced. Meanwhile, the metal isolation layer is arranged between the two semiconductor devices, so that the two semiconductor devices do not interfere with each other during operation.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a semiconductor packaging structure and packaging method. Background Technology

[0002] With the continuous development of electronic devices, the integration level of chips within these devices is constantly increasing. This necessitates reducing the size of various components within the chip, posing a significant challenge to component packaging. Traditional single-sided packaging structures are relatively large and cannot meet the needs of small-sized chips. In existing technologies, some components are stacked to reduce chip size; however, stacked components can generate electromagnetic interference, affecting device performance. Summary of the Invention

[0003] In view of this, this application provides a semiconductor packaging structure and packaging method, as follows:

[0004] A semiconductor package structure, comprising:

[0005] Two semiconductor devices stacked together;

[0006] A metal isolation layer located between the semiconductor devices.

[0007] Preferably, in the above semiconductor packaging structure, the semiconductor device includes: a substrate and a functional structure located on the surface of the substrate; the functional structure includes a first electrode and a second electrode for circuit interconnection.

[0008] Preferably, in the above semiconductor packaging structure, the substrate is a piezoelectric material layer;

[0009] The functional structure includes: an electrode layer located on the surface of the substrate, the side of the electrode layer facing away from the substrate having a thick metal layer, the thick metal layer being used for electrical connection of different electrodes in the electrode layer; an insulating protective layer covering the electrode layer and the thick metal layer, the insulating protective layer having a first opening and a second opening; the thick metal layer exposed through the first opening serving as the first electrode terminal, and the thick metal layer exposed through the second opening serving as the second electrode terminal.

[0010] Preferably, in the above-described semiconductor packaging structure, in the stacking direction of the two semiconductor devices, the first electrical terminals of the two semiconductor devices are arranged opposite to each other, and the second electrical terminals of the two semiconductor devices are arranged opposite to each other.

[0011] Preferably, in the above semiconductor packaging structure, the two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively; the substrates of the two semiconductor devices are disposed opposite to each other;

[0012] The first semiconductor device has a first circuit board on the side opposite to the second semiconductor device. The first and second electrical terminals of the first semiconductor device are electrically connected to the first circuit board through a first electrical connection structure. The first electrical connection structure is also used to support the first circuit board.

[0013] The second semiconductor device has a second circuit board on the side opposite to the first semiconductor device. The first and second electrical terminals of the second semiconductor device are electrically connected to the second circuit board through a second electrical connection structure. The second electrical connection structure is also used to support the second circuit board.

[0014] The edges of the first circuit board and the second circuit board are connected by a third electrical connection structure, which also serves to support the first circuit board and the second circuit board.

[0015] Preferably, in the above semiconductor packaging structure, the first circuit board and the second circuit board are printed circuit boards or ceramic circuit boards;

[0016] The second circuit board has pins on the side opposite to the first circuit board for connecting to external circuits.

[0017] Preferably, in the above semiconductor packaging structure, the two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively;

[0018] In the second semiconductor device, the surface of the functional structure facing away from the substrate is a plane, and the plane has a first opening exposing the first electrode and a second opening exposing the second electrode;

[0019] Wherein, the substrate of the first semiconductor device is fixed on the plane; the first electrode of the first semiconductor device and the second semiconductor device are electrically connected through a first conductive hole, and the second electrode is electrically connected through a second conductive hole; the metal isolation layer is insulated from the first conductive hole and the second conductive hole.

[0020] This application also provides a packaging method for preparing any of the semiconductor packaging structures described above, comprising:

[0021] Fabrication of semiconductor devices;

[0022] The two semiconductor devices are stacked and fixed;

[0023] A metal isolation layer is provided between the two semiconductor devices.

[0024] Preferably, in the above packaging method, the method for preparing the semiconductor device includes:

[0025] Provide substrate;

[0026] A functional structure is formed on one side surface of the substrate, the functional structure including a first electrode and a second electrode for circuit interconnection.

[0027] Preferably, in the above encapsulation method, the method for forming the functional structure includes:

[0028] An electrode layer is formed on the surface of the substrate;

[0029] A thick metal layer is formed on the side of the electrode layer opposite to the substrate; the thick metal layer is used for electrical connection of different electrodes in the electrode layer;

[0030] An insulating protective layer is formed covering the electrode layer and the thick metal layer, the insulating protective layer having a first opening and a second opening; the thick metal layer exposed through the first opening serves as the first electrode terminal, and the thick metal layer exposed through the second opening serves as the second electrode terminal.

[0031] Preferably, in the above packaging method, the two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively;

[0032] Stacking and fixing the two semiconductor devices includes:

[0033] The metal isolation layer is formed on the substrate surface of one of the first semiconductor device and the second semiconductor device;

[0034] The substrate of the first semiconductor device and the substrate of the second semiconductor device are bonded and fixed together.

[0035] A first circuit board is fixedly connected to the side of the first semiconductor device away from the second semiconductor device, and a second circuit board is fixedly connected to the side of the second semiconductor device away from the first semiconductor device; the first and second electrical terminals of the first semiconductor device are respectively electrically connected to the first circuit board through a first electrical connection structure, which also serves to support the first circuit board; the first and second electrical terminals of the second semiconductor device are respectively electrically connected to the second circuit board through a second electrical connection structure, which also serves to support the second circuit board.

[0036] The edges of the first circuit board and the second circuit board are electrically connected by a third electrical connection structure, which also serves to support the first circuit board and the second circuit board.

[0037] Preferably, in the above packaging method, the two semiconductor devices are a first semiconductor device and a second semiconductor device; in the second semiconductor device, the surface of the functional structure facing away from the substrate is a plane, and the plane has a first opening exposing the first electrode and a second opening exposing the second electrode;

[0038] Stacking and fixing the two semiconductor devices includes:

[0039] The metal isolation layer is formed on the plane or on the substrate surface of the first semiconductor device;

[0040] The first semiconductor device is fixed on the plane;

[0041] A first conductive hole and a second conductive hole are formed through the first semiconductor device. The first electrode of the first semiconductor device and the second semiconductor device are electrically connected through the first conductive hole, and the second electrode is electrically connected through the second conductive hole. The metal isolation layer is insulated from the first conductive hole and the second conductive hole.

[0042] Based on the above description, this application provides a semiconductor packaging structure and packaging method. In this semiconductor packaging structure, two semiconductor devices are stacked, reducing the size of the packaged device. Simultaneously, a metal isolation layer is provided between the two semiconductor devices to prevent mutual interference during operation. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0044] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0045] Figure 1 A schematic diagram of a semiconductor packaging structure provided in this application;

[0046] Figure 2 A schematic diagram of another semiconductor packaging structure provided in this application;

[0047] Figure 3 A schematic diagram of yet another semiconductor packaging structure provided in this application;

[0048] Figures 4-12 This application provides a semiconductor packaging method with corresponding product structure diagrams at different process steps;

[0049] Figures 13-14 The product structure diagrams corresponding to different process steps of another semiconductor packaging method provided in the embodiments of this application are shown. Detailed Implementation

[0050] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in this application. The semiconductor packaging structure includes: two stacked semiconductor devices Q; and a metal isolation layer 15 located between the semiconductor devices Q.

[0053] The semiconductor packaging structure provided in this application is applicable to any of the following: filters, dual combiners, and multiplexers. Taking a filter as an example, in this semiconductor packaging structure, two semiconductor devices Q are stacked, reducing the size of the packaged device. Simultaneously, a metal isolation layer 15 is provided between the two semiconductor devices Q to prevent mutual interference between them during operation.

[0054] The semiconductor device Q described above includes a substrate 10 and a functional structure located on the surface of the substrate 10; the functional structure includes a first electrode 21 and a second electrode 22 for circuit interconnection.

[0055] In a direction parallel to the substrate 10, the first electrode 21 and the second electrode 22 are disposed on both sides of the semiconductor device Q for connection with external circuits.

[0056] like Figure 1As shown, in this semiconductor device Q, the substrate 10 is a piezoelectric material layer; the functional structure includes: an electrode layer 11 located on the surface of the substrate 10, the side surface of the electrode layer 11 facing away from the substrate 10 having a thick metal layer 13, the thick metal layer 13 being used for electrical connection of different electrodes in the electrode layer 11; an insulating protective layer 14 covering the electrode layer 11 and the thick metal layer 13, the insulating protective layer 14 having a first opening and a second opening; the thick metal layer 13 exposed through the first opening serves as a first electrode terminal 21, and the thick metal layer 13 exposed through the second opening serves as a second electrode terminal 22.

[0057] The piezoelectric material layer can be made of one or more of the following piezoelectric materials: barium titanate (BT), lead zirconate titanate (PZT), modified lead zirconate titanate, lead metaniobate, lithium lead barium niobate (PBLN), and modified lead titanate (PT). The first electrode 21 and the second electrode 22 of the semiconductor device Q are portions of a thick metal layer 13 exposed through the first and second openings of the insulating protective layer 14. This thick metal layer 13 serves as the ohmic contact layer of the electrode layer, electrically connecting to the outside, reducing contact resistance, improving the stability of the electrical connection, and protecting the electrode layer 11, thus extending the lifespan of the semiconductor device.

[0058] Electrode layer 1 includes multiple electrodes. Electrodes that need to be connected can be connected through thick metal layer 13. Thick metal layer 13 can be insulated from electrodes that need to be isolated through insulating layer 12.

[0059] In the above description, in the stacking direction of the two semiconductor devices Q, the first electrical terminals 21 of the two semiconductor devices Q are arranged opposite to each other, and the second electrical terminals 22 of the two semiconductor devices Q are arranged opposite to each other.

[0060] Since the first terminals 21 of the two semiconductor devices Q are arranged opposite each other, stacking the two semiconductor devices can reduce the distance between the two first terminals 21. If the two first terminals 21 are connected to each other, the connection cost can be reduced and external influences can be reduced.

[0061] In the embodiments of this application, the stacking method of the two semiconductor devices Q is not limited and can be selected based on requirements. For ease of understanding, this application provides two different connection methods for description.

[0062] refer to Figure 2 , Figure 2 This is a schematic diagram of another semiconductor packaging structure provided in this application. Wherein, Figure 2 The two stacked semiconductor devices Q inside the package structure shown are Figure 1The diagram shows two semiconductor devices Q. These two semiconductor devices Q are a first semiconductor device Q1 and a second semiconductor device Q2. The substrates 10 of the two semiconductor devices Q are disposed opposite to each other. The first semiconductor device Q1 has a first circuit board 41 on the side facing away from the second semiconductor device Q2. The first electrode 21 and the second electrode 22 of the first semiconductor device Q1 are electrically connected to the first circuit board 41 via a first electrical connection structure 31, which also supports the first circuit board 41. The second semiconductor device Q2 has a second circuit board 42 on the side facing away from the first semiconductor device Q1. The first electrode 21 and the second electrode 22 of the second semiconductor device Q2 are electrically connected to the second circuit board 42 via a second electrical connection structure 32, which also supports the second circuit board 42. The edges of the first circuit board 41 and the second circuit board 42 are connected via a third electrical connection structure 33, which also supports the first circuit board 41 and the second circuit board 42.

[0063] The first semiconductor device Q1 is connected to the first circuit board 41 via a first electrical connection structure 31, with a gap between them. The second semiconductor device Q2 is connected to the first circuit board 42 via a second electrical connection structure 32, with a gap between them. The first circuit board 41 and the second circuit board 42 are electrically connected via a third electrical connection structure 33, thus achieving the connection between the two semiconductor devices. The third electrical connection structure 33 is located at the edge of the two circuit boards, with a gap between it and the two semiconductor devices. The third electrical connection structure also provides support for the two circuit boards and forms an encapsulation structure with the first circuit board 41 and the second circuit board 42. The encapsulation structure contains the stacked first semiconductor device Q1 and the second semiconductor device Q2, thereby protecting the semiconductor device Q1.

[0064] The first electrical connection structure 31, the second electrical connection structure 32, and the third electrical connection structure 33 are all made of metal. The height of the first electrical connection structure 31 is the same as the height of the second electrical connection structure 32, ensuring that after the two semiconductor devices Q are bonded together, they can be electrically connected and fixed to the corresponding circuit board through the first electrical connection structure 31 and the second electrical connection structure 32. Simultaneously, the first electrical connection structure 31 and the second electrical connection structure 32 can also function as inductors, improving signal distribution in the circuit and enhancing the performance of the semiconductor devices.

[0065] In the above description, the first circuit board 41 and the second circuit board 42 used are printed circuit boards or ceramic circuit boards; the second circuit board 42 has pins 50 for connecting external circuits on the side opposite to the first circuit board 41.

[0066] This application only selects two relatively common circuit boards as examples, but the same applies to other types of circuit boards. The pins on the side of the second circuit board 42 opposite to the first circuit board 41 correspond to the first electrode 21 and the second electrode 22 of the first semiconductor device Q1 and the second semiconductor device Q2, respectively, thereby realizing the connection between the first semiconductor Q1 and the second semiconductor Q2 and the external circuit.

[0067] By setting up two circuit boards, the semiconductor device Q is encapsulated inside, protecting the semiconductor device Q. At the same time, pins 50 for connecting to external circuits are set on the second circuit board 42. The two semiconductor devices Q are connected to their corresponding circuit boards through the first electrical connection structure 31 and the second electrical connection structure 32. The two circuit boards are connected through the third electrical connection structure 33. The two semiconductor devices Q are connected to the external circuit through the circuit on the second circuit board 42 and the pins 50.

[0068] This application also provides another semiconductor packaging structure, such as Figure 3 As shown, Figure 3 This is a schematic diagram of another semiconductor packaging structure provided in this application. The two semiconductor devices Q are a first semiconductor device Q1 and a second semiconductor device Q2. In the second semiconductor device Q2, the surface of the functional structure facing away from the substrate 10 is a plane, with a first opening exposing a first electrode 21 and a second opening exposing a second electrode 22. The substrate 10 of the first semiconductor device Q1 is fixed on the plane. The first electrode 21 of the first semiconductor device Q1 and the second semiconductor device Q2 are electrically connected through a first conductive hole A1, and the second electrode 22 is electrically connected through a second conductive hole A2. The metal isolation layer 15 is insulated from both the first conductive hole A1 and the second conductive hole A2.

[0069] The first semiconductor device Q1 and the second semiconductor device Q2 are interconnected through conductive vias, reducing the connection distance between them and minimizing the impact of parasitic inductance. Simultaneously, the first semiconductor device Q1 protects the second semiconductor device Q2. The metal isolation layer 15 located between the first semiconductor device Q1 and the second semiconductor device Q2 protects them from mutual interference during operation. Using the stacking method described above, the size of the semiconductor device Q can be further reduced.

[0070] The metal isolation layer 15 is hollowed out at positions corresponding to the first conductive hole A1 and the second conductive hole A2 to achieve insulation between the metal isolation layer 15 and the conductive holes.

[0071] refer to Figure 2 , Figures 4-12 As shown, this application also provides a packaging method for preparing the semiconductor packaging structure described above. Figures 4-12 This application provides a semiconductor packaging method with corresponding product structure diagrams at different process steps. The packaging method includes:

[0072] Step S10, as follows Figure 4 As shown, semiconductor device Q is fabricated.

[0073] Step S20, as follows Figure 5 As shown, two semiconductor devices Q are stacked and fixed; wherein, a metal isolation layer 15 is provided between the two semiconductor devices Q.

[0074] In step S10 above, the method for fabricating semiconductor device Q includes:

[0075] Step S11, as follows Figure 6 As shown, a substrate 10 is provided.

[0076] Step S12, as follows Figures 7-10 As shown, a functional structure is formed on one side surface of the substrate 10, the functional structure including a first electrode 21 and a second electrode 22 for circuit interconnection.

[0077] When a functional structure is formed on one side of the substrate 10, a sacrificial layer can be prepared on the other side of the substrate 10 to protect the substrate 10. After the functional structure is formed, the sacrificial layer is removed.

[0078] In step S12 above, the method for forming the functional structure includes:

[0079] Step S121, as follows Figure 7 As shown, an electrode layer 11 is formed on the surface of the substrate 10.

[0080] Step S122, as follows Figures 8-9 As shown, a thick metal layer 13 is formed on the side of the electrode layer 11 facing away from the substrate 10; the thick metal layer 13 is used for electrical connection of different electrodes in the electrode layer 11. Electrodes in the electrode layer 11 can be connected through the thick metal layer 13, and electrodes that need to be insulated from the thick metal layer 13 can be isolated through the insulating layer 12. This can be done as follows... Figure 8 As shown, an insulating layer 12 is formed to cover the electrodes that need to be isolated, and then as... Figure 9 As shown, a thick metal layer is formed to connect the electrodes that need to be connected.

[0081] Step S123, as follows Figure 10 As shown, an insulating protective layer 14 is formed covering the electrode layer 11 and the thick metal layer 13. The insulating protective layer 14 has a first opening and a second opening. The thick metal layer 13 exposed through the first opening serves as the first electrode terminal 21, and the thick metal layer 13 exposed through the second opening serves as the second electrode terminal 22.

[0082] The electrode layer 11 can be composed of multiple identical electrodes or multiple different electrodes. This application does not limit this. It should be noted that when the thick metal layer 13 to be formed needs to connect two non-adjacent electrodes, an insulating layer 12 needs to be prepared beforehand between the two electrodes, such as... Figure 8 As shown, the electrodes between the two electrodes are isolated.

[0083] In the packaging method provided in this application, a first semiconductor device Q1 and a second semiconductor device Q2 are symmetrically arranged based on a metal isolation layer 15. The two semiconductor devices are respectively the first semiconductor device Q1 and the second semiconductor device Q2; the two semiconductor devices Q1 are stacked and fixed, including:

[0084] Step S21, as follows Figure 11 As shown, a metal isolation layer 15 is formed on the surface of the substrate 10 of one of the first semiconductor device Q1 and the second semiconductor device Q2.

[0085] This application does not limit the formation of the metal isolation layer 15 to either the first semiconductor device Q1 or the second semiconductor device Q2, such as Figure 5 or Figure 11 As shown, Figure 5 and Figure 11 A metal isolation layer 15 is formed on one of the two semiconductor devices. It can be seen that the setting of the metal isolation layer 15 does not affect the subsequent bonding and fixing of the first semiconductor device Q1 and the second semiconductor device Q2.

[0086] Step S22, as follows Figure 11 As shown, the substrate 10 of the first semiconductor device Q1 and the substrate 10 of the second semiconductor device Q2 are bonded and fixed together.

[0087] The substrates 10 of the first semiconductor device Q1 and the second semiconductor device Q2 are bonded together, so that the first electrode 21 and the second electrode 22 of both are on the outside, which facilitates connection with external circuits.

[0088] Step S23, as Figure 12 As shown, a first circuit board 41 is fixedly connected to the side of the first semiconductor device Q1 away from the second semiconductor device Q2, and a second circuit board 42 is fixedly connected to the side of the second semiconductor device Q2 away from the first semiconductor device Q1. The first electrode 21 and the second electrode 22 of the first semiconductor device Q1 are electrically connected to the first circuit board 41 through a first electrical connection structure 31, which also supports the first circuit board 41. The first electrode 21 and the second electrode 22 of the second semiconductor device Q2 are electrically connected to the second circuit board 42 through a second electrical connection structure 32, which also supports the second circuit board 42.

[0089] Step S24, as Figure 2 As shown, the edges of the first circuit board 41 and the second circuit board 42 are electrically connected by a third electrical connection structure 33, which also serves to support the first circuit board 41 and the second circuit board 42.

[0090] The first circuit board 41 and the second circuit board 42 are fixed by setting the third electrical connection structure 33. By setting the first electrical connection structure 31 and the second electrical connection structure 32, the two semiconductor devices Q are fixed to the corresponding circuit boards respectively. At the same time, the third electrical connection structure 33 can also connect the first circuit board 41 and the second circuit board 42, so that the first semiconductor device Q1 is connected to the second circuit board 42 through the first circuit board 41. Finally, both are connected to the external circuit through the pins on the side of the second circuit board 42 away from the first circuit board 41.

[0091] Regarding the step S20 above, which involves fixing the two semiconductor layers together, this application also provides a packaging method for preparing another semiconductor packaging structure, such as... Figure 3 , Figures 13-14 As shown, Figures 13-14 This document presents a product structure diagram corresponding to different process steps of another semiconductor packaging method provided in this application embodiment. Two semiconductor devices Q are designated as a first semiconductor device Q1 and a second semiconductor device Q2. In the second semiconductor device Q2, the surface of the functional structure facing away from the substrate 10 is planar, with a first opening exposing the first electrode 21 and a second opening exposing the second electrode 22. The planar surface can be pre-formed to facilitate subsequent interconnection of the first electrode 21 and the second electrode 22. Alternatively, holes can be drilled after the first semiconductor device Q1 and the second semiconductor device Q2 are connected, and the first electrode 21 and the second electrode 22 of the two semiconductor devices Q can be connected accordingly based on these holes.

[0092] This application uses the example of pre-forming an opening for illustration: after the two semiconductor devices Q are fabricated, they need to be stacked and fixed. The fixing method includes:

[0093] Step S31, as follows Figure 13 As shown, a metal isolation layer 15 is formed on the surface of the substrate 10 of the first semiconductor device Q1, which is a plane.

[0094] To facilitate the connection of the terminals of the two semiconductor devices Q, the metal isolation layer 15 has openings corresponding to the positions of the first terminal 21 and the second terminal 22 of the second semiconductor, such as... Figure 13 As shown, this is to ensure that the conductive hole and the metal isolation layer 15 are insulated during the subsequent formation of the conductive hole, so as to avoid short circuit.

[0095] Step S32, as follows Figure 14 As shown, the first semiconductor device Q1 is fixed on the plane.

[0096] Step S33, as follows Figure 3 As shown, a first conductive hole A1 and a second conductive hole A2 are formed through the first semiconductor device Q1. The first electrode 21 of the first semiconductor device Q1 and the second semiconductor device Q2 are electrically connected through the first conductive hole A1, and the second electrode 22 is electrically connected through the second conductive hole A2. The metal isolation layer 15 is insulated from the first conductive hole A1 and the second conductive hole A2.

[0097] In this configuration, the first semiconductor device Q1 is positioned on the functional structure of the second semiconductor device Q2, reducing the overall stacked size. Simultaneously, the first semiconductor device Q1 also protects the second semiconductor device Q2. The terminals of the two semiconductor devices Q are connected via the first conductive hole A1 and the second conductive hole A2. The first and second openings of the first semiconductor device Q1 are slightly extended, allowing the terminals of the second semiconductor device Q2 to also connect to external circuits. To ensure the stability of the connection between the terminals of the two semiconductor devices Q, the metal isolation layer 15 has openings at the locations corresponding to the first conductive hole A1 and the second conductive hole A2, thus guaranteeing the stability of their interconnection.

[0098] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. Regarding the packaging methods disclosed in the embodiments, since they correspond to the packaging structures disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the packaging structure section.

[0099] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0100] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0101] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0102] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor packaging structure, characterized in that, include: Two semiconductor devices stacked together; Metal isolation layer located between the semiconductor devices; The semiconductor device includes: a substrate and a functional structure located on the surface of the substrate; the functional structure includes a first electrode and a second electrode for circuit interconnection; the substrate is a piezoelectric material layer; The functional structure includes: an electrode layer located on the surface of the substrate, the side of the electrode layer facing away from the substrate having a thick metal layer, the thick metal layer being used for electrical connection of different electrodes in the electrode layer; an insulating protective layer covering the electrode layer and the thick metal layer, the insulating protective layer having a first opening and a second opening; the thick metal layer exposed through the first opening serving as the first electrode terminal, and the thick metal layer exposed through the second opening serving as the second electrode terminal.

2. The semiconductor packaging structure according to claim 1, characterized in that, In the stacking direction of the two semiconductor devices, the first electrical terminals of the two semiconductor devices are arranged opposite to each other, and the second electrical terminals of the two semiconductor devices are arranged opposite to each other.

3. The semiconductor packaging structure according to claim 1, characterized in that, The two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively; the substrates of the two semiconductor devices are disposed opposite to each other; The first semiconductor device has a first circuit board on the side opposite to the second semiconductor device. The first and second electrical terminals of the first semiconductor device are electrically connected to the first circuit board through a first electrical connection structure. The first electrical connection structure is also used to support the first circuit board. The second semiconductor device has a second circuit board on the side opposite to the first semiconductor device. The first and second electrical terminals of the second semiconductor device are electrically connected to the second circuit board through a second electrical connection structure. The second electrical connection structure is also used to support the second circuit board. The edges of the first circuit board and the second circuit board are connected by a third electrical connection structure, which also serves to support the first circuit board and the second circuit board.

4. The semiconductor packaging structure according to claim 3, characterized in that, The first circuit board and the second circuit board are printed circuit boards or ceramic circuit boards; The second circuit board has pins on the side opposite to the first circuit board for connecting to external circuits.

5. The semiconductor packaging structure according to claim 1, characterized in that, The two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively; In the second semiconductor device, the surface of the functional structure facing away from the substrate is a plane, and the plane has a first opening exposing the first electrode and a second opening exposing the second electrode; Wherein, the substrate of the first semiconductor device is fixed on the plane; the first electrode of the first semiconductor device and the second semiconductor device are electrically connected through a first conductive hole, and the second electrode is electrically connected through a second conductive hole; the metal isolation layer is insulated from the first conductive hole and the second conductive hole.

6. A packaging method for preparing a semiconductor packaging structure as described in any one of claims 1-5, characterized in that, include: Fabricating a semiconductor device includes: providing a substrate; forming a functional structure on one side surface of the substrate, the functional structure including a first electrode and a second electrode for circuit interconnection; The two semiconductor devices are stacked and fixed; A metal isolation layer is provided between the two semiconductor devices; The method for forming the functional structure includes: An electrode layer is formed on the surface of the substrate; A thick metal layer is formed on the side of the electrode layer opposite to the substrate; the thick metal layer is used for electrical connection of different electrodes in the electrode layer; An insulating protective layer is formed covering the electrode layer and the thick metal layer, the insulating protective layer having a first opening and a second opening; the thick metal layer exposed through the first opening serves as the first electrode terminal, and the thick metal layer exposed through the second opening serves as the second electrode terminal.

7. The packaging method according to claim 6, characterized in that, The two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively; Stacking and fixing the two semiconductor devices includes: The metal isolation layer is formed on the substrate surface of one of the first semiconductor device and the second semiconductor device; The substrate of the first semiconductor device and the substrate of the second semiconductor device are bonded and fixed together. A first circuit board is fixedly connected to the side of the first semiconductor device away from the second semiconductor device, and a second circuit board is fixedly connected to the side of the second semiconductor device away from the first semiconductor device; the first and second electrical terminals of the first semiconductor device are respectively electrically connected to the first circuit board through a first electrical connection structure, which also serves to support the first circuit board; the first and second electrical terminals of the second semiconductor device are respectively electrically connected to the second circuit board through a second electrical connection structure, which also serves to support the second circuit board. The edges of the first circuit board and the second circuit board are electrically connected by a third electrical connection structure, which also serves to support the first circuit board and the second circuit board.

8. The packaging method according to claim 6, characterized in that, The two semiconductor devices are a first semiconductor device and a second semiconductor device, respectively; in the second semiconductor device, the surface of the functional structure facing away from the substrate is a plane, and the plane has a first opening exposing the first electrode and a second opening exposing the second electrode; Stacking and fixing the two semiconductor devices includes: The metal isolation layer is formed on the plane or on the substrate surface of the first semiconductor device; The first semiconductor device is fixed on the plane; A first conductive hole and a second conductive hole are formed through the first semiconductor device. The first electrode of the first semiconductor device and the second semiconductor device are electrically connected through the first conductive hole, and the second electrode is electrically connected through the second conductive hole. The metal isolation layer is insulated from the first conductive hole and the second conductive hole.

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