Rc-igbt power device and method of manufacturing

Abstract

The application relates to an RC-IGBT power device and a preparation method. The device comprises a substrate with a first conductive type, a front cell structure prepared on the front surface of the substrate, and a back surface structure prepared on the back surface of the substrate, further comprising a back surface isolation groove for isolating a second conductive type collector region and a first conductive type FRD cathode region adjacent to the second conductive type collector region, the outer sidewall of the back surface isolation groove is in contact with the isolated second conductive type collector region and the first conductive type FRD cathode region, the groove bottom of the back surface isolation groove extends into a first conductive type field stop buffer layer, and the groove bottom of the back surface isolation groove is covered by a second conductive type injection region located in the first conductive type field stop buffer layer. The application can reduce the mutual influence between the IGBT and the FRD, improve the softness of the FRD reverse recovery, and improve the overall performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to a power device and a preparation method, in particular to an RC-IGBT power device and a preparation method. BACKGROUND

[0002] In application, the conventional IGBT (Insulated Gate Bipolar Transistor) is often used in half-bridge or three-phase full-bridge application, and generally needs to be anti-parallel with a diode as a freewheeling path. The RC-IGBT is a reverse-conducting IGBT device, which integrates the IGBT and the anti-parallel freewheeling diode (FRD) on the same chip, and realizes the self-provided commutation function through a special back process, thereby greatly reducing the manufacturing cost and saving the chip area, and the packaging cost and the testing cost can also be reduced. Compared with the application, the volume and complexity of the power system can be reduced, and the RC-IGBT is usually used in motor control.

[0003] For the RC-IGBT, the FRD reverse recovery hardness is large, and the superposition of the motor application can generate a high overshoot voltage, which is very unfriendly to the motor application scene. Therefore, in the manufacturing process of the RC-IGBT, how to optimize the performance of the IGBT and the integrated FRD has become a research focus in the industry, and in particular, how to avoid the mutual influence of the IGBT and the FRD and optimize the reverse recovery characteristics of the FRD as much as possible is a technical problem in the technical field. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings in the prior art, and to provide an RC-IGBT power device and a preparation method, which can reduce the mutual influence between the IGBT and the FRD, improve the softness of the FRD reverse recovery, and improve the performance of the device.

[0005] According to the technical scheme provided by the present application, the RC-IGBT power device comprises a substrate with a first conductivity type, a front cell structure prepared on the front surface of the substrate, and a back structure prepared on the back surface of the substrate, the back structure comprises a first conductivity type field stop buffer layer prepared on the back surface of the substrate, a first conductivity type FRD cathode region prepared on the first conductivity type field stop buffer layer, and a second conductivity type collector region prepared on the first conductivity type field stop buffer layer, wherein,

[0006] The second conductivity type collector region is in direct correspondence with the corresponding IGBT front cell unit in the front cell structure, the first conductivity type FRD cathode region is in direct correspondence with the corresponding FRD front cell unit in the front cell structure, and the second conductivity type collector region is adjacent to the first conductivity type FRD cathode region.

[0007] The back surface isolation groove is filled with a back surface metal electrode, and the back surface metal electrode is in ohmic contact with the second conductivity type injection region covering the bottom of the back surface isolation groove.

[0008] The second conductivity type injection region is in contact with the second conductivity type collector region and the first conductivity type FRD cathode region on both sides of the back surface isolation groove,

[0009] The second conductivity type collector region, the first conductivity type FRD cathode region and the second conductivity type injection region are all in ohmic contact with the back surface metal electrode.

[0010] The bottom of the back surface isolation groove is in a circular arc shape or a flat shape.

[0011] The back surface metal electrode is also filled in the back surface isolation groove, and the back surface metal electrode filled in the back surface isolation groove is in ohmic contact with the second conductivity type injection region covering the bottom of the back surface isolation groove.

[0012] The front cell structure is prepared in a cell region of a substrate, and a second conductivity type base region traversing the cell region is arranged in the cell region.

[0013] The IGBT front cell units in the front cell structure are connected in parallel to form an integrated body, and an FRD front cell unit is arranged between any two adjacent IGBT front cell units, wherein

[0014] The IGBT front cell unit adopts a trench gate structure.

[0015] The FRD front cell unit includes at least two FRD unit trenches, and an FRD unit polysilicon is filled in the FRD unit trench, and the FRD unit polysilicon is insulated and separated from the inner wall of the FRD unit trench by an FRD unit polysilicon insulation medium layer.

[0016] The bottom of the IGBT unit trench and the bottom of the FRD unit trench in the trench gate structure are located below the second conductivity type base region, and the second conductivity type base region is in contact with the corresponding outer side walls of the IGBT unit trench and the FRD unit trench.

[0017] The second conductivity type base region between adjacent FRD unit trenches is in ohmic contact with an FRD anode metal.

[0018] A first conductivity type high-energy injection layer prepared in the cell region of the substrate is further included, wherein

[0019] The first-conductivity-type high-energy implantation layer is located below the second-conductivity-type base region and is adjacent to the second-conductivity-type base region.

[0020] The bottom of the IGBT cell trench and the bottom of the FRD cell trench are both located in the first-conductivity-type high-energy implantation layer.

[0021] For the IGBT front surface cell unit, further comprising a trench gate polysilicon filled in the IGBT cell trench and a first-conductivity-type emitter region in contact with the outer sidewall of the IGBT cell trench, wherein,

[0022] The trench gate polysilicon is insulated and isolated from the inner wall of the IGBT cell trench by a trench gate polysilicon insulation medium layer, and the trench gate polysilicon is in ohmic contact with the gate metal layer above the substrate.

[0023] The first-conductivity-type emitter region is located in the second-conductivity-type base region, and the first-conductivity-type emitter region and the second-conductivity-type base region are both in ohmic contact with the emitter metal.

[0024] The emitter metal is electrically connected to the corresponding second-conductivity-type base region through a second-conductivity-type emitter metal ohmic contact region.

[0025] The FRD anode metal is electrically connected to the corresponding second-conductivity-type base region through a second-conductivity-type anode metal ohmic contact region.

[0026] The doping concentration of the second-conductivity-type emitter metal ohmic contact region and the second-conductivity-type anode metal ohmic contact region is greater than the doping concentration of the second-conductivity-type base region.

[0027] First, a first-conductivity-type high-energy implantation layer is prepared in the cell region of the substrate, and then a front surface cell process is performed on the front surface of the substrate after the first-conductivity-type high-energy implantation layer is prepared, to obtain the required front surface cell structure, wherein,

[0028] When the first-conductivity-type high-energy implantation layer is prepared, the energy of the first-conductivity-type impurity ion implantation is 2 MeV, the dose of the first-conductivity-type impurity ion implantation is in the order of *e12, and the type of the first-conductivity-type impurity ion implantation includes P or H.

[0029] After the first-conductivity-type impurity ion implantation, a high-temperature annealing step is performed to activate the formation of the required first-conductivity-type high-energy implantation layer, wherein the annealing temperature in the high-temperature annealing step is 1150°C.

[0030] A preparation method of an RC-IGBT power device, for preparing the RC-IGBT power device, wherein the preparation method comprises the following steps:

[0031] A substrate with a first conductivity type is provided, and a front cell process is performed on a cell region of the substrate to form a desired front cell structure;

[0032] A backside implantation process is performed on the substrate to form a first conductivity type field stop buffer layer on the backside of the substrate and a first conductivity type implantation layer on the first conductivity type field stop buffer layer after the backside implantation process;

[0033] A trench etching process is performed on the backside of the substrate to form a desired backside isolation trench, wherein a bottom of the backside isolation trench extends into the first conductivity type field stop buffer layer;

[0034] A different conductivity type impurity ion implantation process is performed on the backside of the substrate to form a first conductivity type FRD cathode region, a second conductivity type collector region and a second conductivity type implantation region using the first conductivity type implantation layer, wherein,

[0035] The second conductivity type implantation region is located in the first conductivity type field stop buffer layer and covers the bottom of the backside isolation trench in the first conductivity type field stop buffer layer, the second conductivity type collector region is directly opposite to an IGBT front cell in the front cell structure, the first conductivity type FRD cathode region is directly opposite to an FRD front cell in the front cell structure, and the second conductivity type collector region is isolated from an adjacent first conductivity type FRD cathode region by the backside isolation trench;

[0036] A metal deposition process is performed on the backside of the substrate to form a backside metal electrode, wherein the backside metal electrode is in ohmic contact with the second conductivity type collector region, the first conductivity type FRD cathode region and the second conductivity type implantation region.

[0037] After the substrate is provided, a first conductivity type impurity ion implantation process is performed on the front side of the substrate to form a first conductivity type high-energy implantation region, wherein,

[0038] The energy of the first conductivity type impurity ion implantation is 100 keV to 2 MeV, the dose of the first conductivity type impurity ion implantation is 5e12 to 1e13 orders of magnitude, and the type of the N-type impurity ion implantation includes P or H;

[0039] After the first conductivity type impurity ion implantation, a high-temperature annealing process is performed to activate the formation of the desired first conductivity type high-energy implantation region, wherein the annealing temperature in the high-temperature annealing process is 900°C to 1150°C;

[0040] After the first conductive type high-energy injection region is prepared, a front surface cell process is performed on the front surface of the substrate to prepare a front surface cell structure, wherein after the front surface cell structure is prepared, the first conductive type high-energy injection region forms a first conductive type high-energy injection layer.

[0041] The front surface cell structure is prepared in a cell region of the substrate, and a second conductive type base region traversing the cell region is arranged in the cell region.

[0042] The front surface cell structure includes a plurality of parallelly distributed IGBT front surface cell units and an FRD front surface cell unit distributed between any two adjacent IGBT front surface cell units, wherein

[0043] The IGBT front surface cell unit adopts a trench gate structure.

[0044] The FRD front surface cell unit includes at least two FRD unit trenches, and an FRD unit polysilicon is filled in the FRD unit trench, and the FRD unit polysilicon is insulated and separated from the inner wall of the FRD unit trench by an FRD unit polysilicon insulation medium layer.

[0045] The trench bottom of the IGBT unit trench in the trench gate structure and the trench bottom of the FRD unit trench are both located below the second conductive type base region, and the second conductive type base region is in contact with the corresponding outer sidewall of the IGBT unit trench and the FRD unit trench.

[0046] The second conductive type base region between adjacent FRD unit trenches is in ohmic contact with an FRD anode metal.

[0047] The corresponding trench bottom of the IGBT unit trench and the FRD unit trench is located in the first conductive type high-energy injection layer.

[0048] Of the two "first conductive type" and "second conductive type", for an N-type RC-IGBT power device, the first conductive type refers to N-type, and the second conductive type refers to P-type; for a P-type RC-IGBT power device, the types referred to by the first conductive type and the second conductive type are exactly opposite to those of the N-type power device.

[0049] Advantages of the present application:

[0050] By forming the first conductive type high-energy ion injection region on the front surface of the substrate and finally forming the first conductive type high-energy ion injection layer, the carrier distribution of the formed IGBT and FRD can be optimized, Vcesat is reduced, and Irrm of the FRD is also reduced, so that the product is more suitable for the scheme of motor control.

[0051] The isolation of the second conductive type collector region and the first conductive type FRD cathode region can be realized through the back surface isolation groove, the mutual influence of the FRD region and the IGBT region in the RC-IGBT is avoided, the back surface regions are more accurately controlled, and the effective width and the doping concentration of the IGBT region are accurately controlled, and the overall performance of the IGBT is improved by optimizing the use of the IGBT collector region.

[0052] When the second conductive type collector region and the second conductive type injection region are formed, the doping concentration of the region at the bottom of the back surface isolation groove in the first conductive type field stop buffer layer can be reduced by the general injection of the second conductive type impurity ions to the back surface of the substrate, the resistivity of the region at the bottom of the back surface isolation groove in the first conductive type field stop buffer layer is improved, the boron injection of the IGBT back surface can be triggered at a smaller current, and the snapback of the RC-IGBT power device can occur at a very small current, which can be ignored.

[0053] Since the back surface isolation groove extends into the first conductive type field stop buffer layer, the efficiency of the first conductive type FRD cathode region during boron injection is improved, which helps to increase the back boron injection of the FRD during the reverse recovery process, thereby increasing the softness of the reverse recovery, avoiding the overvoltage peak caused by the superposition of high di / dt and large system inductance, and damaging the system. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 It is an embodiment schematic diagram of the RC-IGBT power device of the application.

[0055] Figures 2 to 9 It is an embodiment process step sectional view of the preparation method of the RC-IGBT power device of the application, wherein,

[0056] Figure 2 It is an embodiment sectional view after the N+ high-energy injection region is prepared.

[0057] Figure 3 It is an embodiment sectional view after the trench gate polysilicon and the FRD unit polysilicon are prepared.

[0058] Figure 4 It is an embodiment sectional view after the emitter metal and the FRD anode metal are prepared.

[0059] Figure 5 It is an embodiment sectional view after the N+ injection layer is prepared.

[0060] Figure 6 It is an embodiment sectional view of the trench etching to form the back surface isolation groove.

[0061] Figure 7 Another embodiment cross-sectional view of trench etching to form a backside isolation trench of the present application.

[0062] Figure 8 Another embodiment cross-sectional view after P-type impurity ion implantation for the embodiment in Figure 7

[0063] Another embodiment cross-sectional view after P-type impurity ion implantation for the embodiment in Figure 9

[0064] Another embodiment cross-sectional view after P-type impurity ion implantation for the embodiment in DETAILED DESCRIPTION

[0065] The present application will be further described below in conjunction with specific drawings and embodiments.

[0066] In order to reduce the mutual influence between IGBT and FRD, improve the softness of FRD reverse recovery, and improve the overall performance of the device, for the RC-IGBT power device, one embodiment of the present application includes a substrate 9 having an N conductivity type, a front surface cell structure prepared on the front surface of the substrate 9, and a back surface structure prepared on the back surface of the substrate 9, the back surface structure includes an N-type field stop buffer layer 10 prepared on the back surface of the substrate 9, an N-type FRD cathode region 14 prepared on the N-type field stop buffer layer 10, and a P-type collector region 12 prepared on the N-type field stop buffer layer 10, wherein,

[0067] The P-type collector region 12 is directly opposite to the corresponding IGBT front surface cell unit in the front surface cell structure, the N-type FRD cathode region 14 is directly opposite to the corresponding FRD front surface cell unit in the front surface cell structure, and one P-type collector region 12 is adjacent to one N-type FRD cathode region 14.

[0068] ​The back surface isolation trench 22 contacts the isolated P-type collector region 12 and N-type FRD cathode region 14 on both sides of the P-type injection region 13, and the bottom of the back surface isolation trench 22 is covered by the P-type injection region 13 in the N-type field stop buffer layer 10.

[0069] The P-type injection region 13 contacts the P-type collector region 12 and N-type FRD cathode region 14 on both sides of the back surface isolation trench 22,

[0070] The P-type collector region 12, N-type FRD cathode region 14 and P-type injection region 13 are in ohmic contact with the back metal electrode 11.

[0071] Specifically, the substrate 9 can be in a form commonly used at present, and can be selected as a silicon substrate, etc. The substrate 9 can be selected according to actual needs, and can meet the application requirements. Generally, the substrate 9 has a front surface and a back surface opposite to the front surface. The front cell structure is prepared on the front surface of the substrate 9, and the back structure can be prepared on the back surface of the substrate 9. The front cell structure can be in a form commonly used at present, Figure 1 and Figure 9 An embodiment of the front cell structure is shown in FIG. 1, and the specific conditions of the front cell structure can be selected according to needs, and can meet the requirements of the RC-IGBT device.

[0072] Figure 1 and Figure 9 A back structure of the RC-IGBT device is also shown in FIG. 1. The back structure generally includes the N-type field stop buffer layer 10. The doping concentration of the N-type field stop buffer layer 10 is greater than that of the N-type substrate 9. Generally, the N-type field stop buffer layer 10 can be prepared by ion implantation and annealing on the back surface of the N-type substrate 9. The N-type field stop buffer layer 10 generally corresponds to the entire cell region. For an RC-IGBT power device, generally including a cell region in the center and a terminal protection region surrounding the cell region, that is, the front cell structure is located in the cell region. The specific functions and distribution states of the cell region and the terminal protection region can be consistent with the prior art.

[0073] In order to form the collector of the IGBT, the P-type collector region 12 is arranged on the N-type field stop buffer layer 10, and in order to form the cathode of the FRD, the N-type FRD cathode region 14 is arranged on the N-type field stop buffer layer 10; the P-type collector region 12 and the N-type FRD cathode region 14 are in ohmic contact with the back metal electrode 11, and specifically, the specific form of forming the collector of the IGBT device by using the P-type collector region 12 and forming the cathode of the FRD by using the N-type FRD cathode region 14 is consistent with the prior art. In an embodiment of the present application, one P-type collector region 12 needs to correspond to one IGBT front cell unit in the front cell structure, and one N-type FRD cathode region 14 needs to correspond to one FRD front cell unit in the front cell structure.

[0074] Figure 1 and Figure 9 In the embodiment shown in the figure, two P-type collector regions 12 and one N-type FRD cathode region 14 are arranged, and at this time, the front cell structure has two IGBT front cell units and one FRD front cell unit; the front cell structure can also adopt other implementation conditions, and specifically, the selection can be made according to the needs, so as to meet the actual application requirements.

[0075] In the prior art, the P-type collector region 12 is adjacent to and in contact with the corresponding N-type FRD cathode region 14, at this time, the P-type collector region 12 and the adjacent N-type FRD cathode region 14 will have mutual influence, and it is inconvenient to effectively adjust the doping concentration of the P-type collector region 12 and the like. In order to avoid mutual influence, in an embodiment of the present application, the P-type collector region 12 and the adjacent N-type FRD cathode region 14 are isolated by using the back isolation groove 22, wherein the back isolation groove 22 penetrates the P-type collector region 12 and the N-type FRD cathode region 14, the groove bottom of the back isolation groove 22 is located in the N-type field stop buffer layer 10, that is, the depth of the back isolation groove 22 is greater than the thickness corresponding to the P-type collector region 12 and the N-type FRD cathode region 14. The P-type collector region 12, the N-type FRD cathode region 14 and the corresponding outer wall of the back isolation groove 22 are in contact.

[0076] In an embodiment of the present application, the groove bottom of the back isolation groove 22 is in a circular arc shape or a flat shape;

[0077] The back metal electrode 11 is also filled in the back isolation groove 22, and the back metal electrode 11 filled in the back isolation groove 22 is in ohmic contact with the P-type injection region 13 covering the groove bottom of the back isolation groove 22.

[0078] Figure 6 In the embodiment shown in the figure, the groove bottom of the back isolation groove 22 is in a flat shape, Figure 7An embodiment shown in FIG. 2 shows that the bottom of the back isolation trench 22 is arc-shaped. The shape of the back isolation trench 22 can be selected according to actual needs, for example, the shape of the back isolation trench 22 can be determined by process conditions, and the actual application requirements are met.

[0079] In a specific implementation, after the back isolation trench 22 is etched, the P-type injection region 13 is formed by ion implantation, the P-type injection region 13 is located in the N-type field stop buffer layer 10, and the P-type injection region 13 covers the bottom of the back isolation trench 22 in the N-type field stop buffer layer 10, as shown in FIG. 3. Figure 1 and Figure 9 Of course, the P-type injection region 13 is in contact with the P-type collector region 12 and the N-type FRD cathode region 14 which are isolated by the back isolation trench 22. The P-type injection region 13 and the P-type collector region 12 can be prepared by the same process step.

[0080] After the P-type injection region 13 is formed by ion implantation, the doping concentration of the corresponding region of the N-type field stop buffer layer 10 can be reduced. At this time, the snap back of the RC-IGBT power device can occur at a very small current, which can be ignored. By using the back isolation trench 22, the thickness of the corresponding region of the N-type field stop buffer layer 10 can be thinned. When a high voltage is applied to the back of the P-type injection region 13, it is helpful to increase the injection of boron ions on the back during the reverse recovery of the FRD, increase the softness of the reverse recovery, and improve the overall performance of the device.

[0081] In an embodiment of the present application, the front cell structure is prepared in the cell region of the substrate, and the P-type base region 4 traversing the cell region is arranged in the cell region.

[0082] The IGBT front cell units in the front cell structure are connected in parallel to form an integral whole, and an FRD front cell unit is arranged between any two adjacent IGBT front cell units, wherein

[0083] The IGBT front cell unit adopts a trench gate structure.

[0084] The FRD front cell unit includes at least two FRD unit trenches 15, and the FRD unit trench 15 is filled with FRD unit polysilicon 18. The FRD unit polysilicon 18 is insulated and separated from the inner wall of the FRD unit trench 15 by an FRD unit polysilicon insulation medium layer 19.

[0085] The bottom of the IGBT unit trench 16 in the trench gate structure and the bottom of the FRD unit trench 15 are located below the P-type base region 4. The P-type base region 4 is in contact with the corresponding outer sidewall of the IGBT unit trench 16 and the FRD unit trench 15.

[0086] The P-type base region 4 between the adjacent FRD cell trenches 15 is in ohmic contact with the FRD anode metal 8.

[0087] As can be seen from the above description, the front cell structure is prepared in the cell region, and the P-type base region 4 traverses the cell region, specifically, the P-type base region 4 is distributed in the cell region, and the P-type base region 4 generally extends from the front surface of the substrate 9 to the back surface. Figure 1 and Figure 8 In the front cell structure shown, the IGBT front cell unit adopts a trench gate structure, and when the trench gate structure is adopted, at least one IGBT cell trench 16 is included.

[0088] In one embodiment of the present application, the IGBT front cell unit further includes a trench gate polysilicon 1 filled in the IGBT cell trench 16 and an N+ emitter region 6 in contact with the outer sidewall of the IGBT cell trench 16, wherein

[0089] The trench gate polysilicon 1 is insulated and isolated from the inner wall of the IGBT cell trench 16 by a trench gate polysilicon insulation medium layer 2, and the trench gate polysilicon 1 is in ohmic contact with the gate metal layer above the substrate;

[0090] The N+ emitter region 6 is located in the P-type base region 4, and the N+ emitter region 6 and the P-type base region 4 are in ohmic contact with the emitter metal 7.

[0091] Specifically, the trench gate polysilicon 1 is filled in the IGBT cell trench 16, the trench gate polysilicon insulation medium layer 2 can generally be a silicon dioxide layer, and when the trench gate polysilicon insulation medium layer 2 is a silicon dioxide layer, it can be prepared by a thermal oxidation process. Figure 1 and Figure 8 In the embodiment, the N+ emitter region 6 is in contact with the outer sidewall of the IGBT cell trench 16, and the N+ emitter region 6 is located in a P-type base region 4 in contact with the outer sidewall of the IGBT cell trench 16, that is Figure 1 and Figure 8 In the embodiment, the IGBT cell trench 16 and the FRD cell trench 15 can be used to separate the P-type base region 4.

[0092] In order to form the gate electrode of the IGBT device, the trench gate polysilicon 1 needs to be in ohmic contact with the gate metal layer, that is, the gate electrode can be formed by using the gate metal layer and the trench gate polysilicon 1 in ohmic contact with the gate metal layer, the distribution of the gate metal layer above the substrate 9, and the gate electrode formed by using the gate metal layer in cooperation with the trench gate polysilicon 1 are consistent with the prior art. In order to form the emitter of the IGBT device, the N+emitter region 6, the P-type base region 4 where the N+emitter region is located, and the emitter metal 7 need to be in ohmic contact, and the emitter metal 7 generally needs to be insulated and separated from the trench gate polysilicon 1. The specific situation of forming the emitter by using the emitter metal 7 can be consistent with the prior art.

[0093] Figure 1 And Figure 8 In the FRD front surface cell unit, at least two FRD cell trenches 15 are included. Generally, the FRD cell trenches 15 and the IGBT cell trenches 16 can be prepared by using the same process step. The bottom of the FRD cell trench 15 and the bottom of the IGBT cell trench 16 are both located below the P-type base region 4, that is, the FRD cell trench 15 and the IGBT cell trench 16 penetrate the P-type base region 4.

[0094] The FRD cell polysilicon 18 is filled in the FRD cell trench 15, and the FRD cell polysilicon 18 is insulated and separated from the FRD cell trench 15 by the FRD cell polysilicon insulating medium layer 19. Generally, the FRD cell polysilicon 18 can be prepared by using the same process step as the trench gate polysilicon 1, and the FRD cell polysilicon insulating medium layer 19 is prepared by using the same process step as the trench gate polysilicon insulating medium layer 2.

[0095] Unlike the IGBT front surface cell, the FRD cell polysilicon insulating medium layer 19 is not in ohmic contact with the gate metal layer. The N+emitter region 6 can not be arranged on the outer sidewall of the FRD cell trench 15, or even if the N+emitter region 6 is arranged, a conductive channel cannot be formed by using the N+emitter region 6. Figure 1 And Figure 8 In order to ensure process consistency, the N+emitter region 6 is arranged on the outer sidewall of the FRD cell trench 15 adjacent to one side of the IGBT cell trench 16. At the same time, the N+emitter region 6 is not arranged on the outer sidewall between the adjacent FRD cell trenches 15.

[0096] In order to form the anode end of the FRD, the FRD anode metal 8 is in ohmic contact with the P-type base region 4 between the adjacent FRD cell trenches 15. Of course, the FRD anode metal 8 also needs to be insulated and separated from the FRD cell polysilicon 18 in the FRD cell trench 15.

[0097] As can be seen from the above description, when the N-type FRD cathode region 14 is directly opposite the FRD front cell unit, it specifically means that the N-type FRD cathode region 14 is at least opposite the P-type base region 4 in the adjacent FRD cell trench 15, and of course, the N-type FRD cathode region 14 is also opposite the FRD cell trench 15. The P-type collector region 12 is directly opposite the IGBT front cell, and specifically means that the P-type collector region 12 is at least opposite part of the IGBT cell trench 16 and the P-type base region 4 in contact with the outer sidewall of the IGBT cell trench 16, Figure 1 and Figure 8 In the above, the P-type collector region 12 also extends below the FRD cell trench 15 adjacent to the IGBT cell trench 16, and the N-type FRD cathode region 14 also extends below the corresponding FRD cell trench 15. Specifically, the above-mentioned correspondence specifically means that when projected to one side, the projection areas overlap each other, that is, spatially overlap.

[0098] In an embodiment of the present application, the emitter metal 7 is electrically connected to the corresponding P-type base region 4 through the P+ emitter metal ohmic contact region 5.

[0099] The FRD anode metal 8 is electrically connected to the corresponding P-type base region 4 through the P+ anode metal ohmic contact region 17.

[0100] The doping concentration of the P+ emitter metal ohmic contact region 5 and the P+ anode metal ohmic contact region 17 is greater than the doping concentration of the P-type base region 4.

[0101] In order to improve the reliability of the ohmic contact, the P+ emitter metal ohmic contact region 5 is used to realize the ohmic contact between the emitter metal 7 and the P-type base region 4, and the P+ anode metal ohmic contact region 17 is used to realize the ohmic contact between the FRD anode metal 8 and the P-type base region 4.

[0102] Generally, the P+ emitter metal ohmic contact region 5 and the P+ anode metal ohmic contact region 17 are prepared by the same process step. Figure 1 and Figure 8 In the above, the P+ emitter metal ohmic contact region 5 is in contact with the N+ emitter region 6 on both sides, that is, the P+ emitter metal ohmic contact region 5 and the N+ emitter region 6 are located in the same P-type base region 4, and the P+ anode metal ohmic contact region 17 is located in the P-type base region 4 between two adjacent FRD cell trenches 15.

[0103] In an embodiment of the present application, an N+ high-energy implantation layer 3 prepared in the substrate cell region is further included, wherein,

[0104] The N+ high-energy implantation layer 3 is located below the P-type base region 4, and the N+ high-energy implantation layer 3 is adjacent to the P-type base region 4.

[0105] The bottom of the IGBT unit trench 16 and the bottom of the FRD unit trench 15 are both located in the N+ high-energy implant layer 3.

[0106] Specifically, the N+ high-energy implant layer 3 has a doping concentration greater than that of the substrate 9, and the N+ high-energy implant layer 3 is adjacent to the front surface of the substrate 9. The N+ high-energy implant layer 3 also traverses the cell region, that is, is distributed in accordance with the P-type base region 4, and the N+ high-energy implant layer 3 is located below the P-type base region 4, and the N+ high-energy implant layer 3 is adjacent to the P-type base region 4, that is, the junction of the N+ high-energy implant layer 3 and the P-type base region 4 is located above the corresponding bottom of the FRD unit trench 15 and the IGBT unit trench.

[0107] Figure 1 And Figure 9 In the above-mentioned RC-IGBT device, the bottom of the IGBT unit trench 16 and the bottom of the FRD unit trench 15 are both located in the N+ high-energy implant layer 3, that is, the N+ high-energy implant layer 3 can realize the coating of the corresponding bottom of the IGBT unit trench 16 and the FRD unit trench 15.

[0108] In an embodiment of the present application, the N+ high-energy implant layer 3 is first prepared in the cell region of the substrate 9, and after the N+ high-energy implant layer 3 is prepared, the front cell process is performed on the front surface of the substrate 9 to obtain the required front cell structure, wherein,

[0109] When the N+ high-energy implant layer 3 is prepared, the energy of the N-type impurity ion implantation is 100keV-2MeV, the dose of the N-type impurity ion implantation is 5e12-1e13 orders of magnitude, and the type of the N-type impurity ion implantation includes P or H;

[0110] After the N-type impurity ion implantation, a high-temperature annealing step is performed to activate the formation of the required N+ high-energy implant layer 3, wherein the annealing temperature in the high-temperature annealing step is 900°C-1150°C.

[0111] In specific implementation, the N+ high-energy implant layer 3 is generally prepared first, and then the front cell process is performed to obtain the front cell structure. As can be seen from the above description, the front cell process is performed, that is, the process steps of preparing the IGBT unit trench 16 and the FRD unit trench 15. The N+ high-energy implant layer 3 is prepared by performing N-type impurity ion implantation on the front surface of the substrate 9.

[0112] For the above-mentioned RC-IGBT device, the present application provides a preparation method of the RC-IGBT power device, specifically for preparing the RC-IGBT power device, wherein the preparation method comprises the following steps:

[0113] A substrate 9 with an N-type conductivity is provided, and a front-side cell process is performed in the cell region of the N-type substrate 9 to prepare the desired front-side cell structure.

[0114] The substrate 9 described above is subjected to a backside implantation process to prepare an N-type field cutoff buffer layer 10 located on the backside of the substrate 9 and an N-type implantation layer prepared on the N-type field cutoff buffer layer 10.

[0115] A trench etching process is performed on the back side of the substrate 9 to prepare the required back isolation trench 22, wherein the bottom of the back isolation trench 22 extends into the N-type field cutoff buffer layer 10.

[0116] P-type impurity ions are implanted onto the back side of the substrate 9 to form an N-type FRD cathode region 14, a P-type collector region 12, and a P-type implantation region 13 using an N-type implantation layer.

[0117] The P-type injection region 13 is located within the N-type field cutoff buffer layer 10, and the back isolation trench 22 is located at the bottom of the trench within the N-type field cutoff buffer layer 10. The P-type collector region 12 corresponds to the IGBT front cell in the front cell structure, and the N-type FRD cathode region 14 corresponds to the FRD front cell in the front cell structure. The P-type collector region 12 is isolated from the adjacent N-type FRD cathode region 14 through the back isolation trench 22.

[0118] A metal deposition process is performed on the back side of the substrate 9 to form a back metal electrode 11, wherein the back metal electrode 11 is in ohmic contact with the P-type collector region 12, the N-type FRD cathode region 14 and the P-type implantation region 13.

[0119] In practice, the front-side cell process is typically performed on the front side of substrate 9 first, followed by the back-side process. Figures 2 to 9 The image shows an embodiment where the front-side cell process is performed first, followed by the back-side process. The following is a description of an embodiment where the front-side cell process is performed first, followed by the back-side process. Figures 2 to 9 The preparation method of the present invention will be specifically described in the following process steps.

[0120] In one embodiment of the present invention, after providing the substrate 9, N-type impurity ions are first implanted on the front side of the substrate 9 to obtain an N+ high-energy implantation region 21, wherein...

[0121] The energy of the injected N-type impurity ions is 2 MeV, the dose of the injected N-type impurity ions is on the order of *e12, and the types of injected N-type impurity ions include P (phosphorus) or H (hydrogen).

[0122] After the N-type impurity ion implantation, a high-temperature annealing step is performed to activate the formation of the required N+ high-energy implantation region 21, wherein the annealing temperature in the high-temperature annealing step is 1150°C;

[0123] After the N+ high-energy implantation region 21 is prepared, a front surface cell process is performed on the front surface of the substrate 9 to prepare a front surface cell structure, wherein after the front surface cell structure is prepared, the N+ high-energy implantation layer 3 is formed by using the N+ high-energy implantation region 21.

[0124] Figure 2 In the N+ high-energy implantation region 21 obtained by performing N-type impurity ion implantation on the front surface of the substrate 9, the N+ high-energy implantation region 21 extends vertically from the front surface of the substrate 9 to the back surface of the substrate 9, that is, the N+ high-energy implantation layer 3 is formed based on the N+ high-energy implantation region 21.

[0125] In specific implementation, after the N+ high-energy implantation region 21 is formed by implantation and then the final N+ high-energy implantation layer 3 is formed, the front surface carrier concentration distribution of the IGBT region can be optimized. Due to the difference between the doping concentration of the N+ high-energy implantation layer 3 and the doping concentration of the substrate 9, a potential barrier that blocks holes can be formed, which helps to reduce Vcesat. In addition, the N+ high-energy implantation layer 3 relative to the P-type base region 4 of the FRD anode can inhibit the injection efficiency of holes in the FRD front surface cell anode region, reduce the carrier concentration near the PN junction, and thus reduce the reverse recovery current peak (Irrm) and the reverse recovery time (Trr).

[0126] Figure 3 In the embodiment after the front surface cell process is performed, the trench gate polysilicon 1 filled in the IGBT cell trench 16 and the FRD cell polysilicon 18 filled in the FRD cell trench 15 are obtained. Specifically, after the N+ high-energy implantation region 21 is prepared, the P-type base region 4 is formed by ion implantation process. The conditions and process of the ion implantation process for forming the P-type base region 4 can be selected as required to obtain the P-type base region 4. The depth of the P-type base region 4 is less than the depth of the N+ high-energy implantation region 21. After the P-type base region 4, the N+ high-energy implantation layer 3 is formed by using the N+ high-energy implantation region 21 below the P-type base region 4.

[0127] The IGBT cell trench 16 and the FRD cell trench 15 can be simultaneously prepared by the commonly used trench etching process of the present technology. The depth of the IGBT cell trench 16 and the FRD cell trench 15 is less than the thickness of the N+ high-energy implantation region 21. The depth of the IGBT cell trench 16 and the FRD cell trench 15 can be 5-6 μm, and the width can be about 0.8 μm.

[0128] After forming the IGBT cell trench 16 and the FRD cell trench 15, the trench gate polysilicon insulation dielectric layer 2 and the FRD cell polysilicon insulation dielectric layer 19 are prepared, and then the trench gate polysilicon 2 and the FRD cell polysilicon 18 are prepared by polysilicon filling.

[0129] Figure 4 In the embodiment, after the trench gate polysilicon 1 and the FRD cell polysilicon 18 are prepared, the N+ emitter region 6 and the P+ emitter metal ohmic contact region 5 and the P+ anode metal ohmic contact region 17 for improving ohmic contact reliability are formed by ion implantation, respectively. Then, the process steps of dielectric layer deposition, contact hole etching and metal layer deposition are performed to form the emitter metal 7, the gate metal layer and the FRD anode metal 8, at this time, the front cell process is completed.

[0130] In the process step of the back surface, the glass substrate can be temporarily bonded with the substrate 9 after the front cell process to process the back surface of the substrate 9. Generally, the back surface of the substrate 9 needs to be thinned by the commonly used technical means in the technical field.

[0131] After the back surface of the substrate 9 is thinned and processed, N-type impurity ions such as phosphorus ions or hydrogen ions are implanted to form the N-type field stop buffer layer 10. The process conditions for forming the N-type field stop buffer layer 10 can be selected as needed, and the thickness is generally more than 5 μm.

[0132] After the N-type field stop buffer layer 10 is formed, the N-type FRD cathode region 14 and the N-type collector region 23 are formed by ion implantation on the N-type field stop buffer layer 10. The doping concentration of the N-type FRD cathode region 14 is greater than the corresponding doping concentration of the N-type collector region 23 and the N-type field stop buffer layer 10. As described above, the N-type FRD cathode region 14 corresponds to the FRD front cell in the front cell structure, and the N-type collector region 23 corresponds to the IGBT front cell in the front cell structure. The N-type FRD cathode region 14 and the N-type collector region 23 can be formed by implanting N-type impurity ions in the region corresponding to the FRD front cell. Figure 5 In the embodiment, the N-type collector region 23 is in contact with the adjacent N-type FRD cathode region 14.

[0133] Figure 6 In the embodiment, the back surface isolation trench 22 is formed by selective masking and etching. The process conditions and process for forming the back surface isolation trench 22 by trench etching can be consistent with the existing technology. Figure 6In this design, the back isolation trench 22 is located at the junction of the N-type FRD cathode region 14 and the N-type collector region 23, and the back isolation trench 22 penetrates both the N-type FRD cathode region 14 and the N-type collector region 23. In specific implementations, the back isolation trench 22 is generally located below the FRD unit trench 15, and the depth of the back isolation trench 22 is generally 3 μm. The bottom of the back isolation trench 22 can be arc-shaped or straight, such as... Figure 6 and Figure 7 As shown, the shape of the bottom of the back isolation trench 22 can be selected according to the process. The back isolation trench 22 can isolate the N-type FRD cathode region 14 from the N-type collector region 23, that is, the N-type collector region 23 does not contact the N-type FRD cathode region 14.

[0134] In practice, after etching to form the back isolation trench 22, boron (B) impurity ion implantation is performed on the back side of the substrate 9. At this stage, a mask is not required. The energy and dose of B implantation are typically on the order of *e13. After implantation, laser annealing is performed to activate the impurities. The boron implanted into the N-type FRD cathode region 14 is neutralized by a high concentration of phosphorus. After implantation into the N-type collector region 23, a P-type collector region 12 can be formed. After implantation into the back isolation trench 22, a P-type implantation region 13 is formed. Figure 8 As shown. Specifically, the process conditions for laser annealing can be selected according to actual needs, with the aim of meeting the required laser annealing activation.

[0135] Figure 8 In, it is shown Figure 7 In an embodiment where a P-shaped injection region 13 is formed after injection into the middle and back isolation trench 22, for Figure 6 The form of the back isolation groove 22 is not shown; please refer to [reference needed]. Figure 8 Examples are not provided here.

[0136] After forming the P-type collector region 12 and the P-type implantation region 13, a back metal electrode 11 is prepared by processes such as metal evaporation on the back side of the substrate 9. The back metal electrode 11 is also filled in the back isolation trench 22, forming a back metal filler 20. The back metal electrode 11 covers the P-type collector region 12 and the N-type FRD cathode region 14. At this time, the back metal electrode 11 is in ohmic contact with the P-type collector region 12 and the N-type FRD cathode region 14, and in ohmic contact with the P-type implantation region 13 through the back metal filler 20. Figure 9 As shown, at this point, the back-side fabrication process is complete, meaning the required RC-IGBT power device has been fabricated. Of course, after the back-side fabrication process is complete, the temporary bond with the glass substrate needs to be released. The method and process for releasing the temporary bond can be selected as needed, prioritizing the ability to release the temporary bond.

[0137] As can be seen from the above description, by forming the N+ high-energy ion implantation region 21 on the front surface of the substrate 9 and finally forming the N+ high-energy ion implantation layer 3, the carrier distribution of the formed IGBT and FRD can be optimized, the Vcesat is reduced, and the Irrm of the FRD is also reduced, so that the product is more suitable for the scheme of motor control.

[0138] The isolation groove 22 on the back surface can realize the isolation of the P-type collector region 12 and the N-type FRD cathode region 14, avoid the mutual influence between the FRD region and the IGBT region in the RC-IGBT, and more accurately control the effective width and doping concentration of each region on the back surface, especially the IGBT region, so as to optimize the use of the IGBT collector region to improve the overall performance of the IGBT.

[0139] For the RC-IGBT power device, the reason for the snap back is that when the current flows through the path from the front surface to the back surface, there will be a voltage drop between the P-type region (the P-type collector region 12 and the P-type implantation region 13) and the N-type field stop buffer layer 10 on the back surface. When the voltage drop is greater than 0.7V, the back surface PN junction is forward biased, and enters the IGBT mode, which shows a decrease in voltage Vce. In an embodiment of the present application, when forming the P-type collector region 12 and the P-type implantation region 13, the back surface of the substrate 9 is subjected to P-type impurity ion implantation, which can reduce the doping concentration of the region at the bottom of the back surface isolation groove 22 in the N-type field stop buffer layer 10, and increase the resistivity of the region at the bottom of the back surface isolation groove 22 in the N-type field stop buffer layer 10. At this time, a voltage drop of 0.7V can also be achieved under small current, that is, the boron implantation on the back surface of the IGBT can also be triggered under small current, so that the snapback of the RC-IGBT power device can occur under very small current, which can be ignored.

[0140] When the FRD recovers in the reverse direction, the back surface is in a high-voltage state. Due to the existence of the back surface P-type implantation region 13, holes will be injected to the front surface. If the concentration of the N-type field stop buffer layer 10 is reduced, it is equivalent to increasing the injection efficiency of the holes on the back surface. The injection of the holes can delay the process of the FRD turn-off, which shows an increase in the reverse recovery softness; avoid the overvoltage peak caused by the superposition of high di / dt and large system inductance, and damage the system.

Claims

1. An RC-IGBT power device, comprising a substrate having a first conductivity type, a front cell structure fabricated on the front side of the substrate, and a back structure fabricated on the back side of the substrate, the back structure comprising a first conductivity type field cutoff buffer layer fabricated on the back side of the substrate, a first conductivity type FRD cathode region fabricated on the first conductivity type field cutoff buffer layer, and a second conductivity type collector region fabricated on the first conductivity type field cutoff buffer layer, wherein, The second conductivity type collector region corresponds directly to the corresponding IGBT front cell unit within the front cell structure; the first conductivity type FRD cathode region corresponds directly to the corresponding FRD front cell unit within the front cell structure; and the second conductivity type collector region is adjacent to the first conductivity type FRD cathode region. Its characteristic is: It also includes a back isolation trench for isolating the second conductivity type collector area and the first conductivity type FRD cathode area adjacent to the second conductivity type collector area. The outer wall of the back isolation trench is in contact with the isolated second conductivity type collector area and the first conductivity type FRD cathode area. The bottom of the back isolation trench extends into the first conductivity type field cutoff buffer layer, and the bottom of the back isolation trench is covered by the second conductivity type injection area located in the first conductivity type field cutoff buffer layer. The second conductivity type injection region is in contact with the second conductivity type collector regions on both sides of the back isolation trench and the first conductivity type FRD cathode region. The second conductivity type collector region, the first conductivity type FRD cathode region, and the second conductivity type injection region are all in ohmic contact with the back metal electrode.

2. The RC-IGBT power device according to claim 1, characterized in that: The bottom of the back isolation trench is arc-shaped or straight; The back metal electrode is also filled in the back isolation trench, and the back metal electrode filled in the back isolation trench makes ohmic contact with the second conductivity type injection area covering the bottom of the back isolation trench.

3. The RC-IGBT power device according to claim 1, characterized in that: The front cell structure is fabricated in the cell region of the substrate, and a second conductivity type base region is disposed in the cell region, which traverses the cell region; Within the frontal cell structure, the IGBT frontal cell units are interconnected in parallel, and an FRD frontal cell unit is placed between any two adjacent IGBT frontal cell units. The IGBT front-side cell unit adopts a trench gate structure; The front cell of the FRD includes at least two FRD cell trenches, and the FRD cell trenches are filled with FRD cell polysilicon. The FRD cell polysilicon is insulated and isolated from the inner wall of the FRD cell trench by an FRD cell polysilicon insulating dielectric layer. The bottom of the IGBT unit trench and the bottom of the FRD unit trench in the trench gate structure are both located below the base region of the second conductivity type, and the base region of the second conductivity type is in contact with the corresponding outer wall of the IGBT unit trench and the FRD unit trench. The base region of the second conductivity type between adjacent FRD cell trenches is in ohmic contact with the FRD anode metal.

4. The RC-IGBT power device according to claim 3, characterized in that: It also includes a first conductivity type high-energy injection layer fabricated within the substrate cell region, wherein, The first conductivity type high-energy injection layer is located below the second conductivity type base region, and the first conductivity type high-energy injection layer is adjacent to the second conductivity type base region; The bottom of both the IGBT cell trench and the FRD cell trench is located within the high-energy injection layer of the first conductivity type.

5. The RC-IGBT power device according to claim 3 or 4, characterized in that: For the IGBT front-side cell, it also includes trench gate polysilicon filled within the IGBT cell trench and a first conductivity type emitter region contacting the outer wall of the IGBT cell trench, wherein, The trench gate polysilicon is insulated from the inner wall of the trench of the IGBT cell through the trench gate polysilicon insulating dielectric layer, and the trench gate polysilicon is in ohmic contact with the gate metal layer above the substrate. The first conductivity type emitter region is located within the second conductivity type base region, and both the first conductivity type emitter region and the second conductivity type base region are in ohmic contact with the emitter metal.

6. The RC-IGBT power device according to claim 5, characterized in that: The emitter metal is electrically connected to the corresponding base region of the second conductivity type through the ohmic contact region of the emitter metal of the second conductivity type; The FRD anode metal is electrically connected to the corresponding second conductivity type base region through the ohmic contact region of the second conductivity type anode metal; The doping concentrations of the emitter metal ohmic contact region and the anode metal ohmic contact region of the second conductivity type are both greater than the doping concentration of the base region of the second conductivity type.

7. The RC-IGBT power device according to claim 4, characterized in that: First, a high-energy injection layer of the first conductivity type is prepared within the cellular region of the substrate. After preparing the first conductivity type high-energy injection layer, a front-side cellular process is performed on the front side of the substrate to prepare the desired front-side cellular structure. When preparing a high-energy implantation layer of the first conductivity type, the energy of the implanted first conductivity type impurity ions is 2MeV, the dose of the implanted first conductivity type impurity ions is on the order of *e12, and the type of the implanted first conductivity type impurity ions includes P or H; After the first conductivity type impurity ions are implanted, a high-temperature annealing step is performed to activate and form the desired first conductivity type high-energy implanted layer, wherein the annealing temperature in the high-temperature annealing step is 1150°C.

8. A method for fabricating an RC-IGBT power device, characterized in that, The method for fabricating the RC-IGBT power device according to claim 1 includes the following steps: A substrate having a first conductivity type is provided, and a front-side cell process is performed in the cell region of the substrate of the first conductivity type to prepare the desired front-side cell structure; The substrate described above is subjected to a backside implantation process to prepare a first conductivity type field cutoff buffer layer located on the backside of the substrate and a first conductivity type implantation layer prepared on the first conductivity type field cutoff buffer layer. A trench etching process is performed on the back side of the above substrate to prepare the required back isolation trench, wherein the bottom of the back isolation trench extends into the first conductivity type field cutoff buffer layer. Impurity ions of a second conductivity type are implanted onto the back side of the substrate to form a first conductivity type FRD cathode region, a second conductivity type collector region, and a second conductivity type implantation region using a first conductivity type implantation layer. The second conductivity type injection area is located within the first conductivity type field cutoff buffer layer, and the back isolation trench is located at the bottom of the trench within the first conductivity type field cutoff buffer layer. The second conductivity type collector area corresponds to the IGBT front cell in the front cell structure, and the first conductivity type FRD cathode area corresponds to the FRD front cell in the front cell structure. The second conductivity type collector area is isolated from the adjacent first conductivity type FRD cathode area through the back isolation trench. A metal deposition process is performed on the back side of the substrate to form a back metal electrode, wherein the back metal electrode is in ohmic contact with the second conductivity type collector region, the first conductivity type FRD cathode region, and the second conductivity type injection region in the back isolation trench.

9. The method for fabricating the RC-IGBT power device according to claim 8, characterized in that, After providing the substrate, impurity ions of the first conductivity type are implanted on the front side of the substrate to obtain a high-energy implantation region of the first conductivity type. The energy of the first type of conductivity impurity ions injected is 100keV to 2MeV, the dose of the first type of conductivity impurity ions injected is on the order of 5e12 to 1e13, and the types of N-type impurity ions injected include P or H. After the first type of conductivity impurity ions are implanted, a high-temperature annealing step is performed to activate and form the desired first type of conductivity high-energy implantation region. The annealing temperature in the high-temperature annealing step is 900℃~1150℃. After the first conductivity type high-energy injection region is prepared, a front cell process is performed on the front side of the substrate to prepare a front cell structure. After the front cell structure is prepared, a first conductivity type high-energy injection layer is formed using the first conductivity type high-energy injection region.

10. The method for fabricating the RC-IGBT power device according to claim 9, characterized in that, The front cell structure is fabricated in the cell region of the substrate, and a second conductivity type base region is disposed in the cell region, which traverses the cell region; The frontal cell structure includes several IGBT frontal cell units arranged in parallel and FRD frontal cell units distributed between any two adjacent IGBT frontal cell units, wherein, The IGBT front-side cell unit adopts a trench gate structure; The front cell of the FRD includes at least two FRD cell trenches, and the FRD cell trenches are filled with FRD cell polysilicon. The FRD cell polysilicon is insulated and isolated from the inner wall of the FRD cell trench by an FRD cell polysilicon insulating dielectric layer. The bottom of the IGBT unit trench and the bottom of the FRD unit trench in the trench gate structure are both located below the base region of the second conductivity type, and the base region of the second conductivity type is in contact with the corresponding outer wall of the IGBT unit trench and the FRD unit trench. The base region of the second conductivity type between adjacent FRD cell trenches is in ohmic contact with the FRD anode metal. The bottoms of the IGBT unit trenches and the corresponding FRD unit trenches are located within the high-energy injection layer of the first conductivity type.

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