A power constant multifunction logic circuit based on mask control

Abstract

The application relates to a constant-power-consumption multifunctional logic circuit based on mask control and belongs to the field of circuit electronics. The application comprises a double-track logic circuit, a power consumption balancing module and a mask; the double-track logic circuit is used for controlling signal transmission and realizing corresponding logic functions; the output of the mask control signal, the randomness of the mask and the power consumption balancing module are used for increasing the power consumption attack resistance of the circuit. Two logic function circuit structures are integrated in a double-track circuit, the output of different logic functions is controlled by using the mask, the logic units involved realize constant power consumption on the basis of random jumping of the output signal, the randomness of the mask, the double-track structure and the power consumption balancing module are used for improving the power consumption attack resistance, the inherent properties of the mask are used for controlling the output of MOS tubes to realize output of two logic functions under the same double-track structure, the average power consumption and the circuit cost can be reduced on the basis of improving the power consumption attack resistance of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of circuit electronics technology and relates to a multifunctional logic circuit with constant power consumption based on mask control. Background Technology

[0002] After the concept of side-channel power analysis (DPA) attacks was proposed in the 1990s, cryptanalysis research opened up a completely new perspective. Power analysis attacks are non-intrusive side-channel attack techniques whose main purpose is to obtain the non-public keys used in cryptographic chips. Differential power analysis (DPA) attacks, a hypothesis-testing technique based on statistical analysis, pose a significant threat to cryptographic chips because they can significantly reduce the noise impact of power consumption. Consequently, more and more researchers have developed protection strategies against DPA. Currently, mainstream countermeasures include dual-track pre-charging technology and masking-based techniques, the main goal of which is to make the power consumption equal when processing different data in each clock cycle, making the power consumption independent of the data being processed. However, experiments have shown that some anti-power-attack circuit structures have drawbacks such as inconsistent power consumption and high cost.

[0003] By changing the input signal, it was found that the traditional dual-rail precharge logic circuit does not have good power consumption constantness, based on the following... Figure 2 The traditional dual-rail precharge logic circuit shown is as follows: Figure 3 The proposed LBDL circuit structure has a different number of MOSFETs that are turned on when the input signal is different. For example... Figure 1 During the circuit evaluation stage, when the input signal (a,b) is (1,1), MOSFET N5 in the circuit is turned on, and the circuit outputs a signal through N5. When the input signal (a,b) is (0,0), MOSFETs P1, P3, P5, and N6 in the circuit all discharge and output signals, resulting in different power consumption under different input signal conditions. The mask-type circuit proposed based on the dual-rail structure and LBDL structure has been experimentally proven to still have the problem of inconsistent power consumption. Furthermore, both structures introduce a large number of MOSFETs. Additionally, the two structures mentioned above can only implement one logic function using a single dual-rail circuit; to implement multiple logic functions, a new logic circuit needs to be designed, which to some extent increases the average power consumption and circuit cost. Summary of the Invention

[0004] The purpose of this invention is to propose a power-constant multifunctional logic circuit based on mask control, which uses input signals to realize the logic function output of the circuit; introduces a mask to increase the circuit's resistance to power consumption attacks; and uses a mask to increase the circuit's multifunctional logic output.

[0005] This invention includes a dual-track logic circuit, a power balancing module, and a mask. The dual-track logic circuit controls signal transmission to achieve corresponding logical functions. The mask controls signal output, and its randomness, along with the power balancing module, enhances the circuit's resistance to power consumption attacks. By integrating two logic functions into a single dual-track circuit and using a mask to control the output of different logic functions, the power consumption of the involved logic units remains constant despite random changes in the output signal.

[0006] This invention is based on a dual-track precharge logic circuit structure, including AND / NAND circuits, OR / NOR circuits, a mask, and a power balancing module. The AND / NAND circuits and OR / NOR circuits control the on / off state of MOSFETs according to the input signal, realizing the corresponding circuit logic function. A mask is set between the logic circuit and the power balancing module to increase the circuit's resistance to power consumption attacks. The power balancing module is used to balance the power consumption differences caused by the different number of MOSFETs conducting due to different input signals in the circuit.

[0007] The AND / NAND circuit and OR / OR NOT circuit both include three MOSFETs. The gate of each MOSFET serves as the signal input terminal. The sources and drains of two MOSFETs are connected in series and then connected in parallel with another MOSFET. The power supply voltage is input to the drain parallel terminal.

[0008] Each AND / NAND circuit and OR / OR NOT circuit is connected in series with a mask, which is a MOS transistor; the source of each AND / NAND circuit and OR / OR NOT circuit is connected in parallel to the drain of the mask, and the gate of the mask is input with a random signal.

[0009] A mask is connected in series with the AND / NAND circuit, and a mask is connected in series with the OR / OR NOT circuit and then in parallel. The drains of the MOS transistors of the AND / NAND circuit and the OR / OR NOT circuit are connected in parallel and then connected to the power supply. The sources of the two masks are connected in parallel and then used as the output terminal of the logic circuit to output or invert the output signal.

[0010] The power balancing module includes four MOSFETs. The gates of the four MOSFETs serve as signal input terminals. The four MOSFETs are connected in series in pairs and then in parallel. The drains of the MOSFETs in the power balancing module are connected in parallel and then connected to the output terminal of the logic circuit. The sources of the MOSFETs in the power balancing module are connected in parallel and then connected to the power supply.

[0011] This invention is based on a traditional dual-rail precharge logic circuit. It utilizes the same number of MOSFETs to implement AND / NAND and OR / OR NOT logic functions on the original dual-rail structure. To eliminate power consumption differences caused by varying the number of MOSFETs on due to different input signals, a constant power consumption module is added to the circuit, increasing its resistance to power consumption attacks. A masking technique is introduced, leveraging the randomness of the mask to increase the random transitions of the output signal, further enhancing its resistance to power consumption attacks. Utilizing the unique properties of the mask itself, the on / off state of the MOSFETs is controlled. Within a single dual-rail circuit structure, the mask enables the output of two gate logic functions, while simultaneously reducing the average energy consumption and the number of transistors per switch.

[0012] This invention utilizes the randomness of the mask, a dual-track structure, and a power balancing module to improve resistance to power consumption attacks. Simultaneously, it leverages the inherent properties of the mask to control the output of the MOSFET, enabling two different logic functions to be output within the same dual-track structure. While improving the circuit's power consumption resistance, it also reduces average power consumption and circuit cost. Attached Figure Description

[0013] Figure 1 Precharge logic DP for traditional single-rail differential transmission transistors 2 L or gate circuit diagram;

[0014] Figure 2 Precharge logic DP for traditional dual-track differential transmission transistors 2 L-OR / OR NOT gate circuit diagram;

[0015] Figure 3 This is a diagram of a lookup table-based differential logic LBDL dual-track AND / NAND circuit.

[0016] Figure 4 This is a circuit diagram of a differential logic MLBDL based on a mask lookup table;

[0017] Figure 5 Precharge MDP for mask-based differential transmission transistors 2 L-track or logic circuit diagram;

[0018] Figure 6 Precharge MDP for mask-based differential transmission transistors 2 L-shaped dual-track OR / OR NOT gate circuit diagram;

[0019] Figure 7-1 This is the upper part of the circuit structure of the MCPCL, a constant power consumption multifunctional logic circuit based on mask control, according to the present invention.

[0020] Figure 7-2 This is the lower circuit structure of the MCPCL (Multifunctional Logic Circuit) based on mask control, which is a constant power consumption multifunctional logic circuit according to the present invention.

[0021] Figure 8 It is a single-track AND and NAND gate structure;

[0022] Figure 9 It is a single-track OR or NOR gate structure;

[0023] Figure 10 For power balancing modules;

[0024] Figure 11-1 The instantaneous current measured by the MCPCL when the input signal (A,B) is (1,1);

[0025] Figure 11-2 The instantaneous current measured by the MCPCL when the input signal (A,B) is (0,0);

[0026] Figure 11-3 The instantaneous current measured by the MCPCL when the input signal (A,B) is (0,1);

[0027] Figure 11-4 The instantaneous current measured by the MCPCL when the input signal (A,B) is (1,0). Detailed Implementation

[0028] The present invention will be further described below with reference to the accompanying drawings.

[0029] like Figure 7-1 and 7-2 As shown, a power-constant multifunctional logic circuit based on mask control is based on a dual-track pre-charge logic circuit structure, including AND / NAND circuits, OR / OR NOT circuits, and a power balancing module.

[0030] like Figure 8 As shown, both AND and NAND gates include three MOSFETs, and the principles of AND and NAND gates are the same. For example, when the input signal (A,B) is (0,0), NMOS transistors N1 and N4 are turned on, and the voltage signal is transmitted from the drain to the source of N1 and N4; when the input signal (A,B) is (1,1), N1, N3, N4, and N6 are turned off, and no high-level signal is transmitted.

[0031] The circuit structure that controls the on / off state of the MOSFET based on the input signal achieves the AND / NAND logic function.

[0032] like Figure 9 As shown, both OR and NOR gates include three MOSFETs, and the principles of OR and NOR gates are the same. For example, when the input signal (A,B) is (0,0), NMOS transistors N2 and N5 are turned on, and the voltage signal is transmitted from the drain to the source of N2 and N5; when the input signal (A,B) is (1,1), N1 and N4 are turned on, and the voltage signal is transmitted from the drain to the source and output.

[0033] The circuit structure that controls the on / off state of the MOSFET based on the input signal achieves the logic function of OR / OR NOT.

[0034] like Figure 10 As shown, the power balancing module includes four MOSFETs. When the input signal (A, B) is any value, only two fixed number of MOSFETs are turned on and no high-level signal is output.

[0035] The power balancing module is used to balance the power consumption difference in a circuit caused by the different number of MOSFETs being turned on due to different input signals;

[0036] Simultaneously, a mask is set between the logic circuit and the power balancing module; the mask is used... Signal representation. In the upper and lower structures, the masks control the on or off of the two MOSFETs respectively. For example, in the upper part of the MCPCL structure, the mask... When N4 is turned off and N8 is turned on, the signal is transmitted from the drain to the source. Since the mask is a random signal, the output signal has random jump characteristics, which increases the circuit's resistance to power consumption attacks.

[0037] In practice, to eliminate the power consumption differences of MOSFETs caused by different input signals in the upper part of the logic circuit of the MCPCL, when the mask m=1, MOSFETs N2 and N11 are turned on when the input signal (A,B) is (0,0); MOSFETs N1 and N9 are turned on when the input signal (A,B) is (1,1); MOSFETs N1 and N11 are turned on when the input signal (A,B) is (1,0); and MOSFETs N2, N3, and N9 are turned on when the input signal (A,B) is (0,1). At the same time, existing masking technology is introduced to increase the random jump of the output signal and increase the circuit's resistance to power consumption attacks.

[0038] Based on the above structure, the unique properties of the mask itself are used to control the conduction and shutdown of the MOSFET. In a dual-rail circuit structure, the mask is used to control two gate logic functions.

[0039] when Figure 7-1 and 7-2 When the mask values ​​(m, n) shown are different, the circuit will output different logic functions. When the mask m = n = 1, the circuit's logic output is OR / NOR; when the mask m = n = 0, the circuit's logic output is AND / NAND. That is, when the mask values... When the value is (0, 0, 1, 1) or (1, 1, 0, 0), transistors N4 or N8 in the circuit are turned on, and the circuit outputs an AND-NAND / OR-NOR logic value; when the mask value in the circuit is... When the circuit is one of the four cases (1, 0, 0, 0), (0, 1, 0, 0), (0, 0, 1, 0), and (0, 0, 0, 1), it can be used as a mask-based constant power circuit with a single logic function. By controlling the conduction of the MOS through the mask value, the circuit can output positive and negative logic values ​​under the control of different mask values.

[0040] Because the value of the mask is random (meaning that all possible values ​​of the mask are equal), even if an attacker knows the input signal, they cannot accurately know the result, thus effectively enhancing the circuit's resistance to power consumption attacks.

[0041] By reducing the average energy consumption and the number of transistors during each circuit switch, the proposed mask-controlled, constant-power multifunctional logic circuit, based on experimental data and theoretical analysis, exhibits good power consumption constancy under different input signals. Furthermore, it can realize different circuit logic functions based on the unique properties of the mask.

[0042] To verify the effectiveness of this invention, under the same experimental environment and using the same experimental parameters, existing power-constant logic structures, including: Figure 3 The differential logic circuit LBDL based on lookup table shown is as follows: Figure 5 and 6 The mask-based differential transfer transistor precharge circuit MDP shown is 2 L, such as Figure 4 The differential logic MLBDL based on a mask lookup table is compared with the MCPCL based on mask control of this invention, which features constant power consumption. Under the same experimental parameters, the magnitude of the output current generated by different input signals is collected. According to the power consumption formula P = U * I, when U is uniquely determined, the power consumption P is only related to the current I. Therefore, the measured current curve can reflect the magnitude of the power consumption.

[0043] To verify the effectiveness of the circuit structure proposed in this invention against power consumption attacks, two parameters, Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD), were selected as evaluation indicators. The magnitude of these values ​​represents the level of resistance to power consumption attacks (where the smaller the values ​​of NED and NSD, the higher the level of resistance to power consumption attacks). Figures 11-1 to 11-4 As shown, the instantaneous current of the measuring circuit is measured when the input signal is different at different times (where the input signal (a,b) is (1,1) when the sampling time is 5ns; (a,b) is (0,0) when the sampling time is 10ns; (a,b) is (0,1) when the sampling time is 15ns; and (a,b) is (1,0) when the sampling time is 20ns).

[0044] The calculation method for NED is as follows:

[0045]

[0046] The NSD is calculated as follows:

[0047]

[0048] Where σ is the standard deviation, calculated as follows:

[0049]

[0050] Where E # E represents the power consumption measured for each input signal. avg The average power consumption is represented by max(E) and min(E), which correspond to the maximum and minimum power consumption values ​​collected, respectively.

[0051] Considering the diversity of circuit logic functions in the comparison schemes, the comparison of different structures is based on the circuit's logic function, categorized into AND-GATE, NAND-GATE, OR-GATE, and NOR-GATE circuits. Instantaneous current of the circuits is collected at different times. The experimental results comparing the circuit structure of this invention with other circuit structures in terms of resistance to power consumption attacks are shown in Tables 1, 2, 3, and 4.

[0052] Table 1. Comparison of AND-GATE Data

[0053]

[0054] Table 2 Comparison Chart of NAND-GATE Data

[0055]

[0056] Table 3 Comparison Chart of OR-GATE Data

[0057]

[0058] Table 4. Comparison of NOR-GATE Data

[0059]

[0060] Analyzing the experimental data collected in Table 1 (AND-GATE data comparison chart), when the circuit's logic function is AND-gate, the proposed MCPCL circuit structure compares with MDP. 2 The average power consumption of L and MLBDL structures decreased by 29.76% and 43.65%, respectively; compared with LBDL and MDP... 2The NED of the L and MLBDL structures decreased by 33.47%, 11.42%, and 11.67%, respectively; the NSD decreased by 40.61%, 31.53%, and 14.91%, respectively. The lower the NED and NSD values, the higher the power consumption resistance of the circuit, the lower the average power consumption of the circuit, and the lower the cost of the circuit. Similarly, the comparison results in Tables 2 to 4 can be obtained.

Claims

1. A power-constant multifunctional logic circuit based on mask control, characterized in that: The circuit includes a dual-track logic circuit, a power balancing module, and a mask. The dual-track logic circuit controls signal transmission to achieve corresponding logic functions. The mask controls signal output, and its randomness, along with the power balancing module, enhances the circuit's resistance to power consumption attacks. Two logic functions are integrated into a single dual-track circuit, and the mask controls the output of different logic functions, ensuring constant power consumption even with random signal transitions in the relevant logic units. The dual-track logic circuit includes AND / NAND and OR / OR NOT circuits. These circuits control the on / off state of MOSFETs based on input signals to achieve corresponding circuit logic functions. A mask is placed between the logic circuit and the power balancing module to increase the circuit's resistance to power consumption attacks. The power balancing module balances the power consumption differences caused by varying numbers of MOSFETs conducting due to different input signals. The AND / NAND circuit and OR / OR NOT circuit both include three MOSFETs. The gate of each MOSFET serves as the signal input terminal. The sources and drains of two MOSFETs are connected in series and then connected in parallel with another MOSFET. The power supply voltage is input to the drain parallel terminal. Each AND / NAND circuit and OR / OR NOT circuit is connected in series with a mask, which is a MOS transistor; the source of each AND / NAND circuit and OR / OR NOT circuit is connected in parallel to the drain of the mask, and the gate of the mask is input with a random signal. A mask is connected in series with the AND / NAND circuit, and a mask is connected in series with the OR / OR NOT circuit and then in parallel. The drains of the MOS transistors of the AND / NAND circuit and the OR / OR NOT circuit are connected in parallel and then connected to the power supply. The sources of the two masks are connected in parallel and then used as the output terminal of the logic circuit to output or invert the output signal. The power balancing module includes four MOSFETs. The gates of the four MOSFETs serve as signal input terminals. The four MOSFETs are connected in series in pairs and then in parallel. The drains of the MOSFETs in the power balancing module are connected in parallel and then connected to the output terminal of the logic circuit. The sources of the MOSFETs in the power balancing module are connected in parallel and then connected to the power supply.

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