Pipeline successive approximation analog-to-digital converter, integrated circuit and electronic device

Abstract

The present invention provides a pipelined successive approximation analog-to-digital converter, an integrated circuit, and an electronic device. The pipelined successive approximation analog-to-digital converter comprises: a first-stage successive approximation analog-to-digital converter, an interstage gain amplifier, a second-stage successive approximation analog-to-digital converter, and a digital encoding unit. In an embodiment of the present invention, a second digital-to-analog converter in the second-stage successive approximation analog-to-digital converter is provided with a gain-halving capacitor, and the capacitance of the gain-halving capacitor is the sum of the capacitance values ​​of the remaining capacitors in the second digital-to-analog converter. This enables implementation of a two-stage interstage gain-halving technique, reduces the gain of the interstage gain amplifier, and maintains the positive reference voltage of the second-stage successive approximation analog-to-digital converter consistent with the positive reference voltage of the first-stage successive approximation analog-to-digital converter without being halved, effectively reducing power consumption and increasing conversion speed. Furthermore, the converter is adaptable to deep submicron CMOS processes.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a pipeline successive approximation analog-to-digital converter, an integrated circuit and an electronic device. Background Art

[0002] Pipelined Successive Approximation Register Analog to digital converter (Pipelined SAR ADC) has been widely used in various analog-to-digital converter scenarios due to its high speed and high precision. Pipeline SAR ADC usually includes at least two stages of SAR ADC. Each stage of SAR ADC includes a digital-to-analog converter (DAC), a comparator, and a SAR control logic unit. An interstage gain amplifier is provided between the DACs of two adjacent SAR ADC stages to amplify the sampled residual signal of the previous stage SAR ADC and transmit it to the next stage SAR ADC. In deep submicron CMOS processes, the intrinsic gain of transistors gradually decreases, making it difficult for the interstage gain amplifier to achieve high-gain linear amplification. To address this technical problem, related technologies propose reducing the reference voltage in the next stage ADC to half of the reference voltage in the previous stage ADC to achieve a two-stage interstage gain halving technology and reduce the gain of the interstage gain amplifier. However, halving the reference voltage will greatly reduce the conversion speed and power consumption of the ADC. Summary of the Invention

[0003] Embodiments of the present invention provide a pipelined successive approximation analog-to-digital converter, an integrated circuit, and an electronic device for halving the inter-stage gain without halving the reference voltage, thereby improving the conversion speed and power consumption of the ADC.

[0004] In a first aspect, an embodiment of the present invention provides a pipelined successive approximation analog-to-digital converter, comprising:

[0005] A first-stage successive approximation analog-to-digital converter, the first-stage successive approximation analog-to-digital converter comprising a first digital-to-analog converter, a first comparator, and a first digital control logic unit connected in sequence, wherein the first digital-to-analog converter comprises a first capacitor array, the first capacitor array comprising a first fill capacitor and M first capacitors, the first ends of the first fill capacitor and each first capacitor being respectively connected to an analog input voltage, the second ends of each first capacitor being respectively connected to a positive reference voltage and a negative reference voltage via a multiplexer, and the second end of the first fill capacitor being connected to the negative reference voltage; the capacitance value of the first fill capacitor being equal to the capacitance value of the first capacitor among the M first capacitors, and the capacitance values ​​of the M first capacitors increasing in order from the smallest to the largest number of bits by a power of 2, where M is an integer greater than 1;

[0006] an inter-stage gain amplifier, wherein an input terminal of the inter-stage gain amplifier is connected to the residual voltage output from the first digital-to-analog converter;

[0007] a second-stage successive approximation analog-to-digital converter, the second-stage successive approximation analog-to-digital converter comprising a second digital-to-analog converter, a second comparator, and a second digital control logic unit connected in sequence, the second digital-to-analog converter comprising a second capacitor array, the second capacitor array comprising a gain-halving capacitor, a second offset capacitor, and an N-1-bit second capacitor, the first ends of the gain-halving capacitor, the second offset capacitor, and each of the second capacitors being respectively connected to the output end of the inter-stage gain amplifier, the second end of each of the second capacitors being respectively connected to a positive reference voltage and a negative reference voltage through a multiplexer, the second ends of the gain-halving capacitor and the second offset capacitor being respectively connected to the negative reference voltage, the capacitance value of the second offset capacitor being equal to the capacitance value of the first capacitor among the N-1-bit second capacitors, and the capacitance value of the N-1-bit second capacitors increasing in order of powers of 2 from small to large according to the number of bits, the capacitance value of the gain-halving capacitor being the sum of the capacitance values ​​of the N-1-bit second capacitors and the second offset capacitor, where N is an integer greater than 1;

[0008] A digital encoding unit is connected to the output ends of the first digital control logic unit and the second digital control logic unit.

[0009] In a second aspect, an embodiment of the present invention provides an integrated circuit, comprising the pipelined successive approximation analog-to-digital converter as described in the first aspect above.

[0010] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the integrated circuit as described in the second aspect above.

[0011] In the embodiment of the present invention, a gain-halving capacitor is provided in the second digital-to-analog converter in the second-stage successive approximation analog-to-digital converter, and the capacitance value of the gain-halving capacitor is the sum of the capacitance values ​​of the remaining capacitors in the second digital-to-analog converter. This can realize the inter-stage gain-halving technology of the two-stage structure, reduce the gain of the inter-stage gain amplifier, and the positive reference voltage of the second-stage successive approximation analog-to-digital converter is consistent with the positive reference voltage of the first-stage successive approximation analog-to-digital converter, without the need for halving, effectively reducing power consumption and increasing conversion speed, and being adaptable to deep submicron CMOS processes. The analog input signal is amplified and quantized by the two-stage successive approximation analog-to-digital converter and the inter-stage amplifier to generate an (M+N)-bit digital signal, and finally outputs an (M+N-1)-bit digital signal through the digital encoding unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a schematic diagram of a pipelined successive approximation analog-to-digital converter provided by one embodiment of the present invention;

[0013] Figure 2 1 is a schematic diagram of the circuit structure of a first-stage successive approximation analog-to-digital converter provided by one embodiment of the present invention;

[0014] Figure 3 1 is a circuit diagram of a second-stage successive approximation analog-to-digital converter provided by an embodiment of the present invention;

[0015] Figure 4 It is a schematic diagram of the encoding process of a digital encoding unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] It should be understood that in the description of the embodiments of the present invention, if there is a description of "first", "second", etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. "At least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can indicate the existence of A alone, the existence of A and B at the same time, and the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any group of these items, including any combination of single or plural items. For example, at least one of a, b and c can represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c can be single or multiple.

[0018] To facilitate understanding of the technical solutions of the embodiments of the present invention, the following first briefly introduces relevant technologies of pipelined successive approximation analog-to-digital converters.

[0019] The pipelined successive approximation analog-to-digital converter generally includes a multi-stage SAR ADC and a device for encoding a digital signal output by the multi-stage SAR ADC, and outputting a final digital signal obtained by converting an analog input signal.

[0020] Each SAR ADC stage consists of three main components: a digital-to-analog converter (DAC), a comparator, and SAR control logic. The basic operating principle of each SAR ADC stage is as follows: in the first sampling cycle, the DAC's most significant bit (MSB) is set to 1, and the remaining bits are set to 0. The comparator compares the analog input voltage with the initial value of the DAC output voltage (typically half the full-scale voltage). If the analog input voltage is greater than the DAC output voltage, the current bit is encoded as 1, and the DAC's switching state remains unchanged. If the analog input voltage is less than the DAC output voltage, the current bit is encoded as 0, and the DAC's switching state returns to its pre-action state. The SAR logic then shifts to the next bit, changing the DAC's switching state again and comparing it with the analog input voltage. This cycle repeats until the last bit is compared, resulting in the complete A / D conversion code. The core principle of the SAR ADC's operating principle is binary division. Each change in the DAC output voltage is halved, gradually approximating the analog input voltage to achieve analog-to-digital conversion.

[0021] For a pipelined successive approximation analog-to-digital converter, an inter-stage gain amplifier is provided between the DACs of two adjacent SAR ADCs. The inter-stage gain amplifier is used to amplify the remainder (residual voltage) of the analog input voltage of the previous SAR ADC and use it as the analog input of the next SAR ADC.

[0022] In deep submicron CMOS processes, the intrinsic gain of transistors gradually decreases, making it difficult for the interstage gain amplifier to achieve high-gain linear amplification. To address this technical problem, related technologies propose reducing the reference voltage in the subsequent SAR ADC to half of the reference voltage in the previous SAR ADC to achieve a two-stage interstage gain halving technology, thereby reducing the gain of the interstage gain amplifier. For example, if the number of bits of the previous SAR ADC is M bits, the gain factor of the interstage gain amplifier should generally be set to at least 2. M-1 , and after adopting the interstage gain halving technology, the amplification factor of the interstage gain amplifier can be reduced to 2 M-2 However, halving the inter-stage gain by halving the reference voltage will greatly reduce the ADC's conversion speed and power consumption.

[0023] In summary, the drawback of conventional pipelined successive approximation analog-to-digital converters (ADCs) with two or more stages is the high gain of the inter-stage gain amplifier, making them unsuitable for deep submicron CMOS processes. Related technologies reduce the reference voltage, which, while enabling inter-stage gain halving, limits the overall speed and accuracy of the ADC and increases power consumption. Based on this, embodiments of the present invention provide a pipelined successive approximation ADC, integrated circuit, and electronic device for halving the inter-stage gain without halving the reference voltage, thereby improving the ADC's conversion speed and power consumption.

[0024] See Figure 1 , Figure 1 The block diagram of the pipelined successive approximation analog-to-digital converter provided by one embodiment of the present invention is shown in FIG. Figure 1 As shown, the pipelined successive approximation analog-to-digital converter according to an embodiment of the present invention includes: a first-stage successive approximation analog-to-digital converter 10, an inter-stage gain amplifier 30, a second-stage successive approximation analog-to-digital converter 20, and a digital encoding unit 40. The first-stage successive approximation analog-to-digital converter 10 is connected to the second-stage successive approximation analog-to-digital converter 20 via the inter-stage gain amplifier 30, and the first-stage successive approximation analog-to-digital converter 10 and the second-stage successive approximation analog-to-digital converter 20 are respectively connected to the digital encoding unit 40.

[0025] It is understood that the first-stage successive approximation analog-to-digital converter 10 (hereinafter referred to as the first-stage SAR ADC) of the embodiment of the present invention is configured as an M-bit SAR ADC, i.e., the first-stage SAR ADC is configured to output an M-bit digital signal to the digital encoding unit 40, where M is an integer greater than 1. The second-stage successive approximation analog-to-digital converter 20 (hereinafter referred to as the second-stage SAR ADC) of the embodiment of the present invention is configured as an N-bit SAR ADC, i.e., the second-stage SAR ADC is configured to output an N-bit digital signal to the digital encoding unit 40, where N is an integer greater than 1. The digital encoding unit 40 encodes the M-bit digital signal (B11: B1M) output by the first-stage SAR ADC and the N-bit digital signal (B21: B2N) output by the second-stage SAR ADC using an inter-stage staggered accumulation method to obtain a final (M+N-1)-bit binary digital signal (D1: D(M+N-1)).

[0026] See Figure 2 , a circuit structure diagram of a first-stage SAR ADC provided by an embodiment of the present invention. The first-stage SAR ADC includes a first digital-to-analog converter, a first comparator, and a first digital control logic unit connected in sequence. The first digital-to-analog converter includes a first capacitor array, which includes a first fill capacitor C0 and M first capacitors C1 to C M .

[0027] The M first capacitors C1 to C M The capacitance value increases in power of 2 from small to large according to the number of bits. i The capacitance value can be expressed as follows: C i =2 i-1 *CU,i=any integer from 1 to M, CU is the unit capacitance.

[0028] The capacitance of the first complementary capacitor C0 is equal to the capacitance of the first capacitor C1 among the M first capacitors, that is, C0=CU.

[0029] like Figure 2 As shown, the first filling capacitor C0, each first capacitor C1~C M The first ends of the first capacitors C1 to C M The second end of each is connected to the positive reference voltage V ref , a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage), and the second end of the first compensation capacitor C0 is constantly connected to the negative reference voltage.

[0030] It will be appreciated that the analog input voltage can be connected to the input of the first digital-to-analog converter via a sample-and-hold circuit (S / H). A / D conversion of an analog signal requires a certain conversion time, during which the analog signal must remain substantially unchanged to ensure conversion accuracy. The sample-and-hold circuit implements this function.

[0031] like Figure 2 As shown in FIG, the first stage SAR ADC uses the upper plate to sample the analog input voltage. In the first stage SAR ADC, the upper plate of each capacitor is connected to the analog input voltage, and the M first capacitors C1 to C M The lower plate of the MOSFET is connected to multiple reference signal sources via a multi-way selection switch. For example, the reference signal source may include a positive reference voltage V ref and a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage). In some examples, the reference signal source also includes a common mode voltage V CM The lower plate of the first compensation capacitor C0 is permanently connected to a negative reference voltage.

[0032] exist Figure 2 In the example shown, the sampling mode of the first-stage SAR ADC is differential upper plate sampling, and the analog input voltage input to the first-stage SAR ADC is the differential voltage V ip1 and V in1 , where V ip1 is the positive analog input voltage, V in1 The first-stage SAR ADC has two first capacitor arrays with the same structure, each connected to the positive analog input voltage and the negative analog input voltage. For an M-bit differential output first-stage SAR ADC, each first capacitor array includes M+1 capacitors, for a total of 2M+2 capacitors.

[0033] It can be understood that among the M first capacitors in the first capacitor array, C1 to C M-1 Belong to weight capacitors, in the successive approximation conversion process, the output voltage of the first capacitor array can be increased / decreased by switching the switches of the corresponding weight capacitors; C M Used to generate residual voltage signal to the second-stage SAR ADC.

[0034] It is understandable that Figure 2The circuit structure of the first-stage SAR ADC shown is merely exemplary. In specific implementations, the circuit structure of the first-stage SAR ADC can be modified to accommodate different analog sampling methods. For example, when single-ended sampling is used, the first-stage SAR ADC only requires a first capacitor array.

[0035] The inter-stage gain amplifier 30 of the embodiment of the present invention is disposed between the first-stage SAR ADC and the second-stage SAR ADC. Specifically, the input end of the inter-stage gain amplifier 30 is connected to the residual voltage output from the first digital-to-analog converter.

[0036] like Figure 2 As shown, when the sampling mode of the first-stage SAR ADC is differential upper plate sampling, the inter-stage gain amplifier 30 adopts a differential amplifier. When a differential amplifier is adopted, the inter-stage gain amplifier 30 has two input terminals, which are connected to the residual voltages (positive residual voltage and negative residual voltage) output by the two first capacitor arrays. The inter-stage gain amplifier 30 is connected to V ip1 and V in1 The residual voltage is amplified to obtain the differential analog input voltage V ip2 and V in2 Correspondingly, the inter-stage gain amplifier 30 has two output terminals to convert V ip2 and V in2 Output to the second stage SAR ADC.

[0037] It is understandable that switches ( S1 , S2 ) may be provided at the two input terminals of the inter-stage gain amplifier 30 , respectively, so as to control the input of the residual voltage through the switches.

[0038] See Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of a circuit structure of a second-stage SAR ADC provided by an embodiment of the present invention. Figure 3 As shown, the second-stage SAR ADC includes a second digital-to-analog converter, a second comparator, and a second digital control logic unit connected in sequence. The second digital-to-analog converter includes a second capacitor array, which includes a gain-halving capacitor C a , a second filling capacitor C0 and N-1 second capacitors C1 to C N-1 .

[0039] The N-1 second capacitors C1 to C N-1 The capacitance value of the second capacitor Ci can be expressed as follows: C i =2 i-1 *CU,i=any integer from 1 to N-1, CU is the unit capacitance.

[0040] The capacitance value of the second filling capacitor C0 is equal to the N-1 second capacitors C1 to C N-1 The capacitance value of the first capacitor C1 is C0=CU.

[0041] The gain is halved by the capacitor C a The capacitance value of the N-1 second capacitors C1 to C N-1 and the sum of the capacitance values ​​of the second filling capacitor C0, C a The capacitance value can be expressed as follows: C a =2 N-1 *CU.

[0042] like Figure 3 As shown, the gain is halved by capacitor C a , the second filling capacitor C0, N-1 second capacitors C1 to C N-1 The first ends of the N-1 second capacitors C1 to C N-1 The second end of each is connected to the positive reference voltage V ref , negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage), the gain halved capacitor C a , and the second end of the second compensation capacitor C0 is permanently connected to the negative reference voltage.

[0043] like Figure 3 As shown, the second-stage SAR ADC uses the upper plate to sample the analog input voltage. In the second-stage SAR ADC, the upper plates of each capacitor are connected to the output end of the inter-stage gain amplifier 30 to receive the analog input voltage from the inter-stage gain amplifier 30 (obtained by amplifying the residual voltage of the first-stage SAR ADC by the inter-stage gain amplifier 30). N-1 The lower plate of the MOSFET is connected to multiple reference signal sources via a multi-way selection switch. For example, the reference signal source may include a positive reference voltage V ref and a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage). In some examples, the reference signal source also includes a common mode voltage V CM The gain is halved by the capacitor C a , the lower plate of the second compensation capacitor C0 is permanently connected to the negative reference voltage.

[0044] exist Figure 3 In the example shown, the sampling mode of the second-stage SAR ADC is differential upper plate sampling, and the two output terminals of the inter-stage gain amplifier 30 output a differential voltage V ip2 and V in2(The inter-stage gain amplifier 30 is used to adjust the V ip1 and V in1 The residual voltage is amplified). Where, V ip2 is the positive analog input voltage, V in2 is the negative analog input voltage.

[0045] In the upper plate differential sampling mode, the second capacitor array of the second-stage SAR ADC is set to two, and the structures of the two second capacitor arrays are the same. The two second capacitor arrays are correspondingly connected to the positive analog input voltage V ip2 and the negative analog input voltage V in2 For a second-stage SAR ADC with N-bit differential output, each first capacitor array includes N+1 capacitors (a gain-halving capacitor, a second-bit complement capacitor, and N-1 second capacitors), and the second-stage SAR ADC has a total of 2N+2 capacitors.

[0046] It can be understood that among the N-1 second capacitors of the second capacitor array, C1 to C N-1 They are all weighted capacitors. In the successive approximation conversion process, the output voltage of the second capacitor array can be increased / decreased by switching the switches of the corresponding weighted capacitors.

[0047] It is understandable that Figure 3 The circuit structure of the second-stage SAR ADC shown is merely exemplary. In specific implementations, the circuit structure of the second-stage SAR ADC can be modified to accommodate different analog sampling methods. For example, when single-ended sampling is used, the second-stage SAR ADC only requires a second capacitor array.

[0048] The digital encoding unit 40 of this embodiment of the present invention is connected to the output terminals of the first and second digital control logic units. The analog input voltage is amplified and quantized by a two-stage successive approximation analog-to-digital converter and an interstage gain amplifier 30 to generate an (M+N)-bit code. The digital encoding unit 40 then outputs the final (M+N-1)-bit digital code.

[0049] Figure 4 The first stage SAR ADC (M-bit SAR ADC) and the second stage SAR ADC (N-bit SAR ADC) generate a total of (M+N) bit codes. Figure 3The final (M+N-1)-bit binary digital output code (D1: D(M+N-1)) is obtained by the inter-stage staggered accumulation method. Since full-swing quantization needs to be maintained, the subtraction process of the digital code is required. The decoding circuit can achieve Figure 4 The encoding process.

[0050] In the embodiment of the present invention, a gain-halving capacitor is provided in the second digital-to-analog converter in the second-stage successive approximation analog-to-digital converter 20, and the capacitance value of the gain-halving capacitor is the sum of the capacitance values ​​of the remaining capacitors in the second digital-to-analog converter. In this way, the capacitance DAC of the second-stage successive approximation analog-to-digital converter 20 is doubled, and the inter-stage gain of the two-stage structure is halved, thereby reducing the gain of the inter-stage gain amplifier 30 (the amplification factor of the inter-stage gain amplifier 30 is reduced from 2 M-1 times reduced to 2 M-2 The positive reference voltage of the second-stage SAR ADC 20 remains the same as that of the first-stage SAR ADC 10, rather than being halved. This effectively reduces power consumption and increases conversion speed, while also being adaptable to deep-submicron CMOS processes. The analog input signal is amplified and quantized by the two-stage SAR ADC and the interstage amplifier to produce an (M+N)-bit digital signal. Ultimately, the digital encoding unit 40 outputs an (M+N-1)-bit digital signal.

[0051] It should be noted that the solution of the embodiment of the present invention is not limited to being applied to a two-stage successive approximation analog-to-digital converter, but can also be applied to a three-stage or more successive approximation analog-to-digital converter.

[0052] An embodiment of the present invention further provides an integrated circuit, which includes the pipelined successive approximation analog-to-digital converter described in any one of the above embodiments.

[0053] In addition, an embodiment of the present invention further provides an electronic device, comprising a device body and the integrated circuit described above, wherein the integrated circuit is disposed in the device body. For example, the electronic device may be a network device (such as a base station device).

[0054] The above is a detailed description of the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. These equivalent modifications or substitutions are all within the scope defined by the claims of the present invention.

Claims

1. A pipelined successive approximation analog-to-digital converter, characterized in that: include: A first-stage successive approximation analog-to-digital converter, the first-stage successive approximation analog-to-digital converter comprising a first digital-to-analog converter, a first comparator, and a first digital control logic unit connected in sequence, wherein the first digital-to-analog converter comprises a first capacitor array, the first capacitor array comprising a first fill capacitor and M first capacitors, the first ends of the first fill capacitor and each of the first capacitors being respectively connected to an analog input voltage, the second ends of each of the first capacitors being respectively connected to a positive reference voltage and a negative reference voltage via a multiplexer, and the second end of the first fill capacitor being connected to the negative reference voltage; the capacitance value of the first fill capacitor being equal to the capacitance value of the first capacitor among the M first capacitors, and the capacitance values ​​of the M first capacitors increasing in order from the smallest to the largest number of bits by a power of 2, where M is an integer greater than 1; an inter-stage gain amplifier, wherein an input terminal of the inter-stage gain amplifier is connected to the residual voltage output from the first digital-to-analog converter; a second-stage successive approximation analog-to-digital converter, the second-stage successive approximation analog-to-digital converter comprising a second digital-to-analog converter, a second comparator, and a second digital control logic unit connected in sequence, the second digital-to-analog converter comprising a second capacitor array, the second capacitor array comprising a gain-halving capacitor, a second offset capacitor, and an N-1-bit second capacitor, the first ends of the gain-halving capacitor, the second offset capacitor, and each of the second capacitors being respectively connected to the output end of the inter-stage gain amplifier, the second ends of each of the second capacitors being respectively connected to a positive reference voltage and a negative reference voltage via a multiplexer, the second ends of the gain-halving capacitor and the second offset capacitor being respectively connected to the negative reference voltage, the capacitance value of the second offset capacitor being equal to the capacitance value of the first capacitor among the N-1-bit second capacitors, and the capacitance value of the N-1-bit second capacitors increasing in order of powers of 2 from small to large according to the number of bits, the capacitance value of the gain-halving capacitor being the sum of the capacitance values ​​of the N-1-bit second capacitors and the second offset capacitor, where N is an integer greater than 1; A digital encoding unit is connected to the output ends of the first digital control logic unit and the second digital control logic unit.

2. The pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The analog input voltage is a differential voltage; the number of the first capacitor arrays is two, and the two first capacitor arrays are correspondingly connected to the positive input voltage and the negative input voltage in the differential voltage.

3. The pipelined successive approximation analog-to-digital converter according to claim 2, wherein: The inter-stage gain amplifier is a differential amplifier, and two input terminals of the differential amplifier are correspondingly connected to the residual voltages output by the two first capacitor arrays.

4. The pipelined successive approximation analog-to-digital converter according to claim 3, wherein: The differential amplifier is provided with two output terminals; the number of the second capacitor arrays is two, and each second capacitor array is connected to the two output terminals of the differential amplifier.

5. The pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The amplification factor of the inter-stage gain amplifier is 2 to the power of (M-2).

6. The pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The second end of each first capacitor is further connected to the common mode voltage through the multiplexer switch.

7. The pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The second end of each second capacitor is further connected to the common mode voltage through the multiplexer switch.

8. The pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The system further includes a sample-and-hold circuit connected to the analog input voltage and the first digital-to-analog converter.

9. An integrated circuit, characterized in that: The invention comprises the pipelined successive approximation analog-to-digital converter according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The device comprises a device body and the integrated circuit according to claim 9, wherein the integrated circuit is arranged in the device body.

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