An ultra-high precision comparator and its control method

Abstract

The present invention relates to an ultra-high-precision comparator. The high-precision comparator comprises a chopper-type low-noise programmable amplifier (PGA), a chopper switch group (swch), a pair of sampling capacitors (C1a and C1b) and their control switches, a pair of reference voltage sampling capacitors (C2a and C2b) and their control switches, a preamplifier (Preamp), a pair of capacitors (C3a and C3b), and an output comparator (Comp), all connected in sequence. By controlling the chopper switch group (swch), the offset component in the PGA output is offset, while the signal component is sampled by the sampling capacitors. By controlling the sampling capacitors and the reference voltage sampling capacitors, the preamplifier amplifies the difference between the amplified input signal and the reference voltage and transmits it to the output comparator to obtain the final comparison result. The ultra-high-precision comparator can be applied to the on-scale detection of electronic scales, eliminating the need for ADC conversion, significantly improving the on-scale detection speed, and significantly reducing system power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an ultra-high precision comparator. Background Art

[0002] Comparators are extremely common analog modules, often used to indirectly determine whether an event has occurred by determining whether a detected voltage has reached a certain threshold. Limited by factors such as comparator noise and offset voltage, the detection accuracy of common comparators is typically in the millivolt or hundred-microvolt range, which cannot meet the high-precision requirements of microvolt-level applications.

[0003] For example, in an electronic scale's on-scale detection application, the scale needs to periodically wake up from sleep mode to detect whether an object has been placed inside. Traditional solutions require high-precision Sigma-Delta ADCs to convert the signal before making a judgment, which slows down the response time. Summary of the Invention

[0004] The present invention provides a comparator solution with detection accuracy reaching the uV level, which can meet the application requirements of ultra-high precision. Electronic scales using the comparator of the present invention do not require ADC conversion during on-scale detection, which can significantly improve on-scale detection speed and significantly reduce system power consumption.

[0005] An ultra-high-precision comparator includes a chopper-type low-noise programmable amplifier (PGA), a chopper switch group (swch), a pair of sampling capacitors (C1a and C1b), a preamplifier (Preamp), a pair of capacitors (C3a and C3b), and an output comparator (Comp), all connected in sequence. By controlling the chopper switch group (swch), the output signals of the amplifier (PGA) when the chopper clock is high and low are added together to offset the PGA's offset voltage.

[0006] The chopper switch group swch includes two input terminals and two output terminals. The two input terminals are respectively connected to the two output terminals Vop and Von of the amplifier PGA, and the two output terminals are respectively connected to the negative electrodes of capacitors C1a and C1b; the positive electrodes of capacitors C1a and C1b are respectively connected to the two input terminals of the amplifier Preamp; the two output terminals of the amplifier Preamp are respectively connected to the negative electrodes of capacitors C3a and C3b, and the positive electrodes of capacitors C3a and C3b are respectively connected to the two output terminals of the comparator Comp.

[0007] The device further includes a pair of reference voltage sampling capacitors C2a and C2b; the positive electrodes of the reference voltage sampling capacitors C2a and C2b are connected to the positive electrodes of the capacitors C1a and C1b, respectively; the negative electrodes of the reference voltage sampling capacitors C2a and C2b are connected to the reference voltages VTHn and VTHp, respectively, via switches SW1a and SW1b; and the negative electrodes of the reference voltage sampling capacitors C2a and C2b are also connected to the reference voltage VTHCM, respectively, via switches SW2a and SW2b, respectively.

[0008] The two input terminals of the preamplifier Preamp are further connected to the common mode voltage VCM via switches SW3a and SW3b respectively; the two input terminals of the output comparator Comp are further connected to the common mode voltage VCM via switches SW4a and SW4b respectively.

[0009] The reference voltage can also be generated using a resistor DAC.

[0010] The device further includes a pair of reference voltage sampling capacitors C2a and C2b; the positive electrodes of the reference voltage sampling capacitors C2a and C2b are connected to the positive electrodes of the capacitors C1a and C1b, respectively; the negative electrodes of the reference voltage sampling capacitors C2a and C2b are connected to the two output terminals VTHn and VTHp of the resistive DAC, respectively, via switches SW1a and SW1b; and the negative electrodes of the reference voltage sampling capacitors C2a and C2b are further connected to the reference voltage VTHCM, respectively, via switches SW2a and SW2b, respectively.

[0011] An ultra-high precision comparator is set in the electronic scale chip to realize scale detection.

[0012] The control methods of ultra-high precision comparators include:

[0013] When the chopping clock φ ch When the PGA output is high, Vopn(n) is output. ch When it is low, the output of the PGA is Vopn(n) and Added together to cancel the PGA offset voltage.

[0014] When the chopping clock φch is high, the output of the PGA can be expressed as

[0015] Vopn(n)=(Vipn(n)+Vos pga )·Gain (1)

[0016] When the chopping clock φ ch When it is low, the output of the PGA can be expressed as

[0017]

[0018] Where Gain is the gain of the PGA; a switched capacitor circuit is used to add the two.

[0019] When the clock φ1 is high: swch connects the output terminal Vop of the PGA to C1a, connects the output terminal Von of the PGA to C1b, and the sampling capacitor collects Vopn(n) in formula (1); sw1a, sw1b are closed, and the reference voltage sampling capacitor collects the reference voltage VTHpn; when φ1 is low: swch connects Vop to C1b, connects Von to C1a, and the sampling capacitor collects Vopn(n) in formula (2). Collected; sw1a, sw1b are disconnected; φ1 and φ ch The rising edge is later than the falling edge of φ3.

[0020] φ1 and φ ch Same, that is, the same clock.

[0021] When the sampling clock φ2 is high, sw2a, sw2b, sw3a, sw3b are closed, the negative poles of C2a and C2b are connected to VTHCM, and the positive poles of C1a, C1b, C2a, C2b, that is, the input terminal of the preamplifier, are connected to the common mode voltage VCM; when the sampling clock φ2 is low, sw2a, sw2b, sw3a, sw3b are disconnected.

[0022] When the zeroing clock φ3 is high, sw4a and sw4b are closed, and the output offset voltage of the preamplifier is stored in capacitors C3a and C3b; when the zeroing clock φ3 is low, sw4a and sw4b are disconnected; the falling edge of φ3 is later than the falling edge of φ2.

[0023] When φ1 and φ ch After it is high, the positive electrodes of the sampling capacitor and the reference voltage sampling capacitor are in a floating state, and the charges on the two sets of capacitors will be self-balanced. The positive electrode differential voltage after stabilization is Vpre=Vprep-Vpren, then

[0024]

[0025] This voltage will be amplified by the pre-amplifier and compared by the output comparator; the equivalent threshold voltage Vtheq of the comparator is

[0026]

[0027] A resistive DAC is used to generate the reference voltage. By configuring the DAC output, the comparator threshold voltage can be flexibly selected. When the sampling capacitors C1a and C1b are selected to be equal to the reference voltage sampling capacitors C2a and C2b, equation (4) can be simplified to:

[0028]

[0029] The present invention has the following technical effects: The invented ultra-high-precision comparator utilizes a chopper-type low-offset, low-noise amplifier in combination with an invented switched-capacitor circuit to achieve a high-speed, uV-level ultra-high-precision comparator. With the help of a DAC, the solution supports flexible configuration of the threshold voltage.

[0030] By using this ultra-high-precision comparator, the speed of periodic wake-up detection of electronic scales can be significantly improved, thereby significantly reducing the overall power consumption of traditional electronic scale solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The present invention is a schematic diagram of an ultra-high precision comparator comprising a chopper-type low-noise programmable amplifier (PGA), a chopper, a pair of sampling capacitors, a pair of reference voltage sampling capacitors, a preamplifier, and an output comparator.

[0032] Figure 2 yes Figure 1 Switch control timing diagram.

[0033] Figure 3 It is the preferred ultra-high precision comparator. DETAILED DESCRIPTION

[0034] The present invention uses a chopper-type programmable amplifier to amplify signals, thereby avoiding the large errors caused by the amplifier's offset voltage and low-frequency flicker noise. Chopper-type programmable amplifiers are commonly used low-offset, low-noise amplifiers. They modulate the amplifier's offset voltage and low-frequency noise to the chopping frequency. For ease of explanation, the following derivation only considers the offset voltage, Vospga, and ignores low-frequency noise. The PGA's differential input signal is denoted by Vipn(n), the differential output signal by Vopn(n), and the PGA's gain is denoted by Gain.

[0035] When the chopping clock φch is high, the output of the PGA can be expressed as

[0036] Vopn(n)=(Vipn(n)+Vos pga )·Gain (1)

[0037] When the chopping clock φch is low, the output of the PGA can be expressed as

[0038]

[0039] It can be seen that if equation (1) and equation (2) are added together, the offset voltage of the PGA can be offset. The present invention uses a switched capacitor circuit to achieve the addition of the two.

[0040] When the clock φ1 is high: swch connects Vop to C1a, connects Von to C1b, and the sampling capacitor collects Vopn(n) in formula (1); sw1a, sw1b are closed, and the reference voltage sampling capacitor collects the reference voltage VTHpn. When φ1 is low: swch connects Vop to C1b, connects Von to C1a, and the sampling capacitor collects Vopn(n) in formula (2). The rising edge of φ1 and φch must be later than the falling edge of φ3. φ1 and φch can be the same, that is, the same clock.

[0041] When the sampling clock φ2 is high, sw2a, sw2b, sw3a, sw3b are closed, the negative poles of C2a and C2b are connected to VTHCM, and the positive poles of C1a, C1b, C2a, C2b, that is, the input terminal of the preamplifier, are connected to the common mode voltage VCM; when the sampling clock φ2 is low, sw2a, sw2b, sw3a, sw3b are disconnected.

[0042] When the zero adjustment clock φ3 is high, sw4a and sw4b are closed, and the output offset voltage of the preamplifier is stored in C4a and C4b. When the zero adjustment clock φ3 is low, sw4a and sw4b are opened. The falling edge of φ3 must be later than the falling edge of φ2.

[0043] According to the above timing, when φ1 and φch are high, the positive electrodes of the sampling capacitor and the reference voltage sampling capacitor are in a floating state, and the charges on the two sets of capacitors will be self-balanced. The positive differential voltage after stabilization is Vpre = Vprep-Vpren, then

[0044]

[0045] This voltage will be amplified by the pre-amplifier and compared by the output comparator.

[0046] It can be seen that the equivalent threshold voltage Vtheq of the invented comparator is

[0047]

[0048] Preferably, a resistor-type DAC (R-string DAC) is used to generate the reference voltage. This allows for flexible selection of the comparator threshold voltage by configuring the DAC output. When the sampling capacitors C1a and C1b are selected to be equal to the reference voltage sampling capacitors C2a and C2b, equation (4) can be simplified to:

[0049]

[0050] It can be seen that if the gain of the PGA is 500 times and Vthpn is 1mV, the equivalent input threshold voltage is 1uV.

[0051] Preferably, the DAC's reference voltage can be set to the external sensor's supply voltage. For example, in electronic scales, a bridge-type pressure sensor is often used to detect an object's weight, converting weight into a change in resistance. By setting the DAC's reference voltage to the external sensor's supply voltage, even if the supply voltage fluctuates, the fluctuations in the sensor's output voltage and the comparator's threshold voltage can be offset, ensuring extremely high detection accuracy.

Claims

1. An ultra-high precision comparator, characterized in that: The system comprises a chopper-type low-noise programmable amplifier PGA, a chopper switch group swch, a pair of sampling capacitors C1a and C1b, a pair of reference voltage sampling capacitors C2a and C2b, a preamplifier Preamp, a pair of capacitors C3a and C3b, and an output comparator Comp, which are connected in sequence. By controlling the chopper switch group swch, the output signals of the amplifier PGA when the chopper clock is high and low are added to offset the offset voltage of the PGA. The device further includes a pair of reference voltage sampling capacitors C2a and C2b; the positive electrodes of the reference voltage sampling capacitors C2a and C2b are connected to the positive electrodes of capacitors C1a and C1b, respectively; the negative electrodes of the reference voltage sampling capacitors C2a and C2b are connected to reference voltages VTHn and VTHp, respectively, via switches SW1a and SW1b; the negative electrodes of the reference voltage sampling capacitors C2a and C2b are further connected to a reference voltage VTHCM, respectively, via switches SW2a and SW2b; the two input terminals of the preamplifier Preamp are further connected to a common-mode voltage VCM, respectively, via switches SW3a and SW3b; and the two input terminals of the output comparator Comp are further connected to the common-mode voltage VCM, respectively, via switches SW4a and SW4b.

2. The ultra-high precision comparator according to claim 1, wherein: The chopper switch group swch includes two input terminals and two output terminals. The two input terminals are respectively connected to the two output terminals Vop and Von of the amplifier PGA, and the two output terminals are respectively connected to the negative electrodes of capacitors C1a and C1b; the positive electrodes of capacitors C1a and C1b are respectively connected to the two input terminals of the amplifier Preamp; the two output terminals of the amplifier Preamp are respectively connected to the negative electrodes of capacitors C3a and C3b, and the positive electrodes of capacitors C3a and C3b are respectively connected to the two input terminals of the comparator Comp.

3. The ultra-high precision comparator according to claim 1, wherein: A resistive DAC is used to generate a reference voltage. A pair of reference voltage sampling capacitors C2a and C2b are also included. The positive electrodes of the reference voltage sampling capacitors C2a and C2b are connected to the positive electrodes of capacitors C1a and C1b, respectively. The negative electrodes of the reference voltage sampling capacitors C2a and C2b are connected to two output terminals VTHn and VTHp of the resistive DAC via switches SW1a and SW1b, respectively. The negative electrodes of the reference voltage sampling capacitors C2a and C2b are also connected to a reference voltage VTHCM via switches SW2a and SW2b, respectively.

4. An electronic scale, characterized in that: The electronic scale uses the ultra-high precision comparator according to any one of claims 1 to 3 to implement weighing detection.

5. A control method for controlling the ultra-high precision comparator according to any one of claims 1 to 3, characterized in that: When the chopping clock φ ch When the PGA output is high, Vopn(n) is output. ch When it is low, the output of the PGA is Vopn(n) and Added together to cancel the PGA offset voltage.

6. The control method according to claim 5, characterized in that: When the chopping clock φch is high, the output of the PGA can be expressed as Weapon(s)=(Weapon(s)+Vos pga )·Gain (1) When the chopping clock φ ch When it is low, the output of the PGA can be expressed as Where Gain is the gain of the PGA; a switched capacitor circuit is used to add the two.

7. The control method according to claim 5, characterized in that: When the clock φ1 is high: swch connects the output terminal Vop of the PGA to C1a, and connects the output terminal Von of the PGA to C1b, and the sampling capacitor collects Vopn(n) in formula (1); When sw1 a and sw1 b are closed, the reference voltage sampling capacitor collects the reference voltage VTHpn. When φ1 is low, swch connects Vop to C1 b and Von to C1 a. The sampling capacitor collects the reference voltage VTHpn in formula (2). Collect it; sw1a, sw1b are disconnected; φ1 and φ ch The rising edge is later than the falling edge of φ3; ch Same, that is, the same clock; When the sampling clock φ2 is high, sw2a, sw2b, sw3a, sw3b are closed, the negative poles of C2a and C2b are connected to VTHCM, and the positive poles of C1a, C1b, C2a, C2b, that is, the input terminal of the preamplifier, are connected to the common mode voltage VCM; when the sampling clock φ2 is low, sw2a, sw2b, sw3a, sw3b are disconnected.

8. The control method according to claim 5, characterized in that: When the zero adjustment clock φ3 is high, sw4a and sw4b are closed, and the output offset voltage of the preamplifier is stored in capacitors C3a and C3b; When the zero adjustment clock φ3 is low, sw4a and sw4b are disconnected; the falling edge of φ3 is later than the falling edge of φ2; When φ1 and φ ch After it is high, the positive electrodes of the sampling capacitor and the reference voltage sampling capacitor are in a floating state, and the charges on the two sets of capacitors will be self-balanced. The positive electrode differential voltage after stabilization is Vpre=Vprep-Vpren, then This voltage will be amplified by the pre-amplifier and compared by the output comparator; the equivalent threshold voltage Vtheq of the comparator is 9. The control method according to claim 5, characterized in that: A resistive DAC is used to generate the reference voltage. By configuring the DAC output, the comparator threshold voltage can be flexibly selected. When the sampling capacitors C1a and C1b are selected to be equal to the reference voltage sampling capacitors C2a and C2b, equation (4) can be simplified to:

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