Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem that short circuits are prone to occur when conductive contacts contact each other. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, the substrate is provided with a plurality of active regions arranged at intervals, and the substrate is covered with an insulating layer and a barrier layer which are stacked in sequence; a plurality of first grooves arranged at intervals and extending along a first direction are formed in the barrier layer, and the first grooves penetrate through the barrier layer; a filling layer is formed in the first grooves, and a first mask layer is formed on the barrier layer and the filling layer; a plurality of second grooves arranged at intervals and extending along a second direction are formed in the first mask layer, and the second grooves expose the filling layer; and the filling layer exposed in the second grooves and the insulating layer corresponding to the filling layer are removed to form contact holes. The contact holes are formed by using the first grooves and the second grooves, the communication between the contact holes is reduced, and thus the possibility that short circuits occur when the conductive contacts contact each other is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] The semiconductor structure can include a memory cell, which usually includes a transistor and a capacitor electrically connected with the transistor. The capacitor stores data information, and the transistor controls reading and writing of the data information in the capacitor. The gate of the transistor is electrically connected with a word line (WL), and the opening and closing of the transistor are controlled by a voltage on the word line; one of the source and the drain of the transistor is electrically connected with a bit line (BL), and the other of the source and the drain is electrically connected with the capacitor, and the data information is stored or output through the bit line.

[0003] With the miniaturization of the semiconductor structure, single-point bridging is prone to occur in the manufacturing process of the semiconductor structure, which causes the short circuit of the conductive contacts, and affects the performance of the semiconductor structure. SUMMARY

[0004] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are used to reduce or avoid the mutual contact between the conductive contacts, and improve the performance of the semiconductor structure.

[0005] A first aspect of the embodiments of the present application provides a manufacturing method of a semiconductor structure, which includes: providing a substrate, the substrate is provided with a plurality of active regions arranged at intervals, and the substrate is covered with an insulating layer and a barrier layer which are stacked in sequence;

[0006] A plurality of first grooves arranged at intervals are formed in the barrier layer, the first grooves extend along a first direction and penetrate through the barrier layer;

[0007] A filling layer is formed in the first grooves, and a first mask layer is formed on the barrier layer and the filling layer;

[0008] A plurality of second grooves arranged at intervals are formed in the first mask layer, the second grooves extend along a second direction, and the second grooves expose the filling layer;

[0009] The filling layer exposed in the second grooves and the insulating layer corresponding to the filling layer are removed to form a contact hole, and the contact hole exposes the active region.

[0010] The manufacturing method of the semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0011] The method for manufacturing the semiconductor structure in the embodiments of the present application includes the following steps: forming a plurality of first grooves which are arranged at intervals and extend along a first direction in a barrier layer, forming a filling layer in the first grooves, forming a first mask layer on the filling layer and the barrier layer, forming a plurality of second grooves which are arranged at intervals and extend along a second direction in the first mask layer, the second grooves exposing the filling layer, and removing the exposed filling layer to form a contact hole. The contact hole is defined by the area where the orthographic projection of the second grooves on the barrier layer coincides with the first grooves, so that the adjacent contact holes can be prevented from being connected, and the first conductive layer formed in the contact hole in the subsequent process can be prevented from being short-circuited, thereby improving the performance of the semiconductor structure.

[0012] The second aspect of the embodiments of the present application provides a semiconductor structure formed by the method for manufacturing the semiconductor structure as described above, so that the semiconductor structure has at least the advantages of the method for manufacturing the semiconductor structure, and the specific effects are described above and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 The flow chart of the method for manufacturing the semiconductor structure in the embodiments of the present application;

[0015] Figure 2 The structure schematic diagram after forming the barrier layer in the embodiments of the present application;

[0016] Figure 3 The structure schematic diagram after forming the first grooves in the embodiments of the present application;

[0017] Figure 4 The structure schematic diagram after forming the filling layer in the embodiments of the present application;

[0018] Figure 5 The top view of Figure 4

[0019] Figure 6 The structure schematic diagram after forming the first mask layer in the embodiments of the present application;

[0020] Figure 7 The structure schematic diagram after forming the second grooves in the embodiments of the present application;

[0021] Figure 8 ​A structure schematic diagram after forming a contact hole in the embodiment of the present application;

[0022] Figure 9 A structure schematic diagram after forming a first photoresist layer in the embodiment of the present application;

[0023] Figure 10 A structure schematic diagram after forming a third groove in the embodiment of the present application;

[0024] Figure 11 A structure schematic diagram after forming a first dielectric layer in the embodiment of the present application;

[0025] Figure 12 A structure schematic diagram after removing a second anti-reflection layer in the embodiment of the present application;

[0026] Figure 13 A structure schematic diagram after forming a second etching groove in the third anti-reflection layer in the embodiment of the present application;

[0027] Figure 14 A structure schematic diagram after forming a second etching groove in the third base layer in the embodiment of the present application;

[0028] Figure 15 A structure schematic diagram after reserving a part of the third base layer in the embodiment of the present application;

[0029] Figure 16 A top view of Figure 15 ;

[0030] Figure 17 A structure schematic diagram after forming a second photoresist layer in the embodiment of the present application;

[0031] Figure 18 A top view of Figure 16 ;

[0032] Figure 19 A structure schematic diagram after forming a fourth groove in the embodiment of the present application;

[0033] Figure 20 A structure schematic diagram after forming a second dielectric layer in the embodiment of the present application;

[0034] Figure 21 A structure schematic diagram after removing a fourth anti-reflection layer in the embodiment of the present application;

[0035] Figure 22 A structure schematic diagram after forming a third etching groove in the embodiment of the present application;

[0036] Figure 23 Another structure schematic diagram after forming a second groove in the embodiment of the present application;

[0037] Figure 24 Another structure schematic diagram after forming the second groove in the embodiment of the present application;

[0038] Figure 25 Another structure schematic diagram after forming the contact hole in the barrier layer in the embodiment of the present application;

[0039] Figure 26 Another structure schematic diagram after forming the contact hole in the insulating layer in the embodiment of the present application;

[0040] Figure 27 Another structure schematic diagram after removing the filling layer in the embodiment of the present application;

[0041] Figure 28 Another structure schematic diagram after forming the first conductive layer in the embodiment of the present application; Figure 27 Another structure schematic diagram after forming the first support layer in the embodiment of the present application;

[0042] Figure 29 Another structure schematic diagram after forming the first conductive layer in the embodiment of the present application;

[0043] Figure 30 Another structure schematic diagram after forming the first support layer in the embodiment of the present application;

[0044] Figure 31 Another structure schematic diagram after forming the third photoresist layer in the embodiment of the present application;

[0045] Figure 32 Another structure schematic diagram after forming the gap wall in the embodiment of the present application;

[0046] Figure 33 Another structure schematic diagram after etching the second conductive layer in the embodiment of the present application;

[0047] Figure 34 Another structure schematic diagram after forming the second support layer in the embodiment of the present application.

[0048] Explanation of reference signs:

[0049] 100 - substrate; 200 - insulating layer; 300 - barrier layer;

[0050] 310 - first groove; 400 - filling layer; 410 - contact hole;

[0051] 510 - first mask layer; 511 - second groove; 512 - first base layer;

[0052] 513 - first anti-reflection layer; 520 - third mask layer; 521 - third base layer;

[0053] 522 - third anti-reflection layer; 523 - second etching groove; 530 - second mask layer;

[0054] 531 - second base layer; 532 - second anti-reflective layer; 533 - third trench;

[0055] 540 - first photoresist layer; 541 - first through trench; 550 - first intermediate layer;

[0056] 560 - first dielectric layer; 610 - fourth mask layer; 611 - fourth base layer;

[0057] 612 - fourth anti-reflective layer; 613 - fourth trench; 620 - second photoresist layer;

[0058] 621 - second through trench; 630 - second intermediate layer; 640 - second dielectric layer;

[0059] 650 - third etching trench; 710 - first conductive layer; 720 - second conductive layer;

[0060] 730 - first support layer; 740 - fifth trench; 750 - oxide layer;

[0061] 760 - second support layer; 810 - amorphous carbon layer; 820 - first silicon oxynitride layer;

[0062] 830 - hard mask layer; 840 - second silicon oxynitride layer; 850 - third photoresist layer;

[0063] 851 - third through trench; 860 - spacer. DETAILED DESCRIPTION

[0064] In order to reduce the short circuit between the conductive contacts, the application provides a method for manufacturing a semiconductor structure. A plurality of first trenches are formed in a barrier layer, and the first trenches are arranged at intervals and extend along a first direction. A filling layer is formed in the first trenches. A first mask layer is formed on the filling layer and the barrier layer, and a plurality of second trenches are formed in the first mask layer, and the second trenches are arranged at intervals and extend along a second direction. When the filling layer is removed along the second trenches to form filling holes, the contact holes are separated by the barrier layer opposite to the second trenches, so that the adjacent contact holes are prevented from being connected, and the first conductive layer formed in the contact holes is prevented from being short-circuited, and the performance of the semiconductor structure is improved.

[0065] In order to make the above-mentioned objects, features and advantages of the application more apparent, clear and complete, the technical solutions in the embodiments of the application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0066] Referring to Figure 1 , Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present application. The method comprises the following steps:

[0067] In step S101, a substrate is provided. The substrate has a plurality of active regions arranged at intervals therein. The substrate has an insulating layer and a barrier layer stacked in sequence thereon.

[0068] Referring to Figure 2 , the substrate 100 can be a substrate containing a semiconductor material, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a germanium arsenic substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc.

[0069] The substrate 100 has a plurality of active regions (not shown in the figure) arranged at intervals therein. The active regions are electrically connected to at least one capacitor (not shown in the figure). Each active region can be defined by a shallow trench isolation (STI) (not shown in the figure). Specifically, a portion of the substrate 100 is removed to a preset depth by an etching process to form a groove surrounding the plurality of active regions, and an insulating material is deposited in the groove to isolate the active regions from each other. The insulating material can be silicon oxide or silicon nitride, etc.

[0070] The substrate 100 further has a plurality of word lines (not shown in the figure) arranged at intervals therein. The plurality of word lines extend along a third direction, and each word line is insulatively arranged between the active regions. The word lines can be buried word lines (BWLs). The active regions are arranged obliquely with respect to the extension direction (the third direction) of the word lines, and preferably, the active regions are also arranged obliquely with respect to the extension direction (the first direction) of the bit lines. In this way, the arrangement density of the capacitors can be increased, thereby increasing the storage capacity of the semiconductor structure.

[0071] Continuing to refer to Figure 2 , the substrate 100 further has an insulating layer 200 and a barrier layer 300 stacked in sequence thereon. The insulating layer 200 can be made of the same insulating material as that in the STI. In this way, the STI and the insulating layer 200 can be simultaneously manufactured in the same deposition process, i.e., the insulating material is deposited in the groove and on the substrate 100, thereby simplifying the manufacturing process of the semiconductor structure. The barrier layer 300 can be made of silicon nitride or silicon oxynitride, etc., to serve as an etching stop layer. For example, the insulating layer 200 is made of silicon oxide, and the barrier layer 300 is made of silicon nitride.

[0072] In step S102, a plurality of first grooves are formed in the barrier layer, the first grooves being spaced apart and extending along a first direction.

[0073] Referring to Figure 3 , a plurality of first grooves 310 are formed in the barrier layer 300, the first grooves 310 being spaced apart and extending along a first direction. As shown in Figure 3 , the first grooves 310 extend along a direction perpendicular to the plane of the paper. The first grooves 310 extend through the barrier layer 300, so that the first grooves 310 expose the insulating layer 200.

[0074] In step S103, a filling layer is formed in the first grooves, and a first mask layer is formed on the barrier layer and the filling layer.

[0075] Referring to Figure 4 and Figure 5 , a filling layer 400 is formed in the first grooves 310 by a deposition process or the like, the filling layer 400 filling the first grooves 310. The filling layer 400 is made of a material different from that of the barrier layer 300, and has a relatively large selectivity ratio with respect to the barrier layer 300, so as to be removed separately later. For example, the filling layer 400 can be a spin on hardmask (SOH).

[0076] For example, as shown in Figure 4 and Figure 5 , the top surface of the filling layer 400 can be flush with the top surface of the barrier layer 300, where the top surface refers to the surface facing away from the substrate 100, i.e., the upper surface shown in Figure 4 . In the top view shown in Figure 5 , the area filled with the pattern is the barrier layer 300, and the white area is the filling layer 400. The pattern is only for distinguishing the barrier layer 300 and the filling layer 400, and has no other meaning. As shown in Figure 5 , the filling layer 400 can be a plurality of spaced-apart strip structures, each strip structure extending along the first direction (X direction) shown in Figure 5 .

[0077] After the filling layer 400 is formed, a first mask layer 510 is formed on the barrier layer 300 and the filling layer 400, the first mask layer 510 at least contacting the filling layer 400. It can be understood that when there is a remaining film layer on the barrier layer 300, the first mask layer 510 covers the remaining film layer on the barrier layer 300 and the filling layer 400. When there is no film layer on the barrier layer 300, as shown in Figure 6 , the first mask layer 510 covers the barrier layer 300 and the filling layer 400.

[0078] In one possible example, referring to Figure 10The first mask layer 510 can be a stacked structure, including a first base layer 512, which is in contact with the fill layer 400. The material of the first base layer 512 and the fill layer 400 can be the same. For example, the first base layer 512 and the fill layer 400 can be formed in a single patterning process to simplify the semiconductor structure fabrication process. For instance, the first base layer 512 and the fill layer 400 can be formed in a single deposition process.

[0079] Step S104: Multiple spaced second trenches are formed in the first mask layer. The second trenches extend along the second direction and expose the filling layer.

[0080] refer to Figure 7 Multiple second trenches 511 are formed within the first mask layer 510 through an etching process. The multiple second trenches 511 are spaced apart and extend along a second direction, which is different from the extension direction of word lines (third direction) and the extension direction of bit lines (first direction). The filler layer 400 is exposed within the second trenches 511 to facilitate subsequent removal of the filler layer 400.

[0081] It is understandable that the orthographic projection of the second trench 511 onto the substrate 100 and the orthographic projection of the first trench 310 onto the substrate 100 have overlapping regions. These overlapping regions are arranged in an array, and their shape can be a parallelogram, such as a rhombus.

[0082] Step S105: Remove the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer to form a contact hole, which exposes the active area.

[0083] refer to Figure 8 The second trench 511 exposes the filler layer 400 and the barrier layer 300. By adjusting the materials of the filler layer 400 and the barrier layer 300, a larger selectivity ratio is achieved between them, reducing damage to the barrier layer 300 during the removal of the filler layer 400. For example... Figure 8 As shown, the filler layer 400 and the insulating layer 200 are etched along the second trench 511 to remove the filler layer 400 exposed in the second trench 511, as well as the insulating layer 200 corresponding to the removed filler layer 400, forming a contact hole 410. The contact hole 410 penetrates the filler layer 400 and the insulating layer 200 to expose the active region.

[0084] In the semiconductor structure fabrication method of this application embodiment, multiple spaced first trenches 310 extending along a first direction are formed in the barrier layer 300, and a filling layer 400 is formed within the first trenches 310; a first mask layer 510 is formed on the filling layer 400 and the barrier layer 300, and multiple spaced second trenches 511 extending along a second direction are formed in the first mask layer 510, exposing the filling layer 400; then the exposed filling layer 400 is removed to form a contact hole 410. The contact hole 410 is defined by the region where the orthographic projection of the second trench 511 on the barrier layer 300 coincides with the first trench 310. By using the barrier layer 300 opposite to the second trench 511 to separate the contact holes 410, the connection between adjacent contact holes 410 can be reduced or avoided, thereby reducing or avoiding short circuits caused by the subsequent contact of the first conductive layer formed within the contact hole 410, and improving the performance of the semiconductor structure.

[0085] refer to Figures 9 to 16 In one possible embodiment of this application, the step of forming a plurality of spaced first trenches within the barrier layer, the first trenches extending along a first direction and penetrating the barrier layer (step S101) includes:

[0086] Step S1011: Form a third mask layer, a second mask layer and a first photoresist layer stacked sequentially on the barrier layer.

[0087] like Figures 9 to 16 As shown, a third mask layer 520 is deposited on the barrier layer 300, a second mask layer 530 is deposited on the third mask layer 520, and a first photoresist layer 540 is coated on the second mask layer 530. The barrier layer 300, the third mask layer 520, the second mask layer 530, and the first photoresist layer 540 are sequentially stacked along a direction away from the substrate 100. The first photoresist layer 540 is a patterned first photoresist layer 540, which has a first pattern formed through processes such as exposure and development. The first pattern includes multiple first through-holes 541, which expose the top surface of the second mask layer 530.

[0088] For example, the second mask layer 530 includes a second base layer 531 located on the third mask layer 520, and a second anti-reflective layer 532 located on the second base layer 531. The second anti-reflective layer 532 can absorb light from the first photoresist layer 540 during the exposure process to prevent light reflection from affecting the accuracy of the first pattern. The material of the second anti-reflective layer 532 can be an organic material or a combination thereof with etching properties similar to those of the first photoresist layer 540. The second base layer 531 can have a higher selectivity relative to the second anti-reflective layer 532; for example, the material of the second base layer 531 can be a spin-coated hard mask, silicon oxynitride, silicon oxide, silicon nitride, etc.

[0089] Step S1012, etching the second mask layer 530 as a mask with the first photoresist layer 540, removing the second mask layer 530 not covered by the first photoresist layer 540, and retaining the second mask layer 530 covered by the first photoresist layer 540.

[0090] The second mask layer 530 is etched as a mask with the first photoresist layer 540, removing the second mask layer 530 not covered by the first photoresist layer 540, and retaining the second mask layer 530 covered by the first photoresist layer 540. Referring to Figure 10 After etching, the third trench 533 is formed in the second mask layer 530, and the third trench 533 extends along the first direction. The third trench 533 penetrates the second base layer 531 and the second anti-reflection layer 532, and the third trench 533 exposes the top surface of the third mask layer 520. In this process, the first photoresist layer 540 is removed partially or even completely. For example, as shown in Figure 9 and Figure 10 , the first photoresist layer 540 is completely removed, and the top surface of the second anti-reflection layer 532 is exposed, so that the first photoresist layer 540 does not need to be removed separately, and the manufacturing process of the semiconductor structure is simplified.

[0091] Step S1013, forming a first intermediate layer on the sidewall and the bottom of the third trench, and the first intermediate layer in the third trench is enclosed to form a first filling groove.

[0092] Referring to Figure 10 and Figure 11 , the first intermediate layer 550 is deposited on the sidewall and the bottom of the third trench 533, and the first intermediate layer 550 in the third trench 533 is enclosed to form a first filling groove. When the second mask layer 530 includes the second base layer 531 and the second anti-reflection layer 532, the first intermediate layer 550 covers the side surface of the second base layer 531, the side surface of the second anti-reflection layer 532, and the third mask layer 520.

[0093] For example, the selection ratio of the first intermediate layer 550 to the second base layer 531 is greater than or equal to 5, so that the damage to the second base layer 531 is reduced when the first intermediate layer 550 is etched, so as to retain the second base layer 531, and the retained second base layer 531 is used as a mask for etching the third mask layer 520 subsequently.

[0094] In some possible examples of the present application, as shown in Figure 10 and Figure 11 , the step of forming the first intermediate layer 550 on the sidewall and the bottom of the third trench 533, and the first intermediate layer 550 in the third trench 533 is enclosed to form a first filling groove includes:

[0095] The first intermediate layer 550 is deposited on the sidewall and the bottom of the third trench 533, and on the second anti-reflection layer 532. For example, Figure 11As shown, the first intermediate layer 550 is formed on the second mask layer 530 and the third mask layer 520.

[0096] Step S1014, forming a first dielectric layer in the first filling groove.

[0097] The first dielectric layer 560 is formed in the first filling groove, and the first dielectric layer 560 fills the first filling groove. As shown, Figure 11 The material of the first dielectric layer 560 can be the same as that of the second base layer 531, for example, both are spin-on hard masks. In some possible examples, the first dielectric layer 560 can also cover the first intermediate layer 550, and part of the first dielectric layer 560 can be removed by a planarization process, for example, chemical mechanical polishing (CMP), to expose the first intermediate layer 550.

[0098] Step S1015, removing part of the first intermediate layer to form a plurality of first etching grooves arranged at intervals.

[0099] The first intermediate layer 550 on the sidewall of the third groove 533 is etched to form a plurality of first etching grooves arranged at intervals. Specifically, the step of removing part of the first intermediate layer 550 to form a plurality of first etching grooves arranged at intervals includes:

[0100] Referring to Figure 11 and Figure 12 Part of the first intermediate layer 550, part of the first dielectric layer 560, and the second anti-reflective layer 532 are removed to expose the first intermediate layer 550 on the sidewall of the third groove 533. That is, the second anti-reflective layer 532 and the film layer on the second anti-reflective layer 532 are removed to expose the second base layer 531 and the first intermediate layer 550. For example, the second base layer 531 and the first intermediate layer 550 on the sidewall of the third groove 533 are exposed by a planarization process.

[0101] After part of the first intermediate layer 550, part of the first dielectric layer 560, and the second anti-reflective layer 532 are removed to expose the first intermediate layer 550 on the sidewall of the third groove 533, the exposed part of the first intermediate layer 550 is removed to form a first etching groove. For example, the exposed first intermediate layer 550 is etched to form a first etching groove, and the first etching groove exposes the third mask layer 520.

[0102] Step S1016, etching the third mask layer along the first etching groove to form a second etching groove in the third mask layer.

[0103] In some possible embodiments, as shown, Figure 12As shown, the third mask layer 520 includes a third base layer 521 disposed on the barrier layer 300, and a third anti-reflection layer 522 disposed on the third base layer 521. The material of the third base layer 521 can be the same as the material of the second base layer 531, and the material of the third anti-reflection layer 522 can be the same as the material of the second anti-reflection layer 532, so as to reduce the types of materials required in the manufacturing process of the semiconductor structure. In addition, the third mask layer 520 is etched by using the first etching groove, without using photoresist, thereby reducing the number of photoetchings.

[0104] Referring to Figures 12 to 14 , the third mask layer 520 is etched along the first etching groove, so as to form the second etching groove 523 in the third mask layer 520, remove the third anti-reflection layer 522 and the remaining film layers thereon, and retain at least part of the third base layer 521, in which the second etching groove 523 is formed. The third anti-reflection layer 522 and the third base layer 521 are etched along the first etching groove, so as to form the second etching groove 523. In this process, the third anti-reflection layer 522, the second base layer 531, the first intermediate layer 550 and the first filling layer 400 are also removed at the same time, that is, the third base layer 521 is retained, and the second etching groove 523 is formed in the third base layer 521.

[0105] In step S1017, the barrier layer is etched along the second etching groove, so as to form the first groove in the barrier layer.

[0106] Referring to Figure 15 and Figure 16 , the barrier layer 300 is etched along the second etching groove 523, the barrier layer 300 covered by the third base layer 521 is retained, the barrier layer 300 not covered by the third base layer 521 is removed, and the first groove 310 is formed between the retained barrier layers 300. As shown in Figure 15 and Figure 16 , after the first groove 310 is formed, the barrier layer 300 can also have the remaining third base layer 521, that is, the remaining third base layer 521 does not need to be removed separately, and this part of the third base layer 521 can be removed in the subsequent process, so as to simplify the manufacturing process of the semiconductor structure.

[0107] As shown in the top view of Figure 16 , for the convenience of distinction, the area filled with the pattern is the barrier layer 300, and the blank area is the third base layer 521, and the barrier layer 300 and the third base layer 521 are arranged alternately.

[0108] Referring to Figures 15 to 17In some possible embodiments, the step of forming a filling layer 400 in the first trench 310 and forming a first mask layer 510 on the barrier layer 300 and the filling layer 400 (step S103) may include: forming a filling layer 400 in the first trench 310 and forming a first base layer 512 in the second etching trench 523 and on the third base layer 521, wherein the first base layer 512 fills the second etching trench 523 and covers the third base layer 521.

[0109] like Figures 15 to 17 As shown, a first base layer 512 is deposited within the first trench 310, the second etching trench 523, and on the third base layer 521. The first base layer 512 covers the top and side surfaces of the third base layer 521, as well as the top surface of the fill layer 400. Preferably, the first base layer 512 is made of the same material as the third base layer 521, so that the first base layer 512 and the third base layer 521 are integrated, facilitating the subsequent fabrication of the semiconductor structure. Furthermore, the first base layer 512, the third base layer 521, and the fill layer 400 are made of the same material, and the first base layer 512 is in contact with both the third base layer 521 and the fill layer 400, so that these three can form a single unit, facilitating the simultaneous etching of the materials of the first base layer 512, the third base layer 521, and the fill layer 400, simplifying the semiconductor structure fabrication steps.

[0110] Accordingly, refer to Figures 17 to 25 Multiple spaced second trenches 511 are formed within the first mask layer 510. The second trenches 511 extend along a second direction, and the second trenches 511 expose the filler layer 400 (step S104) and may include:

[0111] Step S1041: Form a fourth mask layer on the first mask layer, and form a second photoresist layer on the fourth mask layer.

[0112] refer to Figure 17 and Figure 18 A fourth mask layer 610 is deposited on the first mask layer 510, and a second photoresist layer 620 is coated on the fourth mask layer 610. The second photoresist layer 620 is a patterned second photoresist layer 620, which forms a second pattern through processes such as exposure and development. The second pattern includes a plurality of second through-holes 621, which extend along a second direction and penetrate the second photoresist layer 620, exposing the top surface of the fourth mask layer 610.

[0113] Exemplarily, the fourth mask layer 610 includes a fourth base layer 611 located on the first mask layer 510, and a fourth anti-reflective layer 612 located on the fourth base layer 611. The fourth anti-reflective layer 612 is configured to absorb light of the second photoresist layer 620 during the exposure process, so as to prevent light reflection. The material of the fourth anti-reflective layer 612 can be an organic material similar to the etching property of the first photoresist layer 540, or a combination thereof. The fourth base layer 611 can be made of the same material as the first base layer 512, so as to reduce the materials required in the process of manufacturing the semiconductor structure.

[0114] It should be noted that the first mask layer 510 can include the first base layer 512 and the first anti-reflective layer 513 formed on the first base layer 512. By arranging the first anti-reflective layer 513, the first base layer 512 and the fourth base layer 611 can be separated. The material of the first anti-reflective layer 513 can be the same as that of the fourth anti-reflective layer 612. It can be understood that, in the direction away from the substrate 100, the first base layer 512, the first anti-reflective layer 513, the fourth base layer 611, the fourth anti-reflective layer 612 and the second photoresist layer 620 are sequentially stacked.

[0115] In step S1042, the fourth mask layer is etched by taking the second photoresist layer as a mask, so as to form a fourth groove in the fourth mask layer.

[0116] Reference Figures 17 to 19 The fourth mask layer 610 is etched by taking the second photoresist layer 620 as a mask. After etching, the fourth groove 613 is formed in the fourth mask layer 610, and the fourth groove 613 extends along the second direction. The fourth groove 613 penetrates the fourth base layer 611 and the fourth anti-reflective layer 612, and the fourth groove 613 exposes the top surface of the first mask layer 510. In this process, the second photoresist layer 620 is partially or even completely consumed. For example, as shown in FIG. 6I, the second photoresist layer 620 is completely removed, and the top surface of the fourth mask layer 610 is exposed. Of course, if the second photoresist layer 620 still remains, the remaining second photoresist layer 620 can be removed by a separate ashing process, or can be removed simultaneously when the first mask layer 510 is etched later. Figures 17 to 19

[0117] In step S1043, a second intermediate layer is formed on the sidewall and the bottom of the fourth groove, and the second intermediate layer located in the fourth groove is enclosed to form a second filling groove.

[0118] Reference Figure 19 and Figure 20 ​A second intermediate layer 630 is deposited on the sidewalls and bottom of the fourth trench 613, forming a second filling trench. When the fourth mask layer 610 includes a fourth base layer 611 and a fourth anti-reflective layer 612, the selectivity ratio of the second intermediate layer 630 to the fourth base layer 611 is greater than or equal to 5. This configuration reduces damage to the fourth base layer 611 during the etching of the second intermediate layer 630, thus preserving the fourth base layer 611, which is subsequently used to etch the mask of the first mask layer 510.

[0119] For example, such as Figure 20 As shown, the step of forming a second intermediate layer 630 on the sidewall and bottom of the fourth trench 613, and the second intermediate layer 630 located in the fourth trench 613 forming a second filling trench, includes: depositing the second intermediate layer 630 on the sidewall and bottom of the fourth trench 613 with a fourth mask layer 610, thus facilitating the formation of the second intermediate layer 630.

[0120] Step S1044: Form a second dielectric layer in the second filling groove.

[0121] A second dielectric layer 640 is deposited within the second filling groove to completely fill the second filling groove. The material of the second dielectric layer 640 can be the same as that of the fourth base layer 611, for example, both being spin-coated hard masks.

[0122] Step S1045: Remove part of the second intermediate layer to form multiple spaced third etching grooves.

[0123] refer to Figures 19 to 22 The second intermediate layer 630 located on the sidewall of the fourth trench 613 is etched away to form multiple spaced third etching trenches 650. For example... Figures 19 to 22 As shown, specifically, the second intermediate layer 630 is etched to remove the second intermediate layer 630 located on the sidewall of the fourth trench 613 and on the fourth mask layer 610, forming a third etch trench 650, which exposes the top surface of the fourth mask layer 610.

[0124] like Figures 19 to 22 As shown, in some possible examples, when etching the second intermediate layer 630, portions of the second dielectric layer 640 and the fourth mask layer 610 are also etched away. Specifically, portions of the second dielectric layer 640 are removed, the fourth anti-reflective layer 612 of the fourth mask layer 610 is removed, and portions of the fourth base layer 611 of the fourth mask layer 610 are removed. Figure 22 As shown, the second intermediate layer 630 located at the bottom of the second filling groove, and a portion of the fourth base layer 611 located on the second intermediate layer 630 are retained.

[0125] S1046, etching the first mask layer along the third etching groove to form a second groove in the first mask layer.

[0126] In some possible examples, as shown in Figure 6 and Figure 7 The first base layer 512 covers the barrier layer 300 and the filling layer 400. In the process of etching the first mask layer 510 along the third etching groove 650, the second groove 511 penetrates the first base layer 512, and the groove bottom of the second groove 511 exposes the barrier layer 300 and the filling layer 400.

[0127] In other possible examples, as shown in Figure 22 and Figure 23 The third base layer 521 covers the barrier layer 300, and the first base layer 512 covers the filling layer 400. In the process of etching the first mask layer 510 along the third etching groove 650, the first base layer 512 above the third base layer 521 is etched first to form the second groove 511 in the first base layer 512, and the groove bottom of the second groove 511 exposes the third base layer 521 and the first base layer 512; then, at least the first base layer 512 at the groove bottom of the second groove 511 is etched to extend part of the groove bottom of the second groove 511 to the filling layer 400. For example, the first base layer 512 exposed at the groove bottom of the second groove 511 is etched to extend part of the groove bottom of the second groove 511 to the filling layer 400, and the groove bottom of the second groove 511 exposes the filling layer 400.

[0128] When the material of the first base layer 512 and the third base layer 521 is the same, referring to Figure 24 , the first base layer 512 and the third base layer 521 form an integral whole. In this way, after the second groove 511 is formed in the first base layer 512 above the third base layer 521, the first base layer 512 and the third base layer 521 at the groove bottom of the second groove 511 can be etched to form a long strip-shaped second groove 511 to ensure that the filling layer 400 is fully exposed. For example, Figure 24 The first base layer 512 and the third base layer 521 are etched at the same time, part of the groove bottom of the second groove 511 extends to the filling layer 400, and the other part of the groove bottom exposes the barrier layer 300.

[0129] It can be understood that the first mask layer 510 can include the first base layer 512 and the first anti-reflection layer 513 formed on the first base layer 512, and in the process of etching the first mask layer 510 along the third etching groove 650, the first anti-reflection layer 513 is etched first, and the second groove 511 is formed in the first anti-reflection layer 513; and then the first base layer 512 is etched, so that the second groove 511 extends into the first base layer 512.

[0130] It should be noted that, with reference to Figures 24 to 26 , in the embodiment of the present application, the first mask layer 510 includes the first base layer 512 in contact with the filling layer 400, and the first anti-reflection layer 513 disposed on the first base layer 512, and the filling layer 400 exposed in the second groove 511 and the insulating layer 200 corresponding to the filling layer 400 are removed to form the contact hole 410, the contact hole 410 exposes the active region (step S105), and at the same time, the first anti-reflection layer 513 and the remaining film layer thereon are removed, and at least part of the first base layer 512 is retained. In this way, after the contact hole 410 is formed, the types of film layers above the barrier layer 300 and the remaining filling layer 400 are reduced to facilitate removal.

[0131] It can be understood that when the barrier layer 300 is covered with the third base layer 521, the third base layer 521 and the filling layer 400 are covered with the first base layer 512, as Figure 24 indicated, when the first anti-reflection layer 513 and the remaining film layer thereon are removed, and at least part of the first base layer 512 is retained, part of the first base layer 512 is also retained. When the material of the first base layer 512 and the third base layer 521 is the same, the remaining first base layer 512 and the third base layer 521 can be removed at the same time by etching once, simplifying the manufacturing process of the semiconductor structure.

[0132] With reference to Figures 26 to 34 , in some possible embodiments, after the step of removing the filling layer 400 exposed in the second groove 511 and the insulating layer 200 corresponding to the filling layer 400 to form the contact hole 410, the contact hole 410 exposes the active region (step S105), the method further includes:

[0133] Step a: removing the first mask layer and the filling layer to expose the first groove.

[0134] With reference to Figures 26 to 28 , after the contact hole 410 is formed, the first mask layer 510 and the filling layer 400 are removed, and the first groove 310 is exposed. The first groove 310 is formed between adjacent barrier layers 300, and each first groove 310 communicates with at least one contact hole 410.

[0135] As Figure 26 and Figure 27As shown, after removing the other film layers on the barrier layer 300, and the filler layer 400 between the barrier layers 300, the barrier layer 300 is exposed, as are the insulating layer 200 and the substrate 100. Figure 28 In the top view shown, a substrate 100 and an insulating layer 200 are exposed between adjacent barrier layers 300. The gray area represents the substrate 100, specifically the active region of the substrate 100, while the white area represents the insulating layer 200.

[0136] Step b: A first conductive layer is formed in the first trench and the contact hole, the first conductive layer filling the contact hole and at least part of the first trench.

[0137] refer to Figure 27 and Figure 29 A first conductive layer 710 is deposited within the first trench 310 and the contact hole 410. The first conductive layer 710 can be made of polycrystalline silicon. The first conductive layer 710 fills the contact hole 410 to achieve electrical connection by contacting the active region. The first conductive layer 710 can also fill the first trench 310, and the top surface of the first conductive layer 710 is lower than the top surface of the barrier layer 300. Figure 29 As shown, the first conductive layer 710 fills the bottom of the first trench 310 to prevent the first conductive layers 710 from becoming connected together, thus ensuring the normal operation of the semiconductor structure.

[0138] Step c: Form a second conductive layer on the first conductive layer and the barrier layer, and form a first support layer on the second conductive layer.

[0139] refer to Figure 30 A second conductive layer 720 is formed on the first conductive layer 710 and the barrier layer 300. The second conductive layer 720 fills the first trench 310 and covers the barrier layer 300. The second conductive layer 720 may include the diffusion barrier layer 300 near the substrate 100 and a metal layer disposed on the diffusion barrier layer 300.

[0140] The diffusion barrier layer 300 prevents metal from diffusing into the first conductive layer 710. The material of the diffusion barrier layer 300 may include titanium, titanium nitride, tantalum, tantalum nitride, or aluminum nitride, etc. The diffusion barrier layer 300 may be a single layer or a stacked layer. The material of the metal layer may be copper, aluminum, tungsten, etc. For example, the material of the diffusion barrier layer 300 is titanium nitride, and the material of the metal layer is tungsten.

[0141] like Figure 30 As shown, the second conductive layer 720 is also covered by a first support layer 730. The first support layer 730 can be made of an insulating material, such as silicon nitride or silicon oxynitride, to provide electrical isolation for the second conductive layer 720.

[0142] Step d: removing part of the first support layer and the second conductive layer to form a plurality of fifth trenches which are arranged in intervals and extend along the first direction, and the fifth trenches expose the barrier layer.

[0143] Reference Figures 31 to 33 The first support layer 730 and the second conductive layer 720 are etched to form the fifth trenches 740 which expose the barrier layer 300. The remaining second conductive layer 720 forms a plurality of intervals, and the plurality of second conductive layers 720 correspond to the plurality of first conductive layers 710 one by one, and the corresponding second conductive layer 720 and the first conductive layer 710 are electrically connected.

[0144] In a possible example, referring to Figures 31 to 33 The fifth trenches 740 are formed in the first support layer 730 and the second conductive layer 720 by using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) to improve the density of the fifth trenches 740 and reduce the critical dimension (CD) of the fifth trenches 740.

[0145] Specifically, the amorphous carbon layer 810, the first silicon oxynitride layer 820, the hard mask layer 830, the second silicon oxynitride layer 840, and the third photoresist layer 850 are deposited on the first support layer 730 to form a stack. The third photoresist layer 850 has a third pattern, and the third pattern includes a plurality of third through-slots 851 arranged in intervals, and the third through-slots 851 expose the second silicon oxynitride layer 840. The second silicon oxynitride layer 840 is used to absorb light when the third photoresist layer 850 is exposed. The third pattern is transferred to the hard mask layer 830 by etching the second silicon oxynitride layer 840 and the hard mask layer 830 with the third photoresist layer 850 as a mask. After forming a spacer 860 on the sidewall of the etched hard mask layer 830, the hard mask layer 830 is removed, and the spacer 860 is used as a mask to etch downward to form fourth through-slots in the first silicon oxynitride layer 820 and the amorphous carbon layer 810.

[0146] The fourth through-slots are offset from the first conductive layer 710 on the substrate 100 in orthographic projection to ensure that the remaining second conductive layer 720 is still in contact with the first conductive layer 710 after etching the second conductive layer 720 along the fourth through-slots. The first support layer 730 and the second conductive layer 720 are etched along the fourth through-slots to form the fifth trenches 740.

[0147] It should be noted that, as Figure 33As shown, when the second conductive layer 720 is etched along the fourth trench, the barrier layer 300 can be used as an etching stop layer, i.e., the second conductive layer 720 in the contact hole 410 is not etched, and the etched second conductive layer 720 can be approximately inverted T-shaped.

[0148] Step e: forming a second support layer covering the first support layer and the second conductive layer.

[0149] Reference Figure 33 and Figure 34 The second support layer 760 covers the top surface and side surface of the first support layer 730, and the side surface of the second conductive layer 720, so as to electrically isolate the second conductive layer 720. The second support layer 760 in the fifth trench has a gap therebetween, so as to facilitate subsequent fabrication of a capacitor contact in the gap. The material of the second support layer 760 can be the same as that of the first support layer 730, so that the second support layer 760 and the first support layer 730 are integrated, and layer separation between the second support layer 760 and the first support layer 730 is reduced.

[0150] In some possible embodiments, referring to Figure 34 The second support layer 760 can further be provided with an oxide layer 750, such as a silicon oxide layer, and each first support layer 730 is provided with an oxide layer 750 on both sides thereof, and the oxide layer 750 extends to the side surface of the second conductive layer 720. The first support layer 730 can be a silicon nitride layer, and thus arranged, the layers are in sequence of nitride-oxide-nitride (N-O-N) along the direction away from the side wall of the second conductive layer 720.

[0151] Specifically, a first layer is first deposited on the side wall and the bottom of the fifth trench 740, and the top surface of the first support layer 730, then an oxide layer 750 is deposited on the side surface of the first layer, and then a second layer is deposited on the oxide layer 750 and the first layer, the second layer covers the oxide layer 750 and the first layer, and the first layer and the second layer form the second support layer 760. Of course, the fabrication method of the second support layer 760 is not limited, and other fabrication methods can also be adopted.

[0152] The application further provides a semiconductor structure formed by the fabrication method of the semiconductor structure, and thus has at least the advantages of the fabrication method of the semiconductor structure, and the specific effects are referred to the above, which will not be repeated here.

[0153] The embodiments or implementations in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0154] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the present application. In the description of the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples.

[0155] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The application relates to a method for manufacturing a substrate, which comprises the following steps: providing a substrate, wherein a plurality of active regions are arranged in the substrate, and an insulating layer and a barrier layer are sequentially arranged on the substrate; forming a plurality of first grooves in the barrier layer, wherein the first grooves extend along a first direction and penetrate through the barrier layer; forming a filling layer in the first grooves, and forming a first mask layer on the barrier layer and the filling layer; forming a plurality of second grooves in the first mask layer, wherein the second grooves extend along a second direction, and the second grooves expose the filling layer; removing the filling layer exposed in the second grooves and the insulating layer corresponding to the filling layer, so as to form contact holes, wherein the contact holes expose the active regions; forming a third mask layer, a second mask layer and a first photoresist layer on the barrier layer; taking the first photoresist layer as a mask, etching the second mask layer, and forming third grooves in the second mask layer, wherein the third grooves extend along the first direction; forming a first intermediate layer on the sidewall and the bottom of the third grooves, and the first intermediate layer in the third grooves is enclosed to form a first filling groove; forming a first dielectric layer in the first filling groove; removing part of the first intermediate layer to form a plurality of first etching grooves; etching the third mask layer along the first etching grooves to form second etching grooves in the third mask layer; and etching the barrier layer along the second etching grooves to form the first grooves in the barrier layer. The first mask layer comprises a first base layer in contact with the filling layer, and the material of the first base layer is the same as that of the filling layer. The filling layer and the first base layer are formed by one patterning process. The second mask layer comprises a second base layer on the third mask layer, and a second anti-reflection layer on the second base layer. The first intermediate layer is deposited on the sidewall and the bottom of the third grooves and the second anti-reflection layer. Part of the first intermediate layer, part of the first dielectric layer and the second anti-reflection layer are removed to expose the first intermediate layer on the sidewall of the third grooves. The exposed part of the first intermediate layer is removed to form the first etching grooves. The selection ratio of the first intermediate layer to the second base layer is greater than or equal to 5. The third mask layer comprises a third base layer arranged on the barrier layer, and a third anti-reflection layer arranged on the third base layer. ​ ​ ​ ​ ​ 2. The method of fabricating a semiconductor structure of claim 1, wherein, ​ 3. The method of fabricating a semiconductor structure of claim 2, wherein, ​ 4. The method of fabricating a semiconductor structure of claim 1, wherein, ​ 5. The method of fabricating a semiconductor structure of claim 4, wherein, ​ ​ 6. The method of fabricating a semiconductor structure of claim 5, wherein, ​ ​ ​ 7. The method of fabricating a semiconductor structure of claim 4, wherein, ​ 8. The method of fabricating a semiconductor structure of claim 1, wherein, ​ etching the third mask layer along the first etching groove, forming the second etching groove in the third mask layer, and removing the third anti-reflection layer and the remaining layers on the third anti-reflection layer, while retaining at least part of the third base layer in which the second etching groove is formed.

9. The method of fabricating a semiconductor structure of claim 8, wherein, The step of forming a filling layer in the first trench and forming a first mask layer on the barrier layer and the filling layer comprises: forming a filling layer in the first trench and forming a first base layer in the second etching groove and on the third base layer, the first base layer filling the second etching groove and covering the third base layer.

10. The method of fabricating a semiconductor structure of claim 9, wherein, The first base layer is made of the same material as the third base layer.

11. The method of fabricating a semiconductor structure of claim 9, wherein, The step of forming a plurality of second trenches in the first mask layer, the second trenches being spaced apart and extending along a second direction, and the second trenches exposing the filling layer comprises: etching the first base layer above the third base layer to form the second trenches in the first base layer; etching at least the first base layer at the bottom of the second trench to extend part of the bottom of the second trench to the filling layer.

12. The method of fabricating a semiconductor structure according to any one of claims 2-11, wherein, The step of forming a plurality of second trenches in the first mask layer, the second trenches being spaced apart and extending along a second direction, and the second trenches exposing the filling layer comprises: forming a fourth mask layer on the first mask layer and forming a second photoresist layer on the fourth mask layer; using the second photoresist layer as a mask to etch the fourth mask layer to form a fourth trench in the fourth mask layer; forming a second intermediate layer on the sidewall and the bottom of the fourth trench, and the second intermediate layer in the fourth trench enclosing a second filling groove; forming a second dielectric layer in the second filling groove; removing part of the second intermediate layer to form a plurality of third etching grooves which are spaced apart; etching the first mask layer along the third etching grooves to form the second trenches in the first mask layer.

13. The method of fabricating a semiconductor structure of claim 12, wherein, The first mask layer comprises a first base layer in contact with the filling layer, and a first anti-reflection layer disposed on the first base layer; removing the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer, while also removing the first anti-reflection layer and the remaining layers on the first anti-reflection layer, and retaining at least part of the first base layer.

14. The method of fabricating a semiconductor structure according to any one of claims 1-11, wherein, After the step of removing the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer to form a contact hole exposing the active region, the method further comprises: removing the first mask layer and the filling layer to expose the first trench; forming a first conductive layer in the first trench and in the contact hole, the first conductive layer filling the contact hole and at least part of the first trench; forming a second conductive layer on the first conductive layer and the barrier layer, and forming a first support layer on the second conductive layer; removing part of the first support layer and the second conductive layer to form a plurality of fifth trenches which are spaced apart and extend along a first direction, the fifth trenches exposing the barrier layer; forming a second support layer covering the first support layer and the second conductive layer.

15. A semiconductor structure, characterized by The semiconductor structure is formed by the method of any one of claims 1-14.

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