Method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate, the substrate comprising first regions and second regions which are alternately and spacedly arranged along a first direction; forming a dielectric layer and a first mask layer above the substrate; providing a preset mask with a preset pattern; performing first pattern transfer by using the preset mask to transfer the preset pattern into the first mask layer of the first regions, wherein, in the first pattern transfer step, the preset mask has a first position; performing second pattern transfer by using the same preset mask to transfer the preset pattern into the first mask layer of the second regions, wherein, in the second pattern transfer step, the preset mask has a second position, and the second position is different from the first position; etching the dielectric layer with the first mask layer as a mask to form a contact hole; and forming a bit line contact window which fills the contact hole. At least the accuracy of the size of the bit line contact window can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a manufacturing method of a semiconductor structure. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a kind of semiconductor memory which can write and read data at high speed and randomly, and is widely applied to data storage devices or apparatuses. The DRAM includes a plurality of repeated memory cells, each of which usually includes a capacitor and a transistor, the gate of the transistor is connected with a word line (WL), the drain is connected with a bit line (BL), and the source is connected with the capacitor. A voltage signal on the word line can control the opening or closing of the transistor, and then data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

[0003] In the process of forming the bit line, a bit line contact window needs to be made to make the bit line conduct with other components in the semiconductor structure. However, there are still some problems in the manufacturing method of the bit line contact window at present. SUMMARY

[0004] Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which at least solves the problem that the size of the bit line contact window formed in the semiconductor structure is not accurate enough.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a manufacturing method of a semiconductor structure, which includes: providing a substrate, the substrate including a plurality of active regions separated from each other and isolation regions separating adjacent active regions, the substrate further including first regions and second regions alternately and spaced apart along a first direction, and the first regions and the second regions both extending along a second direction; forming a dielectric layer and a first mask layer stacked in sequence above the substrate; providing a preset mask, the preset mask having a preset pattern; performing first pattern transfer by using the preset mask to transfer the preset pattern into the first mask layer of the first regions, wherein in the first pattern transfer step, the preset mask has a first position compared with the substrate; performing second pattern transfer by using the same preset mask to transfer the preset pattern into the first mask layer of the second regions, wherein in the second pattern transfer step, the preset mask has a second position compared with the substrate, and the second position is different from the first position; etching the dielectric layer with the first mask layer as a mask to form a contact hole exposing part of the surface of the substrate; and forming a bit line contact window filling the contact hole.

[0006] According to another embodiment of the present disclosure, after the step of forming the sequentially stacked dielectric layers and the first mask layer over the substrate, the first pattern transfer is performed before the second pattern transfer.

[0007] According to another embodiment of the present disclosure, the first pattern transfer and the second pattern transfer are performed by: transferring the preset pattern into the first photoresist layer of the first region using the preset mask having the first position relative to the substrate; transferring the preset pattern into the first photoresist layer of the second region using the preset mask having the second position relative to the substrate; and transferring the preset pattern into the first mask layer using the first photoresist layer to complete the first pattern transfer and the second pattern transfer.

[0008] According to another embodiment of the present disclosure, the first photoresist layer is a positive photoresist.

[0009] According to another embodiment of the present disclosure, the first pattern transfer is performed by: transferring the preset pattern into the first photoresist layer of the first region using the preset mask having the first position relative to the substrate; and transferring the preset pattern into the first mask layer using the first photoresist layer to complete the first pattern transfer.

[0010] According to another embodiment of the present disclosure, the step of transferring the preset pattern into the first mask layer includes: etching the first mask layer using the first photoresist layer having the preset pattern as a mask, so that the first opening penetrating through the first mask layer is formed in the first mask layer of the first region.

[0011] According to another embodiment of the present disclosure, the second pattern transfer is performed by: forming a second photoresist layer over the first mask layer; transferring the preset pattern into the second photoresist layer of the second region using the preset mask having the second position relative to the substrate; transferring the preset pattern into the first mask layer using the second photoresist layer to complete the second pattern transfer; and removing the second photoresist layer.

[0012] According to another embodiment of the present disclosure, the step of transferring the preset pattern into the first mask layer using the second photoresist layer includes: etching the first mask layer using the second photoresist layer having the preset pattern as a mask, so that the first opening penetrating through the first mask layer is formed in the first mask layer of the second region.

[0013] According to another embodiment of the present disclosure, before forming the second photoresist layer, the method further comprises: forming a second mask layer on the first mask layer, and a top surface of the second mask layer is higher than a top surface of the first mask layer; the second photoresist layer is located on the second mask layer; and the transferring the preset pattern into the first mask layer by using the second photoresist layer comprises: etching the second mask layer by using the second photoresist layer with the preset pattern as a mask, so as to transfer the preset pattern into the second mask layer; and etching the first mask layer by using the second mask layer with the preset pattern as a mask, so that the first mask layer in the second region forms the first opening penetrating through the first mask layer.

[0014] According to another embodiment of the present disclosure, the method further comprises: forming a third mask layer above the substrate, the third mask layer is located above the dielectric layer, and the first mask layer is located above the third mask layer.

[0015] According to another embodiment of the present disclosure, in the provided preset mask, the preset patterns are arranged at intervals along the first direction, and each row of the preset patterns comprises a plurality of second openings arranged at intervals along the second direction.

[0016] According to another embodiment of the present disclosure, in the preset mask along the first direction, a distance between adjacent second openings is a second distance; in the preset mask along the second direction, a distance between adjacent second openings is a first distance; and the first distance is greater than the second distance.

[0017] According to another embodiment of the present disclosure, the first distance is greater than or equal to 80 nm and less than or equal to 100 nm, and the second distance is greater than or equal to 70 nm and less than or equal to 90 nm.

[0018] According to another embodiment of the present disclosure, in the preset mask along the first direction, the second position is offset from the first position by half of the second distance; and in the preset mask along the second direction, the second position is offset from the first position by half of the first distance.

[0019] According to another embodiment of the present disclosure, in the preset mask, a shape and a size of each second opening are the same.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure first provides a substrate, the substrate includes a plurality of active regions separated from each other and isolation regions separating adjacent active regions, the substrate further includes first regions and second regions alternately and spaced apart along a first direction, and the first regions and the second regions both extend along a second direction. A dielectric layer and a first mask layer are formed on the substrate in sequence. A preset mask is then provided, the preset mask has a preset pattern. The preset pattern is transferred into the first mask layer of the first regions by using the preset mask for a first time, at this time, the preset mask has a first position relative to the substrate. The preset pattern is transferred into the first mask layer of the second regions by using the same preset mask for a second time, at this time, the preset mask has a second position relative to the substrate, the second position is different from the first position. The dielectric layer is etched with the first mask layer as a mask to form a contact hole exposing part of the surface of the substrate. Finally, a bit line contact window is formed to fill the contact hole. In the related art, two preset masks are used to form the bit line contact window in the first regions and the second regions. One of the two preset masks is located at the first position and is used to form the bit line contact window in the first regions, and the other of the two preset masks is located at the second position and is used to form the bit line contact window in the second regions. In theory, the two preset masks have the same preset pattern. However, in the actual production process, it is inevitable that some errors occur when the preset masks are manufactured, which causes the two preset masks to be different, and the size and relative position of the openings constituting the preset pattern in the preset masks can be different. This can cause overlay errors to occur and can cause the critical dimension (CD) of the manufactured bit line contact window to be inconsistent, which can cause the size of the manufactured bit line contact window to be inaccurate. In the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure, only one preset mask is used in the process of forming the bit line contact window, and the bit line contact window is formed in the first regions and the second regions by translating the same preset mask. In this way, the size and relative position of the openings formed in the first regions and the second regions can be kept the same, no overlay errors can occur, the critical dimension of the manufactured bit line contact window can be kept consistent, and the accuracy of the size of the bit line contact window formed in the semiconductor structure can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are included to further provide explanatory aspects relative to the subject matter. Unless otherwise noted, the figures are not drawn to scale. It should be apparent that elements of the drawings can be used in multiple embodiments of the present disclosure while maintaining consistency in the presentation of components across figures. As such, elements shown in one figure can be included with other figures where necessary and practical. For purposes of clarity and understanding, illustrative of the certain aspects of the embodiments are next discussed in terms of the accompanying figures, with several embodiments illustrated in the figures, it should be understood that there is no intention to limit the application to the specific surgical methods disclosed in the illustrations. Although a few embodiments of the application are specifically illustrated and described herein, it is understood that elements can be combined or other embodiments can be used in various combinations to construct additional designs in accordance with the principles of the disclosure.

[0023] Figures 1 to 19 Structure schematic diagram of each step of the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] As can be known from the background, the current manufacturing method of the semiconductor structure has the problem that the size of the formed bit line contact window is not accurate enough.

[0025] The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure. First, a substrate is provided. The substrate comprises a plurality of active regions separated from each other and isolation regions for spacing adjacent active regions, and further comprises first regions and second regions alternately and spaced apart along a first direction, and the first regions and the second regions both extend along a second direction. A medium layer and a first mask layer are formed above the substrate in sequence. A preset mask with a preset pattern is provided. The preset pattern is transferred into the first mask layer of the first region by first pattern transfer using the preset mask, and at this time, the preset mask has a first position relative to the substrate. The preset pattern is transferred into the first mask layer of the second region by second pattern transfer using the same preset mask, and at this time, the preset mask has a second position relative to the substrate, and the first position is different from the second position. The medium layer is etched with the first mask layer as a mask to form a contact hole exposing part of the surface of the substrate. A bit line contact window filling the contact hole is formed. In this way, the accuracy of the bit line contact window formed in the semiconductor structure can be improved.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0027] Figures 1 to 19 Structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure.

[0028] Figure 1 is a top view structure schematic diagram of the substrate, Figure 2 is a cross-sectional structure schematic diagram of the substrate, Figure 2 is Figure 1 is a cross-sectional structure schematic diagram along the AA1 direction.

[0029] Reference Figures 1 to 2, a substrate is provided, the substrate comprises a plurality of active regions 101 and isolation regions 102 which separate the adjacent active regions 101, and the substrate further comprises first regions I and second regions II which are alternately and spacedly arranged along a first direction X, and the first regions I and the second regions II both extend along a second direction Y.

[0030] The material of the active region 101 can comprise silicon, and the isolation region 102 uses an insulating material. The first regions I and the second regions II are used to form bit line contact windows in a subsequent step, and the formed bit line contact windows are located above the first regions I and the second regions II.

[0031] In addition, the substrate can further comprise a word line structure 103, the word line structure 103 comprises a first conductive layer 1031, a second conductive layer 1032 and a word line cap layer 1033, the second conductive layer 1032 is located above the first conductive layer 1031, and the word line cap layer 1033 is located above the second conductive layer 1032 away from the first conductive layer 1031. The word line structure 103 can further have a protective layer 104 between the word line structure 103 and the active region 101, and the protective layer can surround the periphery of the word line structure 103, so that the performance of the word line structure 103 is more stable.

[0032] Figures 3 to 4 A cross-sectional structure diagram of one step in the manufacturing method of the semiconductor structure provided by the embodiment of the present application is shown in the following figure, Figures 3 to 4 The cross-sectional direction of the figure is Figure 1 The BB1 direction. It should be noted that the cross-sectional direction of the subsequent cross-sectional structure diagrams is the BB1 direction, and the subsequent cross-sectional structure diagrams do not show all the structures for the convenience of illustration.

[0033] Referring to Figure 3 The medium layer 110 and the first mask layer 120 are formed above the substrate.

[0034] The first mask layer 120 is used as an intermediate layer in the process of forming the bit line contact window in a subsequent step, and the first mask layer 120 is etched and then the medium layer 110 is etched with the first mask layer 120 as a mask.

[0035] In some embodiments, a third mask layer 130 may be formed above the substrate 100, the third mask layer 130 being located above the dielectric layer 110, and the first mask layer 120 being located above the third mask layer 130. The third mask layer 130 may have multiple stacked film structures. Furthermore, the film structure of the third mask layer 130 may include a first etchable layer 131, a first support layer 132, a second etchable layer 133, and a second support layer 134. The thickness of the first support layer 132 may be less than the thickness of the first etchable layer 131, and the thickness of the second support layer 134 may be less than the thickness of the second etchable layer 133, thus providing support. It is understood that the number of film structures in the third mask layer 130 is variable, and the third mask layer 130 may be a single-layer structure or a multi-layer structure. In subsequent steps, the third mask layer 130 can also serve as an intermediate layer in the bit line contact window formation process. Before etching the medium layer 110 with the first mask layer 120 as the mask, the third mask layer 130 needs to be etched with the first mask layer 120 as the mask.

[0036] Furthermore, a fourth mask layer 140 can be formed above the first mask layer 120. The fourth mask layer 140 can also have multiple stacked film structures. The fourth mask layer 140 may include a third layer to be etched 141 and a third support layer 142. The thickness of the third layer to be etched 141 can be greater than the thickness of the third support layer 142. The number of film structures in the fourth mask layer 140 is variable; the fourth mask layer 140 can be a single-layer structure or a multi-layer structure. In subsequent steps, when etching the first mask layer 120, the fourth mask layer 140 also needs to be etched.

[0037] refer to Figure 4 In some embodiments, after forming a dielectric layer 110 and a first mask layer 120 stacked sequentially on the substrate 100, a first photoresist layer 150 may be formed on the first mask layer 120 before the first pattern transfer. The first photoresist layer 150 will have multiple openings after exposure processing by a photolithography machine in subsequent steps, and the first mask layer 120 can be etched using the exposed first photoresist layer 150 as a mask.

[0038] Figure 5 This is a schematic diagram of the pre-designed photomask. Figure 6 This is a top view of the pre-set photomask structure.

[0039] refer to Figures 5 to 6 A preset photomask 160 is provided, which has a preset pattern.

[0040] In some embodiments, the preset pattern in the preset photomask 160 can include a plurality of preset patterns arranged along a first direction X, and each preset pattern includes a plurality of second openings 161 arranged along a second direction Y.

[0041] In some embodiments, in the preset photomask 160, the distance between adjacent second openings 161 along the first direction X can be a second distance, and the distance between adjacent second openings 161 along the second direction Y can be a first distance. The first distance can be greater than the second distance. The second openings 161 are regularly arranged in the preset photomask 160, and the distance between every two adjacent second openings 161 is the same. The relative positional relationship of the plurality of second openings 161 in the preset photomask 160 is the relative positional relationship of the plurality of bit line contact windows formed in the subsequent steps. The distance between adjacent bit line contact windows along the first direction X can be the second distance, and the distance between adjacent bit line contact windows along the second direction Y can be the first distance.

[0042] In some embodiments, the first distance can be greater than or equal to 80 nm and less than or equal to 100 nm, and the second distance can be greater than or equal to 70 nm and less than or equal to 90 nm. For example, the first distance can be 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, etc., and the second distance can be 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, etc. The values of the first distance and the second distance are the distances between adjacent second openings 161 in the preset photomask 160 along the second direction Y and the first direction X, that is, the distances between adjacent bit line contact windows formed in the subsequent steps along the second direction Y and the first direction X. If the values of the first distance and the second distance are too small, the bit line contact windows formed in the subsequent steps are too close, which will cause a certain degree of waste. If the values of the first distance and the second distance are too large, the distance between the bit line contact windows formed in the subsequent steps is too large, which may not be able to guarantee the performance of the semiconductor structure. Therefore, the values of the first distance and the second distance should be selected within a suitable range. When the first distance is greater than or equal to 80 nm and less than or equal to 100 nm, and the second distance is greater than or equal to 70 nm and less than or equal to 90 nm, the performance of the semiconductor structure can be guaranteed to be good, and waste can be avoided.

[0043] In some embodiments, the shape and size of each second opening 161 in the preset photomask 160 can be the same. The shape and size of the second opening 161 are the shape and size of the bit line contact window formed in the subsequent steps. The shape and size of each second opening 161 are the same, that is, the shape and size of each bit line contact window are the same. The bit line contact windows with the same size can make the semiconductor structure have excellent performance, and the bit line contact windows have better conduction effect.

[0044] In some embodiments, the width of the second opening 161 can be 36-60 nm in the first direction X; and the width of the second opening 161 can be 35-60 nm in the second direction Y. For example, the width of the second opening 161 can be 50 nm, 60 nm, etc. in the first direction X; and the width of the second opening 161 can be 35 nm, 40 nm, etc. in the second direction Y. The width of the second opening 161 in the first direction X and the second direction Y is the width of the bit line contact window formed in the subsequent step in the first direction X and the second direction Y. When the width of the second opening 161 in the first direction X and the second direction Y is appropriately selected, the width of the bit line contact window in the first direction X and the second direction Y is also appropriately selected, which can make the semiconductor structure have excellent performance and the bit line contact window have better conduction effect.

[0045] Figure 7 is a top view structural schematic diagram of a step in the first pattern transfer, Figure 8 is a cross-sectional structural schematic diagram of a step in the first pattern transfer, Figure 8 is a Figure 7 is a cross-sectional structural schematic diagram along the BB1 direction. Figure 9 is a top view structural schematic diagram of a step in the second pattern transfer, Figure 10 is a cross-sectional structural schematic diagram of a step in the second pattern transfer, Figure 10 is a Figure 9 is a cross-sectional structural schematic diagram along the BB1 direction.

[0046] Reference Figures 7 to 16 The first pattern transfer is performed by using the preset mask 160 to transfer the preset pattern into the first mask layer 120 in the first region I. In the first pattern transfer step, the preset mask 160 has a first position relative to the substrate. The second pattern transfer is performed by using the same preset mask 160 to transfer the preset pattern into the first mask layer 120 in the second region II. In the second pattern transfer step, the preset mask 160 has a second position relative to the substrate, which is different from the first position.

[0047] Figure 11 is a top view structural schematic diagram of the preset mask 160 being translated. It should be noted that, for the convenience of illustration, Figure 11 not all structures are shown in the figure.

[0048] Reference Figure 11After the first time of pattern transfer is finished, before the second time of pattern transfer is started, the preset mask 160 needs to be translated, and the preset mask 160 is translated from the first position to the second position. The bit line contact window formed by the preset mask 160 in the first position is located in the first region I, and the bit line contact window formed by the preset mask 160 in the second position is located in the second region II. The bit line contact windows in the first region I and the second region II are formed by translating the same preset mask 160, which can ensure that the critical dimensions and relative positions of the bit line contact windows formed by the first region I and the second region II are the same, and there is no overlay error, which can improve the accuracy of the size of the bit line contact window formed in the semiconductor structure.

[0049] In some embodiments, in the first direction X, the second position is offset from the first position by half of the second distance; in the second direction Y, the second position is offset from the first position by half of the first distance. It can be understood that the distance between the first position and the second position is related to the distance between each second opening 161 in the preset mask 160. In the first direction X, the distance between adjacent second openings 161 is the second distance; in the second direction Y, the distance between adjacent second openings 161 is the first distance. In the first direction X and the second direction Y, the distance offset from the first position to the second position is half of the distance between adjacent second openings 161, which can make the second openings 161 corresponding to the first position and the second position staggered and uniformly arranged. The bit line contact windows formed in the subsequent steps are also staggered and uniformly arranged in the first direction X and the second direction Y, which can improve the performance of the semiconductor structure and improve the conduction effect of the bit line contact window.

[0050] The first time of pattern transfer and the second time of pattern transfer using the preset mask 160 can be performed in various ways. Referring to Figures 7 to 10 In some embodiments, the preset pattern in the first region I and the second region II can be first transferred to the first photoresist layer 150, and then the first time of pattern transfer and the second time of pattern transfer are completed. The specific description of this method will be described below in conjunction with the drawings.

[0051] Referring to Figures 7 to 8 First, the preset pattern is transferred to the first photoresist layer 150 in the first region I by using the preset mask 160 (referring to Figure 6 ) The preset mask 160 has a first position relative to the substrate. The transfer of the preset pattern to the first photoresist layer 150 in the first region I causes the first photoresist layer 150 to have a third opening 151.

[0052] Referring to Figures 9 to 10After the preset pattern is transferred into the first photoresist layer 150 of the first region I, the preset mask 160 is translated so that the preset mask 160 moves from the first position to the second position, and then the second exposure process is performed. The preset pattern is transferred into the first photoresist layer of the second region II by using the same preset mask 160, and at this time, the preset mask 160 has the second position relative to the substrate.

[0053] Reference is made to Fig. 1, which is a schematic diagram of a first photoresist layer 150 and a first mask layer 120. The first photoresist layer 150 is disposed on a substrate 110. The first mask layer 120 is disposed on the first photoresist layer 150. The first mask layer 120 has a first opening 121. The first opening 121 is formed by transferring a preset pattern into the first mask layer 120. Figure 12 After the preset pattern in the first region I and the second region II is transferred into the first photoresist layer 150, the preset pattern in the first region I and the second region II is transferred into the first mask layer 120 by completing the first pattern transfer and the second pattern transfer. The preset pattern is transferred into the first mask layer 120 by using the first photoresist layer 150, so that the first mask layer 120 has the first opening 121. The first pattern transfer and the second pattern transfer are completed.

[0054] The method of performing the first pattern transfer and the second pattern transfer is simple, and the step of transferring the preset pattern in the first region I and the second region II into the first mask layer 120 can be completed by using the same photoresist layer.

[0055] In some embodiments, the first photoresist layer 150 can be a positive photoresist. The positive photoresist has good contrast, and the generated pattern has good resolution.

[0056] The first pattern transfer and the second pattern transfer by using the preset mask 160 can also be performed by using other different methods. Reference is made to Fig. 2, which is a schematic diagram of a first photoresist layer 150 and a first mask layer 120. The first photoresist layer 150 is disposed on a substrate 110. The first mask layer 120 is disposed on the first photoresist layer 150. The first mask layer 120 has a first opening 121. The first opening 121 is formed by transferring a preset pattern into the first mask layer 120. Figures 13 to 17 The first pattern transfer and the second pattern transfer can be performed step by step. First, the preset pattern in the first region I is transferred into the first mask layer 120 by performing the first pattern transfer, and then the preset pattern in the second region II is transferred into the first mask layer 120 by performing the second pattern transfer. The specific method will be described below in combination with the drawings.

[0057] In some embodiments, the step of the first pattern transfer can include the following steps. First, the preset pattern is transferred into the first photoresist layer 150 of the first region I by using the preset mask 160. At this time, the preset mask 160 has the first position relative to the substrate. Figure 13 Figure 6

[0058] Reference is made to Fig. 1, which is a schematic diagram of a first photoresist layer 150 and a first mask layer 120. The first photoresist layer 150 is disposed on a substrate 110. The first mask layer 120 is disposed on the first photoresist layer 150. The first mask layer 120 has a first opening 121. The first opening 121 is formed by transferring a preset pattern into the first mask layer 120. Figure 14 ​​The first photoresist layer 150 is used to transfer the preset pattern into the first mask layer 120, and the first pattern transfer is completed. The step of transferring the preset pattern into the first mask layer 120 can include: taking the first photoresist layer 150 with the preset pattern as a mask, etching the first mask layer 120, so that the first mask layer 120 of the first region I forms the first opening 121 penetrating the first mask layer 120, and the step of transferring the preset pattern of the first region I into the first mask layer 120 is completed.

[0059] After the first pattern transfer is completed, the first photoresist layer 150 needs to be removed. If the fourth mask layer 140 (see Figure 13 ) is still between the first mask layer 120 and the first photoresist layer 150, the fourth mask layer 140 can also be removed.

[0060] In some embodiments, after the first pattern transfer is completed, before the second pattern transfer is performed, the semiconductor structure manufacturing method can further include: referring to Figure 15 , forming a second mask layer 170 on the first mask layer 120, and the top surface of the second mask layer 170 is higher than the top surface of the first mask layer 120. The second mask layer 170 can include a plurality of stacked film layer structures. In the direction away from the dielectric layer 110, the second mask layer 170 can include a fourth to-be-etched layer 171 and a fourth support layer 172. Then, referring to Figure 16 , forming a second photoresist layer 180 on the second mask layer 170.

[0061] Before the second pattern transfer is performed, the preset mask 160 needs to be translated from the first position to the second position.

[0062] After the above steps are completed, the second pattern transfer can be performed. In some embodiments, the step of the second pattern transfer can include: first, taking the preset mask 160 as a photoetching mask to expose the second photoresist layer 180, so that the preset pattern of the second region II is transferred into the second photoresist layer 180, and the fourth opening 181 is formed in the second photoresist layer.

[0063] Referring to Figure 17 , the second photoresist layer 180 (see Figure 16)After exposure, the preset pattern can be transferred to the first mask layer 120. First, the second photoresist layer 180 with the preset pattern is used as a mask to etch the second mask layer 170, so that the preset pattern is transferred to the second mask layer 170. Then, the second mask layer 170 with the preset pattern is used as a mask to etch the first mask layer 120, so that the first opening 121 penetrating the first mask layer 120 is formed in the first mask layer 120 of the second region II, and the preset pattern of the second region II is transferred to the first mask layer 120, completing the second pattern transfer.

[0064] After the second pattern transfer is completed, the second mask layer 170 (see Figure 16 ) and the second photoresist layer 180 above the first mask layer 120 can be removed. At this time, the first mask layer 120 has the first opening 121 in the first region I and the second region II, and the preset pattern in the first region I and the second region II has been transferred to the first mask layer 120.

[0065] The above method performs the first pattern transfer and the second pattern transfer step by step, needs to use two photoresist layers, and the steps of the entire pattern transfer are more clear. Moreover, since the second photoresist layer 180 is exposed and processed before the exposure step of the second pattern transfer is performed, the exposure processing is more realizable and accurate.

[0066] Referring to Figure 18 , the first mask layer 120 is used as a mask to etch the dielectric layer 110, so that the contact hole 111 exposing the surface of the substrate is formed. If the dielectric layer 110 also has the third mask layer 130, the third mask layer 130 also needs to be etched. The contact hole 111 formed here is distributed in the first region I and the second region II, and the size and relative position of the contact hole 111 are consistent with the size and relative position of the second opening 161 in the preset mask 160 (see Figure 6 ).

[0067] Referring to Figure 19 , the bit line contact window 190 filling the contact hole 111 is formed. The bit line contact window 190 is used to connect the bit line structure and the substrate. The bit line contact window 190 is distributed in the first region I and the second region II, and the size and relative position of the bit line contact window 190 are consistent with the size and relative position of the second opening 161 in the preset mask 160.

[0068] According to the experiment, the beneficial effect of the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure on the accuracy of the bit line contact window 190 can be verified. By comparing the bit line contact window manufactured by the traditional method and the bit line contact window 190 manufactured by the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure, all the bit line contact windows 190 located in the first region I can be positioned to a coordinate center, all the bit line contact windows 190 located in the second region II can be positioned to another coordinate center, and the overlay error can be obtained by subtracting the two coordinate centers. It can be concluded that the overlay error of the bit line contact window 190 manufactured by the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is obviously smaller than the overlay error generated by the traditional method. Similarly, the critical dimensions of all the bit line contact windows 190 located in the first region I have an average value, and the critical dimensions of all the bit line contact windows 190 located in the second region II have another average value. The accuracy of the critical dimensions of the bit line contact window 190 can be judged by subtracting the two average values. It can be seen that the critical dimensions of the bit line contact window 190 manufactured by the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure tend to be consistent.

[0069] The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure. First, a substrate is provided. The substrate includes a plurality of active regions separated from each other and isolation regions for isolating adjacent active regions. The substrate also includes a first region I and a second region II arranged at intervals along a first direction X, and the first region I and the second region II both extend along a second direction Y. A first mask layer and a dielectric layer are formed above the substrate in a stacked manner. A preset mask is provided. The preset mask has a preset pattern. The preset pattern is transferred to the first mask layer in the first region I by using the preset mask for the first time, and at this time, the preset mask is located at a first position. The preset pattern is transferred to the first mask layer in the second region II by using the same preset mask for the second time, and at this time, the preset mask is located at a second position, and the first position is different from the second position. The dielectric layer is etched with the first mask layer as a mask to form a contact hole exposing part of the surface of the substrate. A bit line contact window is formed to fill the contact hole. The occurrence of overlay error can be avoided, the critical dimensions of the bit line contact window are kept consistent, and the accuracy of the dimensions of the bit line contact window formed in the semiconductor structure is improved.

[0070] Correspondingly, another embodiment of the present disclosure also provides a semiconductor structure, which is manufactured by the above-mentioned manufacturing method of a semiconductor structure. The semiconductor structure provided by the another embodiment of the present disclosure will be described in detail below with reference to the drawings. The same or corresponding parts of the semiconductor structure provided by the another embodiment of the present disclosure can refer to the corresponding description of the foregoing embodiment, and will not be described in detail below.

[0071] Figure 19 A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 1. Figure 19 The substrate is not shown in FIG. 1.

[0072] Reference Figure 2 and Figure 19 The semiconductor structure comprises: a substrate, the substrate comprises a plurality of active regions 101 and isolation regions 102 which separate adjacent active regions 101, the substrate further comprises first regions I and second regions II which are alternately and spacedly arranged along a first direction X, and the first regions I and the second regions II both extend along a second direction Y; a dielectric layer 110 which is above the substrate; bit line contact windows 190 which are in the dielectric layer 110 and penetrate the dielectric layer 110 in a direction perpendicular to the substrate, and the bit line contact windows 190 are in contact with the surface of the substrate; wherein the bit line contact windows 190 are in the first regions I and the second regions II, in the first regions I, a plurality of rows of bit line contact windows 190 are spacedly arranged along the first direction X, and in each row of bit line contact windows 190 in the first regions I, a plurality of bit line contact windows 190 are spacedly arranged along the second direction Y; the relative position relationship of the bit line contact windows 190 in the second regions II is the same as that of the bit line contact windows 190 in the first regions I.

[0073] In some embodiments, the semiconductor structure can further comprise word line structures 103 which are on the surface of the substrate and are also in the isolation regions 102. The word line structures 103 are used to connect gates in the active regions 101.

[0074] In some embodiments, the critical dimensions of the bit line contact windows 190 tend to be consistent, and the relative position relationship of the bit line contact windows 190 in the first regions I is the same as that of the bit line contact windows 190 in the second regions II, so that the accuracy of the bit line contact windows 190 is higher, the conduction of the bit line contact windows 190 is more stable, and the performance of the semiconductor structure is improved.

[0075] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of mutually independent active regions and an isolation region separating adjacent active regions, the substrate also including a first region and a second region alternately spaced along a first direction, and both the first region and the second region extending along a second direction; A dielectric layer and a first mask layer are formed sequentially stacked on the substrate; A preset photomask is provided, the preset photomask having a preset pattern; The preset photomask is used to perform a first pattern transfer, transferring the preset pattern to the first mask layer in the first region, wherein, in the first pattern transfer step, the preset photomask has a first position relative to the substrate; A second pattern transfer is performed using the same preset photomask to transfer the preset pattern into the first mask layer of the second region. In the second pattern transfer step, the preset photomask has a second position relative to the substrate, and the second position is different from the first position. Using the first mask layer as a mask, the dielectric layer is etched to form contact holes that expose the surface of the substrate portion; A bit line contact window is formed that fills the contact hole.

2. The manufacturing method as described in claim 1, characterized in that, After forming a dielectric layer and a first mask layer stacked sequentially on the substrate, before performing the first pattern transfer, the method further includes forming a first photoresist layer on the first mask layer.

3. The manufacturing method as described in claim 2, characterized in that, The steps of the first graphic transfer and the second graphic transfer include: The preset pattern is transferred into the first photoresist layer in the first region using the preset photomask, wherein the preset photomask has the first position relative to the substrate; The preset pattern is transferred to the first photoresist layer in the second region using the same preset photomask, wherein the preset photomask has the second position relative to the substrate; The preset pattern is transferred to the first mask layer using the first photoresist layer, thus completing the first pattern transfer and the second pattern transfer.

4. The manufacturing method as described in claim 3, characterized in that, The first photoresist layer is a positive photoresist.

5. The manufacturing method as described in claim 2, characterized in that, The steps of the first graphic transfer include: The preset pattern is transferred into the first photoresist layer in the first region using the preset photomask, wherein the preset photomask has the first position relative to the substrate; The preset pattern is transferred into the first mask layer using the first photoresist layer, thus completing the first pattern transfer. Remove the first photoresist layer.

6. The manufacturing method as described in claim 5, characterized in that, The step of transferring the preset pattern into the first mask layer includes: Using the first photoresist layer with the preset pattern as a mask, the first mask layer is etched to form a first opening penetrating the first mask layer in the first region.

7. The manufacturing method as described in claim 6, characterized in that, The second graphic transfer step includes: A second photoresist layer is formed on the first mask layer; The preset pattern is transferred to the second photoresist layer in the second region using the preset photomask, wherein the preset photomask has the second position relative to the substrate; The preset pattern is transferred into the first mask layer using the second photoresist layer, thus completing the second pattern transfer. Remove the second photoresist layer.

8. The manufacturing method as described in claim 7, characterized in that, The step of transferring the preset pattern into the first mask layer using the second photoresist layer includes: The first mask layer is etched using the second photoresist layer having the preset pattern as a mask, so that the first opening penetrating the first mask layer is formed in the first mask layer in the second region.

9. The manufacturing method as described in claim 7, characterized in that, Before forming the second photoresist layer, the process also includes: A second mask layer is formed on the first mask layer, and the top surface of the second mask layer is higher than the top surface of the first mask layer; the second photoresist layer is located on the second mask layer; The step of transferring the preset pattern into the first mask layer using the second photoresist layer includes: Using the second photoresist layer with the preset pattern as a mask, the second mask layer is etched to transfer the preset pattern into the second mask layer; Using the second mask layer having the preset pattern as a mask, the first mask layer is etched to form the first opening penetrating the first mask layer in the second region.

10. The manufacturing method as described in claim 1, characterized in that, Also includes: A third mask layer is formed above the substrate, the third mask layer is located above the dielectric layer, and the first mask layer is located above the third mask layer.

11. The manufacturing method as described in claim 1, characterized in that, In the provided preset photomask, the preset patterns are arranged at intervals along the first direction, and each row of the preset patterns includes a plurality of second openings arranged at intervals along the second direction.

12. The manufacturing method as described in claim 11, characterized in that, Along the first direction, the distance between adjacent second openings in the preset light cover is a second distance; along the second direction, the distance between adjacent second openings in the preset light cover is a first distance; wherein, the first distance is greater than the second distance.

13. The manufacturing method as described in claim 12, characterized in that, The first distance is greater than or equal to 80nm and less than or equal to 100nm; the second distance is greater than or equal to 70nm and less than or equal to 90nm.

14. The manufacturing method as described in claim 12, characterized in that, Along the first direction, the second position is offset by half a second distance relative to the first position; along the second direction, the second position is offset by half a first distance relative to the first position.

15. The manufacturing method as described in claim 11, characterized in that, In the preset light cover, each of the second openings has the same shape and size.

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