data conversion tracking of received data

Abstract

The signal conditioning circuitry (400) includes logic circuitry (402), a low pass filter (404), and comparator circuitry (406). The logic circuitry (402) is configured to compare a data unit from a sequence of data units with a previous data unit and provide a logic output signal. The low pass filter (404) is coupled to the logic circuitry (402), and the low pass filter (404) is configured to provide a data transition density measure of the sequence of data units based on the logic output signal. The comparator circuitry (406) is coupled to the low pass filter (404), and the comparator circuitry (406) is configured to compare the data transition density measure to a threshold value and, based on the comparison to the threshold value, indicate a disruptive pattern in the sequence of data units.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to data transmission, and more specifically to data transition tracking of received data. BACKGROUND

[0002] When a transmitter transmits a signal containing data (referred to herein as a data signal or signal) across a communication channel, such as a high speed data (HSD) signal, the signal leaving the channel can be distorted relative to the signal entering the channel. Distortion compensation circuitry, such as an equalizer or a clock and data recovery (CDR) circuit, can receive the signal leaving the channel and perform distortion compensation on the signal before providing the signal to a receiver. SUMMARY

[0003] In some cases, such as in the presence of a disruptive data pattern, some or all of the distortion compensation circuitry can fail to reliably perform its intended function. As used herein, a disruptive data pattern is a sequence of data units (e.g., a sequence of data bits) having a pattern of values, amplitudes, or magnitudes that can cause a circuit to operate in a manner that results in a failure to comply with performance or operational standards or can cause the circuit to fail completely. In this sense, a disruptive data pattern can be considered a “pathological” sequence of data or a “pathological” pattern for the distortion compensation circuit. In cases where the distortion compensation circuit is adaptive or performs adaptive operations (also referred to as adaptation), operating the distortion compensation circuit (e.g., adaptation) during a disruptive data pattern or pathological pattern can cause the circuit to deviate from its preferred tuning.

[0004] The described examples can be used to monitor for changes or transitions in data and detect a disruptive data pattern in a sequence of data units. Accordingly, one or more of the distortion compensation circuits can be gated, e.g., suspended from adaptation or restarted, in the presence of a disruptive data pattern and allowed to fully operate, e.g., resume adaptation, in the absence of a disruptive data pattern. Without one or more of the described examples, in addition to the problems described above, channel coverage extension provided by the distortion compensation circuitry can degrade by 50% or more in cases where the distortion compensation circuitry includes an equalizer and a CDR circuit. The described example or examples can reduce or eliminate this coverage extension loss. Furthermore, the described example or examples can prevent the equalizer and / or CDR circuitry from failing, thereby maintaining the integrity of the data signal in the presence of a disruptive data pattern.

[0005] In one example, signal conditioning circuitry includes logic circuitry, a low pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit from a sequence of data units with a previous data unit and provide a logic output signal. The low pass filter is coupled to the logic circuitry and the low pass filter is configured to provide a data transition density measure for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low pass filter and the comparator circuitry is configured to compare the data transition density measure to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units. The indication of a disruptive pattern can be provided to distortion compensation circuitry such that at least one aspect or portion of the distortion compensation circuitry (e.g., adaptation) can operate in the absence of a disruptive pattern and be suspended or reset (generally referred to herein as "gated" or "gated on") in the presence of a disruptive pattern.

[0006] In another example, signal conditioning circuitry includes data transition tracking circuitry and an equalizer. The data transition tracking circuitry includes an exclusive OR gate, a low pass filter coupled to the exclusive OR gate, and a comparator circuitry coupled to the low pass filter. The comparator circuitry is configured to compare a data transition density measure to a threshold and, based on the comparison, indicate a disruptive pattern in a sequence of data units. The equalizer is coupled to the comparator circuitry and configured to gate adaptive operation in response to the indication.

[0007] In another example, a method includes comparing a data unit from a sequence of data units with a previous data unit and providing a logic output signal. The method also includes generating a time-averaged signal based on the logic output signal. The method also includes comparing the time-averaged signal to a threshold and, based on the comparison to the threshold, indicating a disruptive pattern in the sequence of data units. The method further includes gating adaptive operation of distortion compensation circuitry in response to the indication of a disruptive pattern. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 An example communication system with data transition tracking circuitry is depicted.

[0009] Figure 2 An example distortion compensation circuitry that can be implemented in Figure 1 Example distortion compensation circuitry that can be implemented in the illustrated system.

[0010] Figure 3 An example signal conditioning circuitry is depicted. Figure 1 A portion of the signal conditioning circuitry illustrated in the example distortion compensation circuitry.

[0011] Figure 4An example signal conditioning circuit system with data conversion tracking circuitry is depicted.

[0012] Figure 5 An example method of operating a signal conditioning circuit system is depicted. Figure 4 A timing diagram of the operation of the signal conditioning circuit system shown in

[0013] Figure 6 An example method of operating a signal conditioning circuit system is depicted. Figure 2 and 4 Simulation results for the signal conditioning circuit system shown in

[0014] Figure 7 An example method of operating a signal conditioning circuit system is depicted. Figure 2 and 4 Simulation results for the signal conditioning circuit system shown in

[0015] Figure 8 An example signal conditioning circuit system with data conversion tracking circuitry is depicted.

[0016] Figure 9 An example method of operating a signal conditioning circuit system is depicted. Figure 2 and 8 Simulation results for the signal conditioning circuit system shown in

[0017] Figure 10 An example signal conditioning circuit system with data conversion tracking circuitry is depicted.

[0018] Figure 11 An example signal conditioning circuit system with data conversion tracking circuitry is depicted.

[0019] Figure 12 An example signal conditioning circuit system with data conversion tracking circuitry is depicted.

[0020] Figure 13 A flowchart of an example method of operating a signal conditioning circuit system with data conversion tracking circuitry is depicted. DETAILED DESCRIPTION

[0021] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the specification and claims, the terms "including" and "comprising," along with their derivatives, are intended to be construed open-ended, in a similar manner to the term "comprising," unless otherwise indicated. Additionally, the terms "couple," "coupled," and "coupling" mean to indirectly or directly connect or support.

[0022] Reference is first made to Figure 1which depicts an example communication system 100 having data transition tracking circuitry 124 according to the present teachings. The system 100 includes a transmitter 102, signal conditioning circuitry 106, and a receiver 108 coupled as illustrated. Within the communication system 100, the transmitter 102 can transmit a data signal TX

[0023] As illustrated, the signal conditioning circuitry 106 is separate from the receiver 108. For example, the signal conditioning circuitry 106 is included on a chip or die separate from one or more chips or dies that include circuitry of the receiver 108. However, the chip including the signal conditioning circuitry 106 and the one or more chips including the receiver 108 can share, e.g., can be mounted to, a common printed circuit board (PCB). Alternatively, the signal conditioning circuitry 106 can be integrated into the receiver 110, as illustrated by the dashed box representing the receiver 110. For example, the circuitry of the signal conditioning circuitry 106 and the receiver 110 is included on the same chip.

[0024] Also, although a one-way communication is depicted, as illustrated by the arrow, the channel 104 can be used for two-way communication. Thus, the transmitter 102 and the receiver 108 each are included in a transceiver (not shown). Also, in the example of two-way communication, the signal conditioning circuitry 106 can also be included on the transmitter 102 side of the channel 104.

[0025] During operation of the system 100, the transmitter 102 transmits a data signal TX OUT using the channel 104. The channel 104 can be a "lossy" channel that distorts TX OUT during transmission, such that a distorted signal CHAN OUT is output from the channel 104. Figure 126 depicts an example eye diagram representing TX OUT , and Figure 128 depicts an example eye diagram representing CHAN OUT . As illustrated by the eye diagrams, transitions in the data shown in the eye diagram 126, e.g., 130 and 132, are not detectable in the eye diagram 128, and can be difficult to distinguish from noise. The distortion compensation circuitry 112 receives CHAN OUT and corrects for distortion in the signal to provide a less distorted signal RX IN to the receiver 108.

[0026] In one example, the data signal TX OUT is a high-speed serial data stream represented as a voltage, where“high-speed” can correspond to 1 gigabit per second (Gbps) or higher. For example, a 0 can be approximately -500 millivolts (mV), and a 1 can be approximately 500 mV. In a particular example, the data signal TX OUT is a wideband 4K or higher resolution digital video signal transmitted at 10 Gbps or higher and having frequency content from the Nyquist to much lower frequencies. Thus, the transmitter 102 can be a video camera outputting a video signal. The channel 104 can be a coaxial cable having an associated connector coupled between the transmitter 102 and the receiver 108 and used to send the video signal to the receiver 108. The receiver 108 performs digital signal processing on the received signal and outputs the video content to an output device (not shown), such as a television screen or monitor.

[0027] However, implementations are not limited to these examples. That is, the transmitter 102 and receiver 108 can be any two endpoints of a data signal sent through a physical medium represented by the channel 104. For example, in another example, the transmitter 102 is a microcontroller or central processing unit sending TX OUT to the receiver 108 over the channel 104, the receiver 108 is a storage device or graphics controller, and the channel 104 is a trace on a PCB, such as a motherboard or daughter card. In other examples, the channel 104 is an HDMI cable, a USB cable, or a fiber optic link. In yet another example, the channel 104 is a wireless medium, where TX OUT is a modulated signal and / or an analog signal, and the transmitter 102 and receiver 108 have wireless capabilities. In the case of wireless transmission, demodulation circuitry (not shown) can be coupled to the channel 104 to receive and demodulate CHAN OUT and provide a demodulated signal to the signal conditioning circuitry 106.

[0028] As a high-speed wideband signal propagates, the channel 104 can attenuate the higher frequency content of the signal as a function of frequency, effectively behaving as a low-pass filter. The signal CHAN OUT output from the channel 104 can also include amplitude and / or timing (time) noise, referred to as jitter. The distortion compensation circuitry 112 removes at least some of the distortion on CHAN OUT and outputs an RX OUT signal that is closer to TX IN , allowing for data recovery in the receiver circuitry 108. That is, the equalizer 116 acts as a high-pass filter that compensates for the frequency-dependent loss in the channel 104 by adding gain back to the higher frequency content attenuated by the channel 104. The CDR 118 re-timed the equalized signal to remove jitter and CHANOUT At least some distortion. The equalization and / or retiming signal is the distortion compensation signal RX provided to the receiver 108. IN and the signal CTRL provided to the data unit delay circuit system 122 IN It contains data units. When CDR 118 is not used, the output of equalizer 116 can be provided to data unit extraction circuitry 120 (e.g., decision circuitry) to provide CTRL. IN Although not shown for simplicity, the distortion compensation circuitry 112 may also include an output driver to drive the channel between the distortion compensation circuitry 112 and the receiver 108, such as a cable, link, or trace on a PCB.

[0029] Figure 2 Depicting can be Figure 1 The system shown implements an example distortion compensation circuit system 112. More specifically, Figure 2 This illustrates an example of a retimer circuit implementation. In this example, the distortion compensation circuit system 112 includes both an equalizer 116 and a CDR 118. The distortion compensation circuit system also includes, as described, an input termination circuit 200, an equalization (EQ) adaptive control circuit system 204, and a decision circuit 206 coupled as described. In this example, the CDR 118 is implemented as a phase-locked loop (PLL) and includes, as described, a phase-frequency detector 210, a charge pump 212, a low-pass filter 214, and a voltage-controlled oscillator (VCO) 216 coupled as described. The low-pass filter includes, as described, a resistor 226, a capacitor 228, and a capacitor 232 coupled between the output of the charge pump 212 and a reference voltage 230 (e.g., ground).

[0030] In another implementation, PLL 118 includes a divide-by-N block 218 that divides the frequency of VCO 216 by a factor of N. Therefore, block 218 is also referred to herein as frequency divider 218. Furthermore, as shown, CDR 118 uses a locally generated clock from VCO 216 to retime the signal from equalizer 116 to generate a retimed signal RX. IN .

[0031] As explained, the CDR 118 is implemented using a second-order analog PLL, and is therefore also referred to herein as a PLL 118. Alternatively, the CDR 118 is implemented using a digital PLL or a delay-locked loop (DLL). In another example implementation, the CDR is phase interpolator-based, which uses a PLL or DLL to implement a reference loop that accepts an input reference clock signal and generates a set of high-speed clock signals used as reference phases. These reference paths are fed to a CDR loop that includes circuitry for selecting a reference phase pair and interpolating between them to provide a clock used to recover data from the data signal. Also, for simplicity, the illustrated distortion compensation circuitry 112 shows the equalizer 116, decision circuit 206, and phase-frequency detector 210 as separate circuit blocks. However, there can be some overlap between the circuitry of these blocks.

[0032] During operation of the distortion compensation circuitry 112, the CHAN OUT signal (as represented by eye diagram 128) is received into the input termination circuitry 200. In an example, the input termination circuitry 200 includes one or more resistors that perform impedance matching when passing the CHAN OUT signal to the equalizer 116. As previously mentioned, the equalizer 116 acts as a high-pass filter that compensates for frequency-dependent losses in the CHAN OUT signal, resulting in an equalized signal (EQ OUT ) 202. The equalized signal 202 is represented by eye diagram 222. As can be seen in the eye diagram 222, transitions in the data are detectable. However, as can also be seen in the eye diagram 222, some noise and jitter remains in the equalized signal 202.

[0033] The equalizer 116 can include a continuous-time linear equalizer (CTLE), a feed-forward equalizer (FFE) with one or more taps, a decision feedback equalizer (DFE) with one or more taps and also including a decision circuit as part of a feedback loop, or a combination. The EQ adaptive control circuitry 204 allows the equalizer 116 to be adaptive by tuning or adjusting the settings (e.g., gain and transfer function) of the equalizer 116 based on conditions in the channel 104 or other conditions or changes in the system, such as changes in temperature and / or supply voltage. The EQ adaptive control circuitry 204 can be implemented as a combination of hardware controllers and memory, or as a combination of sequential logic and combinational logic.

[0034] In one example implementation, prior to CDR lock, the EQ adaptive control circuitry 204 can search or "sweep" equalizer settings to establish initial settings to achieve CDR lock. At CDR lock, the frequency and phase of the clock signal is adjusted so that the clock edges align with the equalized signal 202. These initial equalizer settings can correspond to, for example, the length of the channel 104 (e.g., the length of a cable) and the associated attenuation of the channel 204, which are a priori unknown. Thereafter, as temperature and / or power supply voltage slowly change over time, these initial equalizer settings (e.g., the gain and transfer function of the equalizer 116) can be incrementally adjusted under the control of the EQ adaptive control circuitry 204.

[0035] In Figure 2 In the example retimer circuit implementation shown, the equalized signal 202 is fed to the decision circuit 206 and the PLL 118. In the absence of the PLL 118, such as in a redriver circuit implementation, the equalized signal 202 is fed to the decision circuit 206 and can also be fed directly to the receiver 108 (not shown). In both the retimer and redriver examples, the decision circuit 206 determines at a given point in time whether the data in the equalized signal 202 is a 0 (low) or a 1 (high). In this sense, the decision circuit functions as data cell extraction circuitry.

[0036] In one example redriver circuit implementation, the decision circuit 206 is a limiting or clipper amplifier that attempts to slice the equalized eye (e.g., element 236 shown in FIG. 222) at zero volts or at the center of the eye 236. If the slicer output is greater than 0 (or the center of the equalized eye), the amplifier boosts the signal 202 until it clips in the positive direction. But if the slicer output is less than 0 (or the center of the equalized eye), the amplifier boosts the signal until it clips in the negative direction. In this way, the decision circuit 206 can reduce some voltage noise, but it does not address the timing noise (jitter) associated with the equalized eye 236. The decision circuit 206 then provides the decision as CTRL IN which includes a sequence of data cells, to the data cell delay circuitry 122.

[0037] In Figure 2 In the example retimer circuit implementation shown, the PLL 118 receives the equalized signal 202 into the phase-frequency detector 210. When the frequency divider 218 is implemented, the phase-frequency detector 210 monitors the phase error in the signal 202 relative to the frequency of the VCO 216 or a fraction of the frequency of the VCO 216. Based on the phase error, the PLL 118 adjusts the frequency and phase of the VCO 216 output (the clock signal 208) to the center of the timing noise distribution using the charge pump 212 and the low pass filter 214.

[0038] The clock signal 208 from the VCO with adjusted phase and frequency is provided to the decision circuit 206 and the feedback loop of the PLL 118. The decision circuit 206 uses the clock signal 208 to retime the equalized signal 202 to eliminate timing alignment errors and thereby generate a retimed signal RX IN and a retimed signal CTRL IN . RX IN is represented by eye diagram 224, which is closer to TX OUT or the equalized signal 202 than CHAN OUT . That is, the decision circuit 206 makes a decision about the equalized signal 202 at a given clock edge of the clock signal 208 (i.e., for each bit) whether the equalized signal 202 is a 1 or a 0. To do so, the decision circuit 206 is designed to sample at the center of the open eye 236 of the equalized signal 202 with the phase / frequency aligned clock signal 208 to determine whether the sample is a 1 or a 0. This results in a reduction of both amplitude noise and timing noise of the signal 202.

[0039] The decision circuit 206 can also include lock detection circuitry (not shown), which can include one or more registers and flip-flops. The lock detection circuitry determines when the CDR has achieved lock on the equalized signal 202 by comparing the frequency and phase of the equalized signal 202 to the frequency and phase of the clock signal 208. In a particular example implementation, prior to achieving CDR lock, the decision circuit 206 provides the retimed equalized signal 202 as CTRL IN to the data unit delay circuitry 122. However, initially there is no RX IN signal provided to the receiver 108 because the signal can have an error rate, e.g., a bit error rate, that exceeds an acceptable threshold. After CDR lock, the decision circuit 206 provides the retimed CTRL IN to the data unit delay circuitry 122 and the retimed RX IN to the receiver 108.

[0040] The PLL 118 is also adaptive. More specifically, after the CDR has achieved lock on the equalized signal 202, the PLL 118 keeps the clock signal 208 from the VCO 216 aligned with the equalized signal 202 in the presence of noise, whether caused by the channel 104 or by the circuitry 112. When the clock signal 208 deviates from the ideal value due to noise or temperature / power supply voltage variations (also referred to as "search jitter"), the phase-frequency detector 210 detects the deviation from alignment or search jitter. The PLL 118 then uses the charge pump 212 and the low pass filter 214 to pull the clock signal 208 back into alignment with the equalized signal 202, reducing the search jitter.

[0041] A problem with the distortion compensation circuitry 112 is that one or both of the equalizer 116 and the CDR 118 can fail or can operate unreliably in the presence of certain data sequences or patterns. For example, both the equalizer 116 and the CDR 118 are designed to operate reliably in the presence of random or pseudo-random (e.g., scrambled) data. Thus, for the equalizer 116 and / or the CDR 118, a pathological pattern or a disruptive pattern in a sequence of data units (e.g., a sequence of bits) contains data that is no longer random or pseudo-random. For example, a pathological pattern that can disrupt the operation of the equalizer 116 or the CDR 118 is a sequence of consecutive identical digits (CID), such as a sequence of consecutive 1s or a sequence of consecutive Os, or some other repetitive pattern, such as a sequence of alternating Is and Os.

[0042] One example pathological pattern is data for a clock signal or an analog clock signal that has an alternating pattern of Is and Os. In digital video applications, an example pathological pattern can be a single 0 followed by 19 ones, or a single 1 followed by 19 zeros, which can represent, for example, the color magenta. In other applications, different data sequences can result in pathological patterns for the distortion compensation circuitry.

[0043] The pathological pattern can cause any number of problems in the operation of the equalizer 116 and the CDR 118. For example, the pathological pattern can cause an increase in search jitter, which causes the CDR 118 to lose lock, preventing data recovery. In another example, the pathological pattern causes the equalizer 116 to lose its current and preferred settings, which causes noise and resulting errors in the recovered data. In yet another example, the pathological pattern causes the equalizer 116 to fail, which also prevents data recovery.

[0044] One solution is to reduce the bandwidth of the CDR 118, which reduces its response time deviation in data clock alignment. Another solution is to over-design the receiver 108 with sufficient margin to tolerate increased search jitter and / or sub-optimal equalizer settings. However, these solutions can result in one or more performance parameters of the overall receiver system being sacrificed, a more expensive receiver due to increased power consumption and circuit complexity, and / or failure of other specifications of the receiver system.

[0045] A solution according to this description is to detect ill-conditioned patterns in the data and to gate“operation” in the presence of ill-conditioned patterns, which can include gating adaptive behavior of one or more of the distortion compensation circuits (e.g., the equalizer 116 and / or the CDR 118). That is, data transition tracking circuitry can be used to track a data transition density (DTD) measure of a sequence of data units (e.g., a sequence of bits), and to suspend equalizer 116 adaptation and to suspend or reset CDR 118 phase / frequency tracking, for example, when the DTD measure indicates the presence of ill-conditioned patterns in the data stream. Once the ill-conditioned patterns are no longer detected, at least a portion or aspect of the equalizer 116 and CDR 118 operation (e.g., adaptation) can be ungated or allowed to operate and tune their respective blocks.

[0046] “Data transition density” or“DTD” is a ratio of data unit transitions to total number of data units in a period of time. For example, DTD is a ratio of the number of transitions (e.g., from 0 to 1 or 1 to 0) in a data stream to the total number of unit intervals (e.g., number of recovered bits) of the data stream in a given period of time. For some example applications, for random or pseudo-random data, the DTD of a high-speed digital data stream tends to 0.5, and tends to 0 or 1 in the presence of ill-conditioned patterns. Thus, DTD can be compared to one or more thresholds to detect the presence of ill-conditioned patterns. Once detected, data transition tracking circuitry can output or provide a gating signal (referred to herein as G TRIG ) to gate adaptation of the distortion compensation circuitry.

[0047] Using one or more example implementations of the present description can have one or more advantages or benefits. An example advantage is the ability to adapt the gating distortion compensation circuitry to prevent it from failing or being unreliable in the presence of a sick mode. For the retimer circuit, the gating can include resetting the CDR before CDR lock in the presence of a sick mode to prevent the synchronization process of the equalization scan and to prevent CDR lock from locking to an error, which can prevent data recovery. Another example advantage is that at least some of the circuitry for data transition tracking is simpler than the circuitry used to overdesign the receiver. Another example advantage is to prevent the loss of preferred adaptive equalization settings in the presence of a sick mode. In the context of the retimer circuit, yet another example advantage is the ability to detect a sick mode even before data can be reliably recovered, e.g., even before CDR lock. This is because the data transition tracking circuitry can be designed such that a repeating pattern with a long CID sequence is detectable even before a re-timing CTRL IN is generated.

[0048] Referring again to Figure 1 and 2 , the distortion compensation circuitry 112 further includes a switch 220 and a switch 234. The switch 220 is coupled between the EQ adaptation control circuitry 204 and the equalizer 116. The switch 234 is coupled between the VCO 216 and the low pass filter 214. When operating the distortion compensation circuitry 112 in the presence of random or pseudo-random data, the switches 220 and 234 are closed. However, in the presence of a detected sick mode, the distortion compensation circuitry 112 receives a G TRIG from the data transition tracking circuitry 124. The G

[0049] Upon receiving the G TRIG , the switch 220 is opened, thereby gating the EQ adaptation control circuitry 204. This effectively freezes or maintains the equalizer settings until the sick mode is no longer detected, where the switch 220 is closed, thereby re-enabling the EQ adaptation control circuitry 204. Upon receiving the G TRIG , the switch 234 is also opened, thereby gating the phase and frequency tracking capability of the PLL 118. This keeps the frequency of the VCO 216 constant until the sick mode is no longer detected, where the switch 234 is closed, thereby allowing phase and frequency tracking and associated adaptation of the phase and frequency of the VCO 216. Other gating can be performed using the G TRIG . In another example, in addition to or instead of opening the switch 234, a lock detection circuitry (not shown) that detects CDR lock is gated.

[0050] Figure 3 depicts Figure 1part 300 of the signal conditioning circuitry 106 that includes the example data conversion tracking circuitry 124. More specifically, the circuit 300 further includes data cell extraction circuitry 120 and data cell delay circuitry 122. The data conversion includes the data cell extraction circuitry 120, the data cell delay circuitry 122, and the data conversion tracking circuitry 124. The data conversion tracking circuitry 124 includes logic circuitry 302, a low pass filter 304, and a comparator circuitry 306 coupled as illustrated.

[0051] The data cell extraction circuitry 120 extracts and outputs a sequence of data cells (e.g., data bits) from a signal received to the signal conditioning circuitry. The signal can be the CHAN OUT from the channel 104, or can be the output EQ OUT of the equalizer. However, in the following description, we will refer to the signal to the data cell extraction circuitry 120 as EQ OUT . The data cell extraction circuitry 120 provides the data cells as CTRL IN . CTRL IN may be the output of a decision circuit within a re-timer or re-driver circuit, and is the digital equivalent of RX IN . In a re-timer implementation, the data cell extraction circuitry 120 also receives a clock signal from a clock generator 330. For example, the clock generator 330 is a phase-aligned clock signal output from a CDR, e.g., the clock signal 208 from the CDR 118.

[0052] In one example implementation, e.g., when a re-timer is used, the data cell extraction circuitry 120 includes a sampler that receives EQ OUT and a clock signal, samples EQ OUT at each clock edge, and outputs the resulting bit as a data cell. The sampler can be implemented using a buffer amplifier, an operational amplifier (op amp), a switch (e.g., a field effect transistor) coupled between the output of the buffer amplifier and the input of the op amp, and a capacitor coupled to the input of the op amp. The sampler receives EQ OUT into the buffer amplifier, the switch can open and close on the clock edge to sample and output a voltage corresponding to the charged state of the capacitor, which represents a 1 or 0 sample bit from EQ OUT .

[0053] In another example implementation, e.g., when a re-driver is used, the data cell extraction circuitry 120 includes a slicer that receives EQ OUT and outputs the resulting bit as a data cell. The slicer can be implemented using a buffer amplifier, an operational amplifier (op amp), a switch (e.g., a field effect transistor) coupled between the output of the buffer amplifier and the input of the op amp, and a capacitor coupled to the input of the op amp. The slicer receives EQ OUTThe slicer is implemented with an analog comparator that compares the data unit to a threshold. If EQ OUT the threshold, the comparator output goes high, indicating a 1. If RX IN EQ OUT is below the threshold, the comparator output goes low, indicating a 0.

[0054] The data unit delay circuitry 122 receives a data unit and generates one or more previous data units. In a digital circuit instance, the data unit delay circuitry 122 includes a deserializer that generates multiple parallel bits and previous bits. In an analog or hybrid analog / digital instance, the data unit delay circuitry 122 includes flip-flops, delay lines, or some other analog delay circuitry that delays a current data unit (e.g., a bit) by one unit interval period.

[0055] The logic circuitry 302 (e.g., one or more XOR gates) receives one or more data units from the data unit sequence and compares them to one or more previous data units, and generates a logic output signal (e.g., LOGIC OUT ) based on the comparison. The low-pass filter 304 provides a time-averaged DTD measurement of the data unit sequence based on the logic output signal. The comparator circuitry 306 compares the DTD measurement to at least one threshold (e.g., TH1), and based on the comparison, indicates whether a disruptive (pathological) pattern is present in the data unit sequence. The indication is shown as a signal G TRIG .

[0056] In one instance, such as when a rectifier is used, the comparator circuitry 306 compares the DTD measurement to a single threshold TH1, which is also referred to herein as an upper threshold. When the DTD measurement exceeds the threshold, a pathological pattern is indicated by G TRIG . In another instance, the comparator circuitry 306 compares the DTD measurement to a threshold TH1 and a threshold TH2, which are also referred to herein as lower thresholds. When the DTD measurement is outside either threshold, such as above the threshold TH1 or below the threshold TH2, a pathological pattern is indicated by G TRIG .

[0057] In an instance, the low-pass filter 304 has a sufficiently low cutoff frequency such that G TRIG does not indicate a pathological pattern during a transient shift in the data, such as a short burst of CIDs. Also, the time constant of the data transition tracking circuitry 124 is less than the time constant of the low-pass filter 304, so that G TRIGother control logic (e.g., for adaptive equalizer 116) of the gated DTD measurements. This enables data transition tracking circuitry 124 to react faster than other adaptive circuitry to suspend or reset adaptive circuitry before the ill-conditioned mode can cause adaptive distortion. In a particular example, the time constant of low-pass filter 304 is about one order of magnitude smaller than the time constant of the adaptive control circuitry using G TRIG The time constant of the gated adaptive control circuitry is about one order of magnitude smaller. Thus, the reaction speed of transition tracking circuitry 124 will be 10 times faster than other adaptive circuitry in the system.

[0058] Figure 4 、 8 and 10 to 12 depict signal conditioning circuitry including different examples of data transition tracking circuitry according to the present description. In particular, Figure 4 Example signal conditioning circuitry 400 having an example digital implementation of data transition tracking circuitry is depicted. That is, circuitry 400 includes a sampler or slicer 420 as data unit extraction circuitry, a deserializer 422 as data unit delay circuitry, and data transition tracking circuitry 424, coupled as described.

[0059] In one example implementation, circuitry 400 is used as distortion compensation circuitry with a retimer circuit, where block 420 is a sampler receiving both the equalized signal EQ OUT 456 and a phase-aligned clock signal 432 from a clock generator 430 for producing a data unit sequence 434 (in this case a bit sequence). For example, clock generator 430 is a local VCO within a CDR of the retimer circuit. Sampler 420 can be implemented as described above with reference to block 120 of Figure 3 In another example implementation, circuitry 400 is used as distortion compensation circuitry with a re-driver circuit, where block 420 is a slicer receiving only the EQ OUT signal 456 for producing bit sequence 434. Slicer 420 can be implemented as described above with reference to block 120 of Figure 3 In both the retimer and re-driver implementations, the remaining circuitry 422 and 424 is the same. Thus, only one implementation (in this case the retimer circuit implementation) is described with reference to Figure 4 and associated Figures 5 to 7 .

[0060] In a particular example, the EQ OUTThe signal is provided at approximately 10 Gb / s. Therefore, every 100 picoseconds (e.g., one unit interval (UI) or one cycle of 10 Gb data), sampler 420 samples the data center on the rising edge of clock signal 432 to output new data bits. This high-speed serial data stream 434 is provided to deserializer 422. Deserializer 422 parallelizes the serial data stream 434 into multiple (n) slower data streams 436, which are processed in the digital domain by data conversion tracking circuitry system 424. In other instances, the data rate may be different, for example from 270 Mb / s to 12 Gb / s, or even higher data rates, such as 50 Gb / s, 100 Gb / s, or higher.

[0061] In an example implementation, deserializer 122 includes multiple shift registers configured for serial input parallel output (SIPO). In example applications, such as digital video, n = 64. However, n can be other values, such as 32. Therefore, deserializer 422 receives 64 sequential bits (1, 2, 3, ... n) from serial data stream 434 and outputs them to 64 corresponding (separate) lines. A high-speed sampling clock signal 432 is also fed to deserializer 422, which is divided (e.g., segmented) by n, and the n parallel output bits 436 are timed to n. Therefore, the speed of each of the 64 lines with n parallel bits 436 provided to the data conversion tracking circuitry system 424 is one-sixty-fourth of the serial data stream 434.

[0062] The data conversion tracking circuit system 424 includes a digital logic circuit system with an XOR group 402 having multiple XOR gates (one of which is labeled 406) coupled as shown, a low-pass filter 404, and a comparator circuit system 406. The low-pass filter 404 includes a summer 408 with inputs coupled to the output of the XOR group 402, and an integrator and dump circuit 460 coupled to the output of the summer 408. The low-pass filter 404 may also include a right shifter 418 coupled to the output of the integrator and dump circuit 460. The integrator and dump circuit 460 includes an adder 410 and a z-axis... -1 The accumulator of register 412, where z -1 Indicator register 412 is delayed by one clock cycle. The inputs of adder 410 are coupled to the outputs of summer 408 and register 412 (forming a feedback loop). The output of adder 410 is coupled to the input of register 412. Integrator and dump circuit 460 also includes switch 416, one terminal of which is coupled to the output of register 412, and the other terminal is coupled to the input of right shifter 418 (if used in the circuit) or the input of comparator circuit system 406.

[0063] The comparator circuitry 406 includes two digital comparators 454 and 426 and an AND gate 428. One input of comparator 454 and one input of comparator 426 are coupled to the terminal of switch 416 or the output of right shifter 418. The other input of comparator 454 is coupled to receive an upper threshold value TH1. The other input of comparator 426 is coupled to receive a lower threshold value TH2. The threshold values TH1 and TH2 can be programmed into registers or some other memory device (not shown) coupled to comparators 454 and 426. The outputs of comparators 454 and 426 are coupled to inputs of AND gate 428, and G TRIG signal 452.

[0064] The n parallel bits 436 are input to a plurality (e.g., 63) of XOR gates 406, where each bit is XORed with the previous bit. Thus, for the 64 signals 436 in, we have (n-1) 63 signals 438 out of the XOR group 402. The summer 408 combines (e.g., adds) the 63 signals 438 into a single signal 440 of integer values, each signal 440 having log2(n) bits, or in this example, 6 bits. In this example, the minimum value of the single signal 440 can be 0, and the maximum value can be 63. The integer values of signal 440 are updated at each deserializer clock edge at a rate of 1 / 64 of the original data rate.

[0065] The signal 440 is provided to an integration and dump circuit 460, which provides a time-averaged DTD signal or measurement 446. If used, the right shifter 418 truncates the least significant bits (LSBs) to remove noise from the signal 446. That is, the sum of the signal 440 from the output of summer 408 and the signal 442 from the register output are accumulated in register 412 until a clear and dump clock edge or pulse 444 is provided to register 412 and switch 416. The pulse 444 closes the switch 416, causing the accumulated sum 442 to be output from the integration and dump circuit 460 as the DTD measurement 446, and clears the register 412. Then, the switch 416 is again opened to restart the accumulator until another clock edge or pulse 444 is provided. In this example, the switch 416 is used. However, in an alternative example, the switch 416 is not present, and the low pass filter 404 is designed to monitor the slope or rate of change of the signal 440.

[0066] Comparator 454 compares DTD measurement 446 to TH1 and asserts, e.g., provides a high signal 450 (1) when signal 446 is less than TH1. Otherwise, comparator 454 is de-asserted, providing a low signal 450 (0). Comparator 426 compares DTD measurement 446 to TH2 and asserts, e.g., provides a high signal 448 (1) when signal 446 is greater than TH2. Otherwise, comparator 426 is de-asserted, providing a low signal 448 (0).

[0067] When both signals 450 and 448 are high, AND gate 428 asserts, e.g., provides a high G TRIG signal 452 (1) indicating "good" data, meaning a type of data that allows correct operation of the distortion compensation circuitry adaptation. Thus, a high G TRIG signal 452 signals the distortion compensation circuitry to continue operating in a continuous adaptation manner. In one example, good data is data that is sufficiently randomized. Conversely, when one or both of signals 450 and 448 are low, AND gate 428 is de-asserted, providing a low G TRIG signal 452 (0). A low G TRIG signal 452 indicates a pathological pattern and thus allows gating of the distortion compensation circuitry adaptation.

[0068] TH1 and TH2 are application-specific and implementation-specific. In one example, TH1 and TH2 are designed based on the value of n and the design of integration and dump circuit 460. That is, register 412 accumulates signal 440 for a number of cycles of the clock signal divided by n, and its output signal 446 can represent a multi-bit number. The size of the accumulator depth (total number of bits) and the frequency of the read and clear clock or pulse determine the level of averaging provided by integration and dump circuit 460. Thus, thresholds TH1 and TH2 can be determined by the amount of averaging performed by integration and dump circuit 460, the frequency at which the DTD 446 measurement is provided, and the number of output signals 438 from XOR group 402.

[0069] In an example where n is 64, when data 434 is random or pseudo-random, output signal 438 from summer 408 is expected to be in the middle of the extremes, e.g., approximately 31.5, which is in the middle of 0 and 63. If data 434 contains a pathological pattern, then output signal 438 from summer 408 is skewed towards the maximum (63) or minimum (0) for a period of time long enough that the time-averaged DTD measurement signal 446 triggers AND gate 428 to de-assert and indicate the presence of a pathological pattern. In an example where n = 64, thresholds TH1 and TH2 can be set to 400 and 275, respectively, to de-assert AND gate 428 when DTD measurement 446 exceeds the thresholds.

[0070] Figure 5 Depiction Figure 4 The timing diagram of the operation of the signal conditioning circuitry 400 shown in FIG. 4B without the right shifter 418. In particular, the waveforms 440, 442, 444, 446, 448, 450, and 452 of the three time periods 500, 502, and 504 represent Figure 4 The corresponding signals shown in FIG. 4B having the same element designations. The signal 440, depicted as a series of lowercase letters representing a series of integer values, is provided to the integrate-and-hold circuit 406 by the summer 408. As a result of the feedback, the accumulated sum 442 is depicted as a series of uppercase letters representing a series of integer values.

[0071] At the start of the timing diagram, it is assumed that the register 412 has just been cleared, as indicated by the 0 at the start of the waveform 442 and the absence of a value in the waveform 446. Throughout the time period 500, the clear-and-hold pulse 444 is not provided, and the waveforms 448, 450, and 452 are depicted as low (0). For the first subsequent clock edge (at time tl), the accumulated signal 442 has the value Z, which is the sum of the previous value 0 fed back with the current value z from the signal 440. As further illustrated, since z -1 One clock delay at the register 412, the accumulated signal 442 is delayed one clock edge from the value represented by the waveform 440.

[0072] For the next clock edge (at time t2), the accumulated signal 442 has the value Y, which is the sum of the previous value Z fed back with the current value y from the signal 440. For the next clock edge (at time t3), the accumulated signal 442 has the value X, which is the sum of the previous value Y fed back with the current value x from the signal 440. This accumulation continues until the clear-and-hold pulse 444 is provided to the integrate-and-hold circuit 460 during the time period 502 at time t5. The final accumulation before the pulse 444 occurs at time t4, where the accumulated signal 442 has the value S. S is the sum of the previous value T fed back with the current value s from the signal 440. In an alternative implementation, the clear-and-hold signal 444 is a clock rather than a pulse.

[0073] At the rising edge of the clear-and-hold pulse 444, the switch 416 closes and the value of the register 412, currently S, is provided as the DTD measurement value 446 from the integrate-and-hold circuit 460. Then, the switch 416 opens, and the register 412 is cleared, as indicated by the 0 in the waveform 442, so that accumulation begins again and continues (as shown) until the clear-and-hold pulse 444 is provided to the integrate-and-hold circuit 460 during the time period 504 at time t6.

[0074] The accumulated signal 442 just prior to the pulse 444 at time t6 has a value J. J is the sum of the previous value K fed back with the current value j from signal 440. At the rising edge of the clear and dump pulse 444, the switch 416 is closed and the value of register 412, now J, is provided as the DTD measurement value 446 from the integration and dump circuit 460. Then, the switch 416 is opened, the register 412 is cleared, as indicated by the 0 in the waveform 442 during time period 504, so that the accumulation starts again.

[0075] During time period 502, assume that the DTD value 446 of S provided to comparators 454 and 426 is greater than TH1 and greater than TH2. This causes the output signal 448 of comparator 426 to go high, while the output signal 450 of comparator 454 remains low. Thus, G TRIG signal 452 remains low, indicating a sick mode, which can be used for gate distortion compensation circuitry adaptation. However, during time period 504, assume that the DTD value 446 of J provided to comparators 454 and 426 is less than TH1 and greater than TH2. This causes the output signal 448 of comparator 426 to remain high, and the output signal 450 of comparator 454 to go from low to high. Thus, G TRIG signal 452 goes high, indicating good data, which signals the distortion compensation circuitry to resume operating in an adaptive manner.

[0076] Figure 6 and 7 depicting the signal conditioning circuitry 112 and 400 shown in common operation Figure 2 and 4 analog results for the signal conditioning circuitry 112 and 400 shown in common operation. Figure 6 A graph 600 is illustrated depicting a waveform 604 representing the control voltage of the VCO 216 plotted against time. Figure 6 A graph 602 is also illustrated depicting a waveform 446 representing the DTD measurement signal 446 plotted against time. The line superimposed on the waveform 446 illustrates the upper threshold value TH1 of 400 and the lower threshold value TH2 of 274. Figure 7 A graph 700 is illustrated depicting a waveform 706 representing the adaptation of the CTLE of the equalizer 116 plotted against time. Figure 7 Waveforms 702, 704, and 708 are also illustrated, which depict the adaptation produced for three tap coefficients of the DFE of the equalizer 116 plotted against time.

[0077] In the example simulation, and as illustrated by the waveform 604, the CDR 118 acquires lock on the equalized signal 202 at time t2 with an offset of 500 ppm. Prior to CDR lock, the CTLE (waveform 706) starts with a minimum boost, and increments by 3 after a timeout if the CDR 118 fails to lock. Prior to detecting CDR lock, if a CTLE timeout occurs, the VCO control voltage 604 is reset. The VCO control voltage 604 is also reset if the DTD measurement 446 transitions from indicating a pathological pattern to indicating random or pseudo-random data. For example, during the time frame between ti and t2, when the DTD measurement 446 transitions from being less than TH2 to being between TH1 and TH2, this reset is indicated. Thus, the DTD measurement 446 can indicate a pathological pattern prior to CDR lock. Also, the waveforms 702 through 708 illustrate that equalization adaptation is suspended prior to and after CDR lock, which occurs at time t2. When the DTD measurement 446 is outside of TH1 or TH2, the equalization that is suspended is depicted by the horizontal portions of the waveforms 702 through 708, for example, starting at times ti, t3, and t4.

[0078] Figure 8 An example signal conditioning circuit 800 is depicted that has an example simulation implementation of data transition tracking circuitry. That is, the circuit 800 includes a sampler 820 as data unit extraction circuitry, a 1-UI delay circuit 822 as data unit delay circuitry, and data transition tracking circuitry 824. In this example implementation, the circuit 800 is used as distortion compensation circuitry with a re-timer circuit, where the sampler 820 receives both an equalized signal EQ OUT containing data from a clock generator 830 for producing a sequence of data units (in this case, a sequence of bits). For example, the clock generator 830 is a local VCO within a CDR of the re-timer circuit. The sampler 820 can be implemented as described above with reference to the block 120 of FIG. 1. Figure 3

[0079] Thus, every 1-UI or every 1 -data period, the sampler 820 samples the center of the data on the rising edge of the clock signal to output a recovered data bit. This high-speed serial data stream is provided to the delay circuit 822 and the data transition tracking circuitry 824. The delay circuit 822 delays each bit in the serial data stream by 1-UI. The delay circuit 822 outputs the delayed data bit as a previous data unit to the data transition tracking circuitry 824. In one example, the delay circuit 822 is implemented using a D flip-flop.

[0080] ​Data transition tracking circuitry 824 includes analog circuitry of exclusive OR gate 802, low pass filter 804, and comparator circuitry 806. Low pass filter 804 can be implemented as an RC circuit with at least one resistor and one capacitor. Comparator circuitry 806 includes analog comparator 808, analog comparator 810, and OR gate 812 with inversion at the input corresponding to the TH2 comparator 810 output.

[0081] As illustrated, one input of exclusive OR gate 802 is coupled to the output of sampler 820. Another input of exclusive OR gate 802 is coupled to the output of delay circuitry 822. The output of exclusive OR gate 802 is coupled to an input of low pass filter 804. The output of low pass filter 804 is coupled to one input of comparator 808 and one input of comparator 810. Another input of comparator 808 is coupled to receive upper limit threshold TH1. Another input of comparator 810 is coupled to receive lower limit threshold TH2. Thresholds TH1 and TH2 can be programmed into registers or some other memory device (not shown) coupled to comparators 808 and 810. The outputs of comparators 808 and 810 are coupled to inputs of OR gate 812, and a G TRIG signal is provided at the output of OR gate 812.

[0082] Exclusive OR gate 802 exclusive ORs each bit with the previous bit and provides the resulting XOR OUT signal. Low pass filter 804 time averages the XOR OUT signal based on a time constant of low pass filter 804 to produce a DTD signal or measurement 814. Comparator 808 compares DTD measurement 814 to TH1 and asserts, for example, provides a high signal when signal 814 is less than TH1. Otherwise, comparator 808 is de-asserted, providing a low signal. Comparator 810 compares DTD measurement 814 to TH2 and asserts, for example, provides a high signal when signal 814 is greater than TH2. Otherwise, comparator 810 is de-asserted, providing a low signal that is inverted. When the signals from both comparators 808 and 810 are high, OR gate 812 is de-asserted, for example, provides a low G TRIG signal indicating good data to distortion compensation circuitry. Otherwise, OR gate 812 is asserted, providing a high G TRIG signal indicating a sick mode to gate distortion compensation circuitry. In this example, the polarity of G Figure 4 is reversed relative to the example given in TRIG

[0083] Figure 9 depicts common operation Figure 2 and 8 ​Analog results for the signal conditioning circuitry 112 and 800 shown in the middle. The plot 800 showing a waveform 814 depicting a DTD measurement signal 814 plotted versus time is shown. In this particular example, the lines superimposed on the waveform 814 illustrate an upper threshold TH1 of 50 mV and a lower threshold TH2 of -50 mV. However, TH1 and TH2 can be programmed for a particular application and sick mode. Further, in this example, a sick mode is detected when the DTD measurement 814 falls to approximately -75 mV. However, good data is detected when the DTD measurement 814 has an average value of approximately 0 V.

[0084] Figure 10 An example signal conditioning circuitry 1000 depicting another example analog implementation with data transition tracking circuitry. That is, the circuit 1000 includes a slicer 1020 as data unit extraction circuitry, a delay line 1022 as data unit delay circuitry, and the data transition tracking circuitry 824 (as described above with reference to Figure 8 In this example implementation, the circuitry 1000 is used as distortion compensation circuitry with a re-driver circuit, where the slicer 1020 receives an equalized signal EQ OUT containing data and outputs a "recovered" data bit. This high speed serial data stream is provided to the delay line 1022 and the data transition tracking circuitry 824. The delay line 1022 delays each bit in the serial data stream by 1 UI. The delay line 1022 outputs the delayed data bit as a previous data unit to the data transition tracking circuitry 824. The data transition tracking circuitry 824 processes the data stream and the delayed data stream as described above with reference to Figure 3

[0085] The slicer 1020 amplifies and clips the EQ OUT to output a "recovered" data bit. This high speed serial data stream is provided to the delay line 1022 and the data transition tracking circuitry 824. The delay line 1022 delays each bit in the serial data stream by 1 UI. The delay line 1022 outputs the delayed data bit as a previous data unit to the data transition tracking circuitry 824. The data transition tracking circuitry 824 processes the data stream and the delayed data stream as described above with reference to Figure 8 TRIG signal indicating good data or a sick mode to the distortion compensation circuitry. In this example, the polarity of the G Figure 4 signal given in the example above is reversed. TRIG

[0086] Figure 11 ​​​An example signal conditioning circuit 1100 is depicted that has another example analog implementation of data transition tracking circuitry. That is, the circuitry 1100 includes a sampler 1120 as data unit extraction circuitry, a 1 -UI delay circuit 1122 as data unit delay circuitry, and data transition tracking circuitry 1124. In this example implementation, the circuitry 1100 functions as distortion compensation circuitry with a re-timer circuit, where the sampler 1120 receives an equalized signal EQ OUT containing data and a phase-aligned clock signal from a clock generator 1130 for generating a sequence of data units (in this case, a sequence of bits). For example, the clock generator 1130 is a local VCO within a CDR of the re-timer circuit. The sampler 1120 can be implemented as described above with reference to the block 120. Figure 3

[0087] Thus, every 1 UI or every 1 data period, the sampler 1120 samples the center of the data on the rising edge of the phase-aligned clock signal to output a new data bit. This high-speed serial data stream is provided to the delay circuitry 1122 and the data transition tracking circuitry 1124. The delay circuitry 1122 delays every bit in the serial data stream by 1 UI. The delay circuitry 1122 outputs the delayed data bit as a previous data unit to the data transition tracking circuitry 1124. In one example, the delay circuitry 1122 is implemented using a D flip-flop.

[0088] The data transition tracking circuitry 1124 includes analog circuitry of an XOR gate 1102, a low-pass filter 1104, and comparator circuitry 1106. The low-pass filter 1104 can be implemented as an RC circuit having at least one resistor and one capacitor. The comparator circuitry 1106 includes a full-wave (FW) rectifier 1108 and an analog comparator 1110.

[0089] As illustrated, one input of the XOR gate 1102 is coupled to the output of the sampler 1120. Another input of the XOR gate 1102 is coupled to the output of the delay circuitry 1122. The output of the XOR gate 1102 is coupled to an input of the low-pass filter 1104. The output of the low-pass filter 1104 is coupled to an input of the low FW rectifier 1108. The output of the FW rectifier 1108 is coupled to one input of the comparator 1110. Another input of the comparator 1110 is coupled to receive an upper threshold value TH1. The threshold value TH1 can be programmed into a register or some other memory device (not shown) coupled to the comparator 1110. A G TRIG signal is provided at the output of the comparator 1110.

[0090] The XOR gate 1102 XORs every bit with the previous bit and provides the resulting XOR​OUT Signal. Low-pass filter 1104 based on the time constant of low-pass filter 1104 for XOR. OUT The signal is time-averaged to generate a time-averaged signal. FW rectifier 1108 rectifies any negative voltage in the time-averaged signal to a positive voltage to generate the DTD measurement. Comparator 1110 compares the DTD measurement with TH1, and asserts, for example, that a high G is provided when the DTD measurement is greater than TH1. TRIG Signal. Otherwise, comparator 1110 is deasserted, thus providing low G. TRIG Signal. Low G TRIG The signal indicates good data to the distortion compensation circuit system. High G TRIG The signal indicates the ill-conditioned mode to gating the distortion compensation circuitry system for adaptation. In this example, relative to... Figure 4 The examples given in the text make G TRIG The polarity reversal.

[0091] Figure 12 An example signal conditioning circuit system 1200 with a data conversion tracking circuit system is described as an example of a mixed analog and digital implementation. Specifically, the circuit system 1200 includes a sampler 1220 as a data unit extraction circuit system, a UI delay circuit system 1222 as a data unit delay circuit system, and a data conversion tracking circuit system 1224. In this example implementation, the circuit system 1200, together with a retimer circuit, serves as a distortion compensation circuit system, wherein the sampler 1220 receives an equalization signal EQ containing data. OUT Both the phase-aligned clock signal from clock generator 1230 and the clock signal from clock generator 1230 are used to generate a sequence of data cells (in this case, a bit sequence). For example, clock generator 1230 is a local VCO within the CDR of a retimer circuit. Sampler 1220 can be referenced as above. Figure 3 Implemented as described in block 120.

[0092] Therefore, every UI or every data cycle, sampler 1220 samples the data center on the rising edge of the phase-aligned clock signal to output a new data bit. This high-speed serial data stream is provided to delay circuit system 1222 and data conversion tracking circuit system 1224. Delay circuit system 1222 delays each bit in the serial data stream by 1 UI. Delay circuit system 1222 outputs the delayed data bit as the previous data unit to data conversion tracking circuit system 1224. In one example, delay circuit system 1222 is implemented using D flip-flops.

[0093] Data conversion tracking circuitry 1224 includes XOR gate 1202 and analog circuitry of low pass filter 1204 and digital comparator circuitry 1206. Low pass filter 1204 is implemented as a high speed counter that provides an interface between the high speed analog domain and the low speed digital domain. Comparator circuitry 1206 includes two digital comparators 1208 and 1210 and AND gate 1212.

[0094] As illustrated, one input of XOR gate 1202 is coupled to the output of sampler 1220. Another input of XOR gate 1202 is coupled to the output of delay circuitry 1222. The output of XOR gate 1202 is coupled to an input of counter 1204. The output of counter 1204 is coupled to one input of comparator 1208 and one input of comparator 1210. Another input of comparator 1208 is coupled to receive upper threshold value TH1. Another input of comparator 1210 is coupled to receive lower threshold value TH2. Threshold values TH1 and TH2 can be programmed into registers or some other memory device (not shown) coupled to comparators 1208 and 1210. The outputs of comparators 1208 and 1210 are coupled to inputs of AND gate 1212, and a G TRIG signal is provided at the output of AND gate 1212.

[0095] XOR gate 1202 XORs each bit with the previous bit and provides the resulting XOR OUT signal. Counter 1204 time averages the XOR OUT signal based on a time constant of counter 1204 to produce a DTD signal or measurement. That is, the XOR OUT signal is accumulated in counter 1204 until a read and clear signal is provided to counter 1204. The read and clear signal causes the current accumulation to be output from counter 1204 as a DTD measurement 446 and clears counter 1204.

[0096] Comparator 1208 compares the DTD measurement to TH1 and asserts, for example, provides a high signal (1) when the DTD measurement is less than TH1. Otherwise, comparator 1208 is de-asserted, providing a low signal (0). Comparator 1210 compares the DTD measurement to TH2 and asserts, for example, provides a high signal (1) when the DTD measurement is greater than TH2. Otherwise, comparator 1210 is de-asserted, providing a low signal (0).

[0097] When the output signals of both comparators are high, AND gate 1212 asserts, for example, provides a high G TRIG signal (1) indicating "good" data, meaning a type of data that allows correct operation of the distortion compensation circuitry to adapt. Thus, a high G TRIGThe signals are sent to the distortion compensation circuitry to continue operating in an adaptive manner. Conversely, when one or both of the output signals from the comparators are low, the AND gate 1212 is de-asserted, providing a low G TRIG signal (0). The low G TRIG signal indicates a sick mode, and thus allows gating of the distortion compensation circuitry. TH1 and TH2 are application-specific and implementation-specific. In one example, TH1 and TH2 are determined by the amount of averaging performed by the counter 1204.

[0098] Figure 13 A flowchart depicting an example method 1300 of operating signal conditioning circuitry that includes data transition tracking circuitry is shown. For example, the method 1300 can be implemented in the circuitry (or portions thereof) shown in one or more of FIGS. 8 and 10-12. Figures 1 to 4

[0099] According to the method 1300, at blocks 1302 and 1304, the circuitry (e.g., distortion compensation circuitry) receives a signal and extracts a sequence of data units from the signal. For example, data unit extraction circuitry receives an equalized signal EQ OUT and extracts data units using samplers in a re-timer implementation or slicers in a re-driver implementation. The data units can be provided as CTRL IN to data unit delay circuitry and data transition tracking circuitry.

[0100] At block 1306, the data unit delay circuitry generates previous data units. In one example, a flip-flop or delay line generates a single delayed data stream. In another example, a deserializer generates multiple parallel data streams.

[0101] At block 1308, logic circuitry compares one or more data units to one or more previous data units and provides one or more logic outputs. In one example, a single XOR gate compares a data unit to previous data units from a data stream and a single delayed data stream to generate a single XOR output. In another example, an XOR bank having multiple XOR gates compares a data unit to previous data units from parallel data streams and outputs multiple XOR outputs.

[0102] At block 1310, a low-pass filter generates a time-averaged signal (DTD measure) based on the one or more logic output signals. In one example, the low-pass filter is an analog circuit, such as an RC circuit or a counter, that receives a single XOR output and provides the time-averaged signal. In another example, the low-pass filter is a digital circuit including a summer and an integration and dump circuit that receives multiple XOR outputs and provides the time-averaged signal.

[0103] ​At block 1312, the comparator circuitry compares the time-averaged signal to a single threshold, where the comparator circuitry includes a FW rectifier, and based on the comparison, indicates a disruptive pattern in the sequence of data units. For example, the indication is G TRIG signal. In another example, the comparator circuitry compares the time-averaged signal to two thresholds to produce G TRIG . The comparator circuitry can be digital or analog circuitry.

[0104] At block 1314, in response to the indication of a disruptive pattern (e.g., G TRIG ), at least a portion of the gated distortion compensation circuitry is gated (e.g., the distortion compensation circuitry is adapted). For example, EQ adaptation control is suspended, phase-frequency adaptation in the CDR circuit is suspended, and / or the CDR circuit is reset.

[0105] The foregoing examples illustrate several possible embodiments of various aspects of the present disclosure, where equivalent changes and / or modifications made by others skilled in the art will occur in light of the description and accompanying drawings. In the described embodiments, modifications are possible and other embodiments are possible within the scope of the claims.

Claims

1. A signal conditioning circuitry comprising: logic circuitry configured to compare a data unit from a sequence of data units with a previous data unit and provide a logic output signal; a low pass filter coupled to the logic circuitry, wherein the low pass filter is configured to provide a data transition density measure of the sequence of data units based on the logic output signal; comparator circuitry coupled to the low pass filter, wherein the comparator circuitry is configured to compare the data transition density measure to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units; and distortion compensation circuitry coupled to the comparator circuitry, the distortion compensation circuitry configured to gate an adaptive operation in response to the indication of the disruptive pattern.

2. The signal conditioning circuitry of claim 1, further comprising: a sampler; and a deserializer coupled to the sampler; and wherein the logic circuitry includes a plurality of exclusive OR gates coupled between the deserializer and the low pass filter.

3. The signal conditioning circuitry of claim 1, wherein the logic circuitry consists of a single exclusive OR gate having first and second inputs.

4. The signal conditioning circuitry of claim 3, further comprising: a sampler coupled to the first input; and delay circuitry coupled between the sampler and the second input.

5. The signal conditioning circuitry of claim 3, further comprising: a slicer coupled to the first input; and a delay line coupled between the slicer and the input.

6. The signal conditioning circuitry of claim 1, wherein the low pass filter includes: a summer circuit coupled to the logic circuitry; and an accumulator coupled to the summer circuit.

7. The signal conditioning circuitry of claim 6, wherein the low pass filter further includes: a switch coupling the accumulator to the comparator circuitry.

8. The signal conditioning circuitry of claim 1, wherein the distortion compensation circuitry includes an equalizer.

9. The signal conditioning circuitry of claim 1, wherein the distortion compensation circuitry includes a clock and data recovery circuit.

10. A signal conditioning circuitry comprising: a data transition tracking circuitry including: an exclusive OR gate; a low pass filter coupled to the exclusive OR gate; and comparator circuitry coupled to the low pass filter, wherein the comparator circuitry is configured to compare a data transition density measure to a threshold and, based on the comparison, indicate a disruptive pattern in a sequence of data units; and an equalizer coupled to the comparator circuitry, wherein the equalizer is configured to gate an adaptive operation in response to the indication. ​ 11. The signal conditioning circuitry of claim 10, further comprising a clock and data recovery circuit coupled to the comparator circuitry, wherein the clock and data recovery circuit is configured to gate operation in response to the indication.

12. The signal conditioning circuitry of claim 11, wherein the clock and data recovery circuit is configured to gate adaptive operation in response to the indication.

13. The signal conditioning circuitry of claim 10, further comprising a clock and data recovery circuit coupled to the comparator circuitry, wherein the clock and data recovery circuit is configured to reset operation in response to the indication.

14. The signal conditioning circuitry of claim 10, further comprising: a sampler; and a deserializer coupled between the sampler and the exclusive OR gate; and wherein the data conversion circuitry further includes an additional exclusive OR gate coupled between the deserializer and the low pass filter; and wherein the low pass filter includes: a summer circuit coupled to the first and second exclusive OR gates; an accumulator coupled to the summer circuit, and a switch coupling the accumulator to the comparator circuitry.

15. The signal conditioning circuitry of claim 10, the exclusive OR gate having first and second inputs, the signal conditioning circuitry further comprising: a sampler coupled to the first input; and delay circuitry coupled between the sampler and the second input.

16. The signal conditioning circuitry of claim 10, the exclusive OR gate having first and second inputs, the signal conditioning circuitry further comprising: a slicer coupled to the first input; and a delay line coupled between the slicer and the second input.

17. The signal conditioning circuitry of claim 10, wherein the comparator circuitry includes: a first comparator coupled to the low pass filter; a second comparator coupled to the low pass filter; and a logic gate coupled to the first and second comparators.

18. The signal conditioning circuitry of claim 17, wherein the first and second comparators are digital comparators and the low pass filter includes a counter.

19. The signal conditioning circuitry of claim 10, wherein the comparator circuitry includes: a comparator; and a rectifier circuit coupled between the low pass filter and the comparator.

20. A receiver including the signal conditioning circuitry of claim 10.

21. A method for signal conditioning, comprising: comparing a data unit from a sequence of data units with a previous data unit and providing a logic output signal; generating a time average signal based on the logic output signal; comparing the time average signal to a threshold and, based on the comparison to the threshold, indicating a disruptive pattern in the sequence of data units; and gating distortion compensation circuitry adaptation in response to the indication of the disruptive pattern. ​

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