Data processing method, computing device and related products

Abstract

The present disclosure discloses a data processing method, a computing device, a computer-readable storage medium, and a computer program product. The computing device that executes the data processing method may be included in a combined processing device, and the combined processing device may also include an interface device and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operations specified by the user. The combined processing device may also include a storage device, which is respectively connected to the computing device and the other processing devices, and is used to store data of the computing device and the other processing devices. The solution disclosed in the present disclosure can call a suitable computing library operator to convert the tensor data into a memory continuity state by reversely inferring the view class operator that causes the tensor data to become a memory discontinuous state, thereby reducing the data handling in the device-side memory and improving the processing efficiency of the machine.

Description

Technical Field

[0001] The present disclosure generally relates to the field of intelligent computing. More specifically, the present disclosure relates to a data processing method, a computing device, a computer-readable storage medium, and a computer program product. Background Art

[0002] In intelligent computing systems, programming frameworks provide programmers with an interface for accessing hardware and systems, and are a crucial core component. On one hand, programming frameworks encapsulate common operations in algorithms into operators, such as convolution and pooling, for direct access by programmers. On the other hand, as the interface between hardware and software, programming frameworks encapsulate the hardware architecture, reducing the complexity and difficulty of writing or applying deep learning algorithms and improving their implementation efficiency.

[0003] TensorFlow, PyTorch, and other popular deep learning frameworks are often used. In these frameworks, computational graphs are often used to describe the computational process of machine learning algorithms. Tensors are used to represent all data in the computational graph, and operators are used to represent various operations. A class of operators, such as transpose, slice, and split, only alter the appearance of tensor data without changing its actual arrangement in memory. In other words, they don't actually move data in memory. These operators are called view operators.

[0004] Due to this characteristic of view operators, tensor data is often discontinuous in memory, meaning the dimension order is inconsistent with the storage order. Reading operations on discontinuous data can lead to low memory access efficiency and high memory consumption in hardware devices. Furthermore, for some high-performance computing libraries, such as CNNL, the vast majority of operators require the input tensors to be continuous in memory. The current approach is to call specific operators to move and rearrange data one by one, making the tensors continuous in memory and thus passing them to the next operator in the computing library. This method of moving and rearranging data one by one is very time-consuming, resulting in poor overall performance. Summary of the Invention

[0005] In order to at least partially solve one or more technical problems mentioned in the background technology, the present disclosure provides a data processing solution, which can process tensor data in a discontinuous memory state, call the data handling operator of a suitable computing library to convert it into a continuous memory state, thereby improving data access efficiency and adapting to the needs of operators in high-performance computing libraries.

[0006] In a first aspect, the present disclosure discloses a data processing method, comprising: in response to a first tensor to be processed being in a memory non-continuous state, determining a view class operator that the first tensor undergoes to transition from a memory continuity state to the memory non-continuous state according to first description information of the first tensor; determining a data handling operator in a computing library that needs to be called according to the view class operator; determining parameters required to call the data handling operator to convert the first tensor from the memory non-continuous state to the memory continuity state according to the first description information; and calling the data handling operator according to the parameters to convert the first tensor into a memory continuity state.

[0007] In a second aspect, the present disclosure discloses a computing device comprising: a processor configured to execute program instructions; and a memory configured to store the program instructions, which, when loaded and executed by the processor, enables the processor to perform the data processing method according to the first aspect of the present disclosure.

[0008] In a third aspect, the present disclosure discloses a computer-readable storage medium having program instructions stored therein. When the program instructions are loaded and executed by a processor, the processor is caused to perform the data processing method according to the first aspect of the present disclosure.

[0009] In a fourth aspect, the present disclosure discloses a computer program product, comprising a computer program or instructions, which implement the data processing method of the first aspect of the present disclosure when executed by a processor.

[0010] Based on the data processing solution provided above, we can infer the view operators in the computational graph that caused the transition from a continuous state to a discontinuous state based on the description of the tensor data in the discontinuous state. Based on this information, we can select the appropriate high-performance computing library operators to perform data transfer processing. This data transfer processing can achieve continuous data transfer based on tensor data, thereby improving processing efficiency and overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an illustrative and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0012] Figure 1 The following example shows the different shapes of multidimensional arrays and their storage order in memory;

[0013] Figure 2 An exemplary flow chart of a data processing method according to an embodiment of the present disclosure is shown;

[0014] Figure 3 An exemplary flow chart of a data processing method according to an embodiment of the present disclosure is shown;

[0015] Figure 4 An exemplary flow chart of a data processing method according to another embodiment of the present disclosure is shown;

[0016] Figure 5 A block diagram illustrating a hardware configuration of a computing device that can implement various aspects of the disclosed embodiments;

[0017] Figure 6 A structural diagram showing a combined processing device according to an embodiment of the present disclosure; and

[0018] Figure 7 A schematic structural diagram of a board card according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of this disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this disclosure, not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this disclosure.

[0020] It should be understood that the terms "first," "second," "third," and "fourth," etc., which may appear in the claims, specification, and drawings of this disclosure, are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the specification and claims of this disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0021] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0022] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0023] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0024] In the programming framework of intelligent computing systems, data is typically modeled as tensors. A tensor can be thought of as an N-dimensional array, where the number of dimensions of the array is the rank of the tensor. Therefore, a 0-order tensor corresponds to scalar data; a 1-order tensor corresponds to a one-dimensional array, or vector; a 2-order tensor corresponds to a two-dimensional array, or matrix; and so on, with an N-order tensor corresponding to an N-dimensional array. For example, an RGB image can be represented as a 3-order tensor, while a dataset consisting of multiple RGB images can be represented as a 4-order tensor.

[0025] Each tensor has some common properties, including data type and shape. The shape of a tensor indicates the length of each order of the tensor. For example, a 0-order tensor corresponds to a scalar data and its shape is empty; a 1-order tensor corresponds to a one-dimensional vector and its shape contains one element, which is the length of the vector; a 2-order tensor corresponds to a matrix and its shape contains two elements, corresponding to the row and column lengths respectively; a 3-order tensor corresponds to a 3-dimensional data and its shape contains three elements, corresponding to the length of each order.

[0026] Although multidimensional arrays have multiple dimensions, because memory (for example, DRAM and RAM) is always laid out in one dimension, there is a correspondence between multidimensional arrays and the storage order in memory. Multidimensional arrays are typically allocated in contiguous memory space, meaning that multidimensional arrays can be expanded one-dimensionally and stored sequentially in memory.

[0027] Figure 1 The different shapes of multi-dimensional arrays and their storage order in memory are exemplified, wherein a one-dimensional array in a continuous memory is used to implement the storage of the multi-dimensional array.

[0028] Figure 1 Figure (a) shows the first data, namely the three-dimensional array X, which has three dimensions: dimension 0 (dim0), dimension 1 (dim1), and dimension 2 (dim2). The size of dimension 0 is 2, the size of dimension 1 is 2, and the size of dimension 2 is 3. Therefore, its shape (size) can be expressed as: X3 = (2, 2, 3).

[0029] Figure 1 Figure (c) shows the storage order of the three-dimensional array X in memory. Data with the same background in the figure are located in the same dimension. Assuming that the storage is done in a low-dimensional order (for example, from left to right in shape representation corresponds to high-dimensional to low-dimensional), the first data is expanded one-dimensionally to obtain:

[0030] X=[1,2,3,4,5,6,7,8,9,10,11,12].

[0031] More specifically, the data of the lowest dimension (the same row) is continuous, while the data of higher dimensions are spaced at different distances. For example, in the storage method shown in Figure (c), accessing the physical structure of adjacent elements on dimension dim2 requires an offset of 1 position (for example, from data 1 to data 2, data 5 to data 6, and so on); accessing the physical structure of adjacent elements on dimension dim1 requires an offset of 3 positions (for example, from data 1 to data 4, data 2 to data 5, ..., data 9 to data 12, and so on); and accessing the physical structure of adjacent elements on dimension dim0 requires an offset of 6 positions (for example, from data 1 to data 7, data 2 to data 8, ..., data 6 to data 12, and so on). This offset is called the stride. The stride of each dimension of the three-dimensional array X can be expressed as S X =(6,3,1).

[0032] In the programming framework of intelligent computing systems, there are view operators that operate on the external representation of tensors, such as transpose, slice, split, etc. Taking transpose as an example, it operates according to a certain dimension conversion rule perm N =(p1, p2, ..., p i ,…,p N ), get the data arrangement after dimension conversion, where p i The value of (i∈1,2,…,N) represents the original dimension of the array, p i In perm N The position in represents the target dimension of the transformation. For example, given the dimension transformation rule perm3 = (0,2,1), it means that dimension 1 and dimension 2 are to be swapped. That is, the original dimension 1 is to be converted to dimension 2 of the new array, and the original dimension 2 is to be converted to dimension 1 of the new array.

[0033] Figure 1 Figure (b) shows the transformed array Y obtained by applying the transpose operator to the three-dimensional array X shown in Figure (a). In this example, the aforementioned exemplary dimension transformation rule perm3 = (0, 2, 1) is applied. As can be seen from the figure, compared to array X, dimensions 1 and 2 of array Y are swapped. At this point, the dimensional information of the three-dimensional array Y can be expressed as: Y3 = (2, 3, 2).

[0034] However, since the view operator does not change the storage location of the data in memory, the storage order of the array Y obtained after the transposition operation in memory remains the same. Figure 1As shown in (c). At this time, according to the storage order in (c), the step size of each dimension of array Y becomes S Y =(6,1,3). As can be seen, if storing data sequentially with lower dimensions first is called memory continuity, then the current storage order of array Y is discontinuous. In other words, after the transpose operator changes the order of the array's dimensions but does not change its storage location in memory, the array's storage order in memory becomes discontinuous.

[0035] If you want the array Y to be continuous in memory, then according to the principle of low dimension first, its one-dimensional expansion should be Figure 1 As shown in Figure (d):

[0036] Y=[1,4,2,5,3,6,7,10,8,11,9,12].

[0037] In this article, when the one-dimensional expansion of tensor data in dimension order is consistent with the storage order of the data in the memory, the tensor data is said to be in a "memory continuity state", otherwise it is in a "memory discontinuity state". Figure 1 The example also shows that when the tensor data is in the "memory continuity state", its dimension strides are arranged in descending order. For example, the dimension stride S of the tensor X is X =(6,3,1) is arranged in descending order; and the dimension step size of tensor Y is S Y =(6,1,3) is non-descending order.

[0038] The shape of a tensor can help programmers develop an intuitive understanding of it. In programming frameworks like Pytorch, View operators can modify properties such as the shape (size), stride (the distance between the first index of adjacent dimensions), and storage offset (the offset of the first element of a tensor relative to the storage start), without changing the actual storage location of the tensor. In this case, the size, stride, and storage offset are used to calculate the memory location of the data on the device.

[0039] Assume that the size of the tensor is (s0,s1,s2,…,s i ), stride is (y0,y1,y2,…,y i ), storage_offset is b, then the tensor is at the point (x0,x1,x2,…,x i ) is calculated as follows:

[0040]

[0041] Where dptr is the starting position of the memory storage corresponding to the tensor, that is, storage_offset, and dtype is the data type of the tensor.

[0042] Combine from the front Figure 1 As can be seen from the description, after the tensors in the computation graph are processed by view operators, they produce discontinuous corresponding data, meaning that their state becomes memory-discontinuous. View operators do not copy or modify the data stored in the tensor; they simply redefine the correspondence between subscripts and data elements in the tensor. When accessing tensors in this memory-discontinuous state, traditional CPUs and GPUs must perform discontinuous data access according to the above formula. This leads to low hardware memory access efficiency and high memory consumption. When performing various operations on tensors using high-performance neural network computing libraries (such as CNNL), most operators require that the input tensors be in a memory-continuous state; otherwise, an error will occur. In this case, it is necessary to first call a specific operator (such as the cnnlStrideCopy operator) to move the data one by one into contiguous storage according to the above formula. After the tensor is in a memory-continuous state, it is passed to the next CNNL operator. Obviously, these methods are very time-consuming. When the data volume is large, moving the data one by one will be extremely time-consuming.

[0043] In view of this, considering that in the operation of computational graphs such as neural networks, the discontinuity of memory data is often caused by view-type operators, the present disclosure proposes a data processing solution to reversely deduce the view-type operators that cause tensor data to be in a discontinuous state in memory, thereby calling appropriate data transfer operators to perform continuous data transfer based on tensors and improve processing speed.

[0044] Regarding the terms "node" and "operator" mentioned in this disclosure, it should be noted that the term "operator" is from the perspective of computer computing (or from the perspective of software or algorithm); while the term "node" is a more figurative term (from the perspective of graphics or a more intuitive level). In terms of what they refer to, the terms "operator" and "node" actually refer to the same thing. That is, in this disclosure, the terms "operator" and "node" can be considered to have the same meaning and can be used interchangeably, but are described from different perspectives.

[0045] Figure 2 An exemplary flow chart of a data processing method according to an embodiment of the present disclosure is shown. In this processing method, by inferring the view operators experienced by tensor data in a non-continuous state in memory, an appropriate data transfer operator is selected from the computation library to perform continuous data transfer based on the tensor, thereby obtaining tensor data in a continuous state in memory.

[0046] As shown in the figure, in step 210, in response to the first tensor to be processed being in a memory non-continuous state, the view class operator that the first tensor undergoes when transitioning from a memory continuity state to a memory non-continuous state is determined according to the first description information of the first tensor.

[0047] In some embodiments, the is_contiguous function in the Pytorch framework can be used to determine whether the tensor data is continuous in memory. The tensor data can be determined by manual calculation. The tensor data can also be determined by other means. This application does not limit this. If the tensor data is continuous, no additional processing is required. If the tensor data is discontinuous, it can be reversed.

[0048] The description information of tensor data can include the three attributes mentioned above: shape (size), stride (stride), and storage offset (storage_offset). The shape represents a multi-dimensional view of the entire data element in the tensor data, while the stride and storage offset can determine the specific location of each data element in memory. View operators only change these attributes of the tensor data, so these attributes can be used to infer the view operators that the tensor data has experienced. Each view operator has different characteristics. Based on these characteristics, according to the changes in the attributes of the tensor data, it can be determined which view operator caused the change in the attributes of the tensor data.

[0049] Specifically, in some embodiments, the view type operator experienced by the first tensor can be determined based on the first data shape information (size) and the first dimension stride information (stride) in the first description information.

[0050] For example, reordering view operators such as transpose, permute, and view do not change the size of the tensor data; instead, they simply change the relative positions of the data elements within the viewport. Therefore, based on this characteristic, after applying a reordering view operator to tensor data, the data size indicated by its shape information remains unchanged, consistent with the memory size pointed to by the pre-processed tensor data. However, since the relative positions of data elements, such as the dimensional order, change, the dimensional stride information is no longer in descending order, as it would have been in a continuous state.

[0051] Based on this property change of tensor data, in some examples, it can be determined whether the view-type operator experienced by the first tensor is a rearrangement-type view-type operator by judging whether the following conditions are met, namely: the data scale indicated by the first data shape information of the first tensor is consistent with the memory size pointed to by the first tensor, and the first dimension step information indicates that the step sizes of each dimension are arranged in non-descending order.

[0052] For example, an extended view operator like expand increases the size of tensor data. However, since it does not copy the data stored in the tensor but instead repeatedly retrieves data from the same location, the dimension stride information of the tensor data that has undergone the expand operator will contain a dimension stride of 0. This means that when retrieving data in that dimension, the step length is 0. Therefore, based on this characteristic, we can construct a condition to determine whether tensor data has undergone an extended view operator.

[0053] Specifically, in some examples, whether the view operator applied to the first tensor is an extended view operator can be determined by determining whether the following conditions are met: the first dimension stride information of the first tensor contains a dimension stride of 0, and the data size obtained by adjusting the first data shape information based on the position index of 0 is consistent with the memory size pointed to by the first tensor. This determination process will be described later with reference to specific examples.

[0054] After determining the view type operator that the first tensor has passed through, then, in step 220, the data handling operator in the computing library that needs to be called is determined based on the determined view type operator.

[0055] High-performance computing libraries contain numerous operators for performing various functions, such as I / O and computation. Some data manipulation operators in the library can continuously manipulate data based on tensors, thereby improving processing efficiency. For example, the CNNL permute / transpose operators transpose tensor data; the CNNL expand operator expands tensor data; and so on. These operators perform the same functions as similar operators in programming frameworks, differing in that they modify the actual memory location of the data, i.e., they perform data manipulation within memory.

[0056] Therefore, by analyzing which view operators the tensor data may have undergone, we can select data handling operators with corresponding functions to achieve memory continuity processing of the data.

[0057] Specifically, in some embodiments, when the determined view type operator is a rearrangement type view type operator, the data handling operator to be called is determined to be a data rearrangement operator, such as a CNNL transpose operator.

[0058] Optionally or additionally, in other embodiments, when the determined view class operator is an extended view class operator, the data handling operator to be called is determined to be a data expansion operator, such as a CNNL expand operator.

[0059] Then, in step 230 , parameters required for calling a data transfer operator to convert the first tensor from a non-contiguous memory state to a continuous memory state are determined according to the first description information of the first tensor.

[0060] As mentioned earlier, most operators in the high-performance computing library require memory-contiguous input tensors, including the data handling operators mentioned above that perform continuous data handling based on tensors. Therefore, when calling these data handling operators, the corresponding parameters need to be determined. These parameters include: the second description information of the second tensor that serves as the input tensor of the data handling operator; and the operation parameter information of the data handling operator. It can be understood that the output tensor of the data handling operator is a tensor with the same shape as the first tensor being processed but in a memory-contiguous state.

[0061] The second tensor used as an input to a data manipulation operator must be memory-contiguous. Therefore, the first description of the current first tensor is used to derive the description of the current memory data when it is memory-contiguous, thereby deriving the second description of the second tensor. Based on the previously determined characteristics of the view operator that causes the first tensor to transition from a memory-contiguous state to a memory-discontiguous state, the description of the memory data corresponding to the first tensor when it was memory-contiguous can be inferred.

[0062] In one example, when the data handling operator is a data rearrangement operator (that is, it means that the view class operator is a rearrangement type view class operator), the second description information of the second tensor serving as the input tensor of the data handling operator can be determined in the following manner: first, the descending order of the first dimension step information in the first description information is determined as the second dimension step information in the second description information of the second tensor; then, according to the change rule of converting the first dimension step information into the descending order, the first data shape information in the first description information is converted to obtain the second data shape information in the second description information.

[0063] In another example, when the data handling operator is a data expansion operator (that is, the view class operator is an extended view class operator), the second description information of the second tensor serving as the input tensor of the data handling operator can be determined as follows: first, the position index corresponding to the value 0 is obtained from the first dimension step information in the first description information; then, based on the position index of the value 0, the corresponding position of the first data shape information in the first description information is set to 1 to determine the second data shape information in the second description information; and, based on the second data shape information and the memory continuity rule, the second dimension step information in the second description information is determined. The above parameter determination method will be described in detail later with reference to examples.

[0064] Once the input tensor (the second tensor) of the data handling operator is determined and the shape of the output tensor (i.e., the first data shape information of the first tensor) is known, the operation parameters of the data handling operator can be determined accordingly. The method for determining the corresponding operation parameters varies depending on the data handling operator.

[0065] In one example, when the data handling operator is a data reordering operator, determining the operation parameter information of the data handling operator may include: taking the second tensor as the input of the data handling operator; taking the first tensor as the output of the data handling operator; and inferring the operation parameter information of the data handling operator based on the first description information and the second description information.

[0066] In another example, when the data handling operator is a data expansion operator, determining the operation parameter information of the data handling operator includes: using the first data shape information as the operation parameter information.

[0067] Thus, the data handling operator that needs to be called and its corresponding parameters are determined.

[0068] Finally, in step 240, a data transfer operator is called based on the determined parameters to convert the first tensor into a memory-continuous state. In this step, the execution of the data transfer operator transfers the data in memory. Because these data transfer operators transfer data continuously based on tensors, they can significantly improve data transfer efficiency compared to transferring data one by one.

[0069] The application of the disclosed embodiments is described below with reference to several specific examples.

[0070] Figure 3 An exemplary flow chart of a data processing method according to an embodiment of the present disclosure is shown.

[0071] As shown in the figure, first, in step 310, it is determined whether the tensor data currently being processed is in a memory continuity state, for example, by using the is_contiguous function in the Pytorch framework. If it is continuous, then no processing is required (step 350). If it is discontinuous, then it can proceed to step 320 to further perform conditional judgment to determine whether the view operator that causes the tensor data to be discontinuous is a reordering view operator.

[0072] In this example, assume that the current tensor data is c, its shape is: c4 = (4, 6, 5, 3), and the dimension step is S c =(30,1,6,120). The is_contiguous function can be used to easily determine whether the tensor data c is in a non-contiguous memory state.

[0073] Next, in step 320, it is determined whether the conditions of the rearrangement view operator are met. Specifically, it is possible to first determine whether the data size of the current tensor data c is the same as the memory address space it points to (step 321). If they are not the same, it means that the tensor data c has not only undergone the rearrangement view operator, and it is possible to determine whether the conditions of other view operators are met (step 360). For example, Figure 4 Describes the conditions for extended view operators. If they are the same, it means that the tensor data may have only undergone rearrangement view operators.

[0074] Continuing with the previous example, assume that the size of the memory address space pointed to by tensor data c is 360. Based on the shape information c4 = (4, 6, 5, 3) of tensor data c, its data size can be calculated as 4 × 6 × 5 × 3 = 360, which is consistent with the size of the memory address space.

[0075] When the size of tensor data c is the same as the memory address space, the dimensional stride of the current tensor data c can be determined to be in descending order (step 322). If it is in descending order, it indicates that tensor data c is memory-contiguous and no processing is required (step 350). If it is not in descending order, it can be determined that tensor data c has undergone a reordering view operator.

[0076] Therefore, the data reordering operator in the computing library (such as the CNNL transpose operator) can be called to perform data manipulation on the tensor data c to convert it into a memory-continuous state.

[0077] Next, in step 330 , the parameters required to call the data rearrangement operator are derived, including description information of the input tensor and operation parameter information.

[0078] Specifically, in step 331, the dimension step information of the tensor data c is arranged in descending order to derive the dimension step information that should correspond to it in the memory continuity state, which is also the dimension step information of the input tensor (assuming it is tensor data a) to be used as the data rearrangement operator. For example, the dimension step of the tensor data c is S c =(30,1,6,120), the corresponding descending order is S a =(120,30,6,1), which is the dimension step information of the input tensor a.

[0079] Next, in step 332, the dimension step S of the tensor data c is set to c Transformed into the dimension step S of tensor data a a According to the change rule of , the shape of the tensor data c is transformed to obtain the shape information of the tensor data a, that is, the data shape information.

[0080] In the above example, if the dimension step size S of the tensor data c is c Identified in sequence as (0, 1, 2, 3), the dimension step of the tensor data a is S a The identifier is (3,0,2,1), which means that the relative position of the dimensions changes from (0,1,2,3) to (3,0,2,1). According to this change rule, a similar transformation is performed on the shape of tensor data c (c4=(4,6,5,3), resulting in the shape of tensor data a (a4=(3,4,5,6).

[0081] Thus, the data shape information and dimension step information in the description information of the tensor data a can be determined.

[0082] Then, in step 333, tensor data a is used as the input tensor of the data rearrangement operator, and the shape of tensor data c is used as the output tensor of the data rearrangement operator. The operation parameter information of calling the data rearrangement operator is determined based on the description information of the input and output.

[0083] In the current example, to transform tensor data a with shape a4 = (3, 4, 5, 6) into an output tensor with shape c4 = (4, 6, 5, 3), the corresponding data reordering operator's operation parameters (axis parameters) can be determined as (1, 3, 2, 0). In other words, if the dimension sequence of tensor data a is (0, 1, 2, 3), then after reordering, the dimension sequence of the output tensor should be changed to (1, 3, 2, 0) to correspond to the output tensor shape c4 = (4, 6, 5, 3).

[0084] Finally, in step 340, the data reordering operator is called to apply data reordering to the input tensor (tensor data a) according to the operation parameters (1, 3, 2, 0) to obtain an output tensor whose shape is consistent with the initial data tensor c to be processed, but is already in a continuous state in the memory.

[0085] Figure 4 An exemplary flow chart of a data processing method according to another embodiment of the present disclosure is shown.

[0086] As shown in the figure, first, in step 410, it is determined whether the currently processed tensor data b is in a memory continuity state, for example, by using the is_contiguous function in the Pytorch framework. If it is continuous, then no processing is required (step 450). If it is discontinuous, then it can proceed to step 420 to further perform conditional judgment to determine whether the view class operator that causes the tensor data to be discontinuous is an extended view class operator.

[0087] In this example, assume that the current tensor data is b, its shape is: b5 = (3, 2, 5, 3, 7), and the dimension step is S b =(35,0,7,0,1). Using the is_contiguous function, we can easily determine whether the tensor data b is in a non-contiguous state in memory.

[0088] Next, in step 420, it is determined whether the conditions of the extended view class operator are met. Specifically, it can be determined first whether there is a dimension step of 0 value in the dimension step of the current tensor data b (step 421). If not, it means that the tensor data b has not undergone the extended view class operator, and it can be determined whether the conditions of other view class operators are met (step 460). For example, Figure 3 The condition for the rearrangement view operator described. If present, it means that the tensor data b has a dimension that has been expanded, that is, it has undergone an expansion view operator.

[0089] At this point, it can be further determined whether it is in a memory continuity state before undergoing the extended view class operator. Specifically, the corresponding dimension size in the data shape information of the tensor data b can be set to 1 according to the position index of the value 0, that is, the extension is removed, and then it is determined whether the obtained data scale is consistent with the memory size pointed to by the tensor data b (step 422). If inconsistent, it means that the tensor data b is not in a memory continuity state before undergoing the extended view class operator. At this time, it can be determined whether the conditions of other view class operators are met (step 460), or the memory continuity processing can be performed in the manner mentioned in the background technology (not shown in the figure). If consistent, it means that the tensor data has only undergone an extended view class operator, and it was in a memory continuity state before undergoing the extended view class operator.

[0090] Continuing with the previous example, assume that the size of the memory address space pointed to by tensor data b is 105. According to the dimension step information S of tensor data b b =(35,0,7,0,1), showing that two dimensions, dim1 and dim3, are derived through expansion. Unexpanding the corresponding dimensions, that is, assigning them a value of 1, yields a shape of (3,1,5,1,7) based on the shape of tensor data b: b5 = (3,2,5,3,7). This shape allows us to calculate the data size to be 3 × 1 × 5 × 1 × 7 = 105, which is consistent with the memory address space.

[0091] Therefore, the data expansion operator in the computing library (such as the CNNL expand operator) can be called to perform data movement processing on the tensor data b to convert it into a memory continuity state.

[0092] Next, in step 430 , the parameters required to call the data expansion operator are derived, including description information of the input tensor and operation parameter information.

[0093] Specifically, in step 431, based on the position index of the 0 value in the dimension stride information of the tensor data b, the corresponding position of its data shape information is set to 1, thereby obtaining the data shape information of the input tensor. It can be understood that the shape after removing the expansion is the data shape before expansion, that is, the shape of the input tensor used as the data expansion operator.

[0094] In this example, the dimension step information S of the tensor data b is b =(35,0,7,0,1), where the step size of dim1 and dim3 is 0. Accordingly, dim1 and dim3 in the shape information b5 = (3,2,5,3,7) of the tensor data b are reset to 1, resulting in the shape before expansion (3,1,5,1,7), which is the shape when the data in the current memory is in a continuous state.

[0095] Next, in step 432, the corresponding dimensional step information, that is, the dimensional step information of the input tensor, is determined based on the derived shape before expansion and the memory continuity rule.

[0096] In this example, based on the derived shape (3, 1, 5, 1, 7), according to the memory continuity principle, the dimension stride can be determined to be (35, 35, 7, 7, 1), which is also the dimension stride information of the input tensor to be used as the data expansion operator.

[0097] Thus, the data shape information and dimension step information in the description information of the input tensor of the data expansion operator can be determined.

[0098] Next, in step 433, the operation parameter information of the data expansion operator is determined. It can be understood that the data expansion operator needs to expand the input tensor to the same shape as the tensor data b currently in the non-contiguous state in memory. Therefore, its operation parameter information is the data shape information of the tensor data b. In this example, it is (3, 2, 5, 3, 7), which means that dim1 needs to be expanded into 2 parts and dim3 needs to be expanded into 3 parts.

[0099] Finally, in step 440, the data expansion operator is called to apply data expansion to the input tensor (shape (3,1,5,1,7), dimension step size (35,35,7,7,1)) according to the operation parameters (3,2,5,3,7) to obtain an output tensor whose shape is consistent with the initial data tensor b to be processed, but is already in a continuous state in the memory, that is, actual data copy expansion has been performed.

[0100] The data processing method of the embodiment of the present disclosure is described above in conjunction with the accompanying drawings to convert tensor data in a non-contiguous memory state into a continuous memory state. The present disclosure also provides a computing device that can be used to execute the above data processing method to achieve memory data continuity.

[0101] Figure 5 1 is a block diagram showing a hardware configuration of a computing device 500 that can implement various schemes of the disclosed embodiments. As shown in the figure, the computing device 500 may include a processor 510 and a memory 520. Figure 5 In the computing device 500, only the components related to this embodiment are shown. Therefore, it is obvious to those skilled in the art that the computing device 500 may also include Figure 5 The components shown in the figure are different from common components, such as displays.

[0102] The computing device 500 may correspond to a computing device having various processing functions, such as functions for compiling a computation graph. For example, the computing device 500 may be implemented as various types of devices, such as a personal computer (PC), a server device, a mobile device, etc.

[0103] The processor 510 is configured to execute program instructions to control all functions of the computing device 500. For example, the processor 510 controls all functions of the computing device 500 by executing a program stored in the memory 520 on the computing device 500. The processor 510 can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an artificial intelligence processor chip (IPU), etc. provided in the computing device 500. However, the present disclosure is not limited thereto.

[0104] Memory 520 is hardware used to store various data processed by computing device 500. For example, memory 520 can store processed data and data to be processed by computing device 500. Memory 520 can also store data processed or to be processed by processor 510, such as pre-compiled and post-compiled computation graphs. Furthermore, memory 520 can store program instructions, such as applications and drivers, to be driven by computing device 500. For example, memory 520 can store various programs related to data processing methods to be executed by processor 510. Memory 520 can be DRAM, but the present disclosure is not limited thereto. Memory 520 can include at least one of volatile memory and non-volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. The volatile memory may include dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, ferroelectric RAM (FeRAM), etc. In an embodiment, the memory 520 may include at least one of a hard disk drive (HDD), a solid-state drive (SSD), a high-density flash memory (CF), a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, caches, or a memory stick.

[0105] In summary, the specific functions implemented by the memory 520 and processor 510 of the computing device 500 provided in the embodiments of this specification can be interpreted in comparison with the aforementioned embodiments in this specification, and can achieve the technical effects of the aforementioned embodiments, so they will not be repeated here.

[0106] In an embodiment of the present disclosure, a computer-readable storage medium is also provided, in which program instructions are stored. When the program instructions are loaded and executed by a processor, the processor executes the calculation graph optimization method or data processing method described in the embodiment of the present disclosure.

[0107] In an embodiment of the present disclosure, a computer program product is also provided, including a computer program or instructions. When the computer program or instructions are executed by a processor, the optimization method or data processing method of the computational graph described in the embodiment of the present disclosure is implemented.

[0108] Figure 6 6 is a structural diagram showing a combined processing device 600 according to an embodiment of the present disclosure. As shown in the figure, the combined processing device 600 includes a computing device 602, an interface device 604, other processing devices 606 and a storage device 608. According to different application scenarios, the computing processing device may include one or more computing devices 610, which may be configured as Figure 5 The computing device 500 shown is used to perform the operations described herein in conjunction with the accompanying drawings.

[0109] In various embodiments, the computing and processing device of the present disclosure may be configured to perform user-specified operations. In exemplary applications, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, the computing and processing device of the present disclosure may be considered to have a single-core structure or a homogeneous multi-core structure.

[0110] In exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through interface means, to jointly complete the operation specified by the user. Depending on the difference in implementation, the other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as central processing unit (Central Processing Unit, CPU), graphics processing unit (Graphics Processing Unit, GPU), artificial intelligence processor. These processors may include but are not limited to digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0111] In one or more embodiments, the other processing device may serve as an interface between the computing device disclosed herein (which may be embodied as an artificial intelligence computing device such as a neural network computing device) and external data and control, performing basic control including but not limited to data transfer, starting and / or stopping the computing device, and so on. In other embodiments, the other processing device may also collaborate with the computing device to jointly complete computing tasks.

[0112] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it to the storage device (or memory) on the computing and processing device chip. Furthermore, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them to the control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0113] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0114] In some embodiments, the present disclosure also discloses a chip (e.g. Figure 7 In one implementation, the chip is a system on chip (SoC) and integrates one or more components such as Figure 6 The chip can be connected to the external interface device (such as Figure 7 The external interface device 706 shown in the figure is connected to other related components. The related components can be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and / or interface modules (such as DRAM interfaces) can be integrated on the chip. In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 7 The board is described in detail.

[0115] Figure 7 is a structural diagram showing a board 700 according to an embodiment of the present disclosure. As shown in the figure, the board includes a storage device 704 for storing data, which includes one or more storage units 710. The storage device can be connected and transmit data with the control device 708 and the chip 702 described above in a manner such as a bus. Further, the board also includes an external interface device 706, which is configured for data relay or transfer function between the chip (or the chip in the chip packaging structure) and the external device 712 (such as a server or computer, etc.). For example, the data to be processed can be passed to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0116] In one or more embodiments, the control device in the disclosed board can be configured to regulate the state of the chip. To this end, in one application scenario, the control device can include a microcontroller unit (MCU) for regulating the working state of the chip.

[0117] According to the above combination Figure 6 and Figure 7 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0118] According to different application scenarios, the electronic devices or devices disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, vehicles, household appliances, and / or medical equipment. The vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs. The electronic devices or devices disclosed herein may also be applied to the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic devices or devices disclosed herein may also be used in cloud, edge, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or apparatuses with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0119] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teachings of the present disclosure, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present disclosure can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present disclosure. In addition, depending on the different schemes, the description of some embodiments of the present disclosure also has different emphases. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

[0120] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this document divides them based on the consideration of logical functions, and there may be other ways of division in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0121] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solution described in the embodiments of this disclosure. In addition, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically separately.

[0122] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0123] The foregoing content can be better understood in accordance with the following terms:

[0124] Clause 1. A data processing method comprising:

[0125] In response to a first tensor to be processed being in a memory non-contiguous state, determining, according to first description information of the first tensor, a view operator that the first tensor undergoes when transitioning from a memory continuous state to the memory non-contiguous state;

[0126] Determine the data handling operator in the calculation library that needs to be called according to the view class operator;

[0127] Determining, according to the first description information, parameters required for calling the data handling operator to convert the first tensor from the non-contiguous memory state to the continuous memory state; and

[0128] The data handling operator is called according to the parameter to transform the first tensor into a memory continuity state.

[0129] Clause 2. The method of clause 1, wherein determining the view-type operator that the first tensor has undergone comprises:

[0130] Determine a view operator that the first tensor undergoes according to the first data shape information and the first dimension step information in the first description information.

[0131] Clause 3. The method of clause 2, wherein determining the view-type operator undergone by the first tensor further comprises:

[0132] When the data scale indicated by the first data shape information is consistent with the memory size pointed to by the first tensor, and the first dimension step information indicates that the steps of each dimension are arranged in non-descending order, it is determined that the view type operator experienced by the first tensor is a rearrangement view type operator.

[0133] Clause 4. The method according to any one of clauses 2-3, wherein determining the view operator undergone by the first tensor further comprises:

[0134] When there is a dimension step of 0 in the first dimension step information, and the data scale obtained after adjusting the first data shape information according to the position index of 0 is consistent with the memory size pointed to by the tensor data, it is determined that the view class operator experienced by the first tensor is an extended view class operator.

[0135] Clause 5. The method according to any one of Clauses 1 to 4, wherein determining the data handling operator to be called based on the view class operator comprises:

[0136] When the view operator is a rearrangement view operator, determining that the data handling operator to be called is a data rearrangement operator; or

[0137] When the view class operator is an extended view class operator, it is determined that the data handling operator to be called is a data extension operator.

[0138] Clause 6. The method according to any one of clauses 1 to 5, wherein determining the parameters required to call the data handling operator comprises:

[0139] determining second descriptive information of a second tensor serving as an input tensor of the data handling operator; and

[0140] Determine the operation parameter information of the data handling operator.

[0141] Clause 7. The method according to clause 6, wherein when the data manipulation operator is a data rearrangement operator, determining the second description information of the second tensor comprises:

[0142] Determine the descending order of the first dimension step information in the first description information as the second dimension step information in the second description information of the second tensor; and

[0143] According to the change rule of converting the first dimensional step information into the descending order, the first data shape information in the first description information is converted to obtain the second data shape information in the second description information.

[0144] Clause 8. The method of clause 6, wherein when the data manipulation operator is a data expansion operator, determining the second description information of the second tensor comprises:

[0145] Obtaining a position index corresponding to a value of 0 from the first dimension step information in the first description information;

[0146] According to the position index of the 0 value, setting a corresponding position of the first data shape information in the first description information to 1 to determine the second data shape information in the second description information; and

[0147] The second dimension step information in the second description information is determined according to the second data shape information and the memory continuity rule.

[0148] Clause 9. The method according to any one of clauses 6 to 8, wherein when the data manipulation operator is a data rearrangement operator, determining the operation parameter information of the data manipulation operator comprises:

[0149] Using the second tensor as input to the data handling operator;

[0150] Using the first tensor as the output of the data handling operator; and

[0151] The operation parameter information of the data handling operator is inferred based on the first description information and the second description information.

[0152] Clause 10. The method according to any one of clauses 6 to 8, wherein when the data handling operator is a data expansion operator, determining the operation parameter information of the data handling operator comprises:

[0153] The first data shape information is used as the operation parameter information.

[0154] Clause 11. A computing device comprising:

[0155] a processor configured to execute program instructions; and

[0156] A memory configured to store the program instructions, which, when loaded and executed by the processor, causes the processor to perform the data processing method according to any one of clauses 1 to 10.

[0157] Clause 12. A computer-readable storage medium storing program instructions, which, when loaded and executed by a processor, causes the processor to perform the data processing method according to any one of clauses 1 to 10.

[0158] Clause 13. A computer program product comprising a computer program or instructions, which, when executed by a processor, implements the data processing method described in any one of Clauses 1 to 10.

[0159] Although a plurality of embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many modifications, changes, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The appended claims are intended to define the scope of protection of the present disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A data processing method, comprising: In response to a first tensor to be processed being in a memory non-contiguous state, determining, according to first description information of the first tensor, a view operator that the first tensor undergoes when transitioning from a memory continuous state to the memory non-contiguous state; Determine the data handling operator in the calculation library that needs to be called according to the view class operator; Determining, according to the first description information, parameters required for calling the data handling operator to convert the first tensor from the non-contiguous memory state to the continuous memory state; and The data handling operator is called according to the parameter to transform the first tensor into a memory continuity state.

2. The method according to claim 1, wherein determining the view-type operator undergone by the first tensor comprises: Determine a view operator that the first tensor undergoes according to the first data shape information and the first dimension step information in the first description information.

3. The method according to claim 2, wherein determining the view-type operator undergone by the first tensor further comprises: When the data scale indicated by the first data shape information is consistent with the memory size pointed to by the first tensor, and the first dimension step information indicates that the steps of each dimension are arranged in non-descending order, it is determined that the view type operator experienced by the first tensor is a rearrangement view type operator.

4. The method according to any one of claims 2 to 3, wherein determining the view operator undergone by the first tensor further comprises: When there is a dimension step of 0 in the first dimension step information, and the data scale obtained after adjusting the first data shape information according to the position index of 0 is consistent with the memory size pointed to by the first tensor, it is determined that the view class operator experienced by the first tensor is an extended view class operator.

5. The method according to any one of claims 1 to 3, wherein determining the data handling operator to be called according to the view operator comprises: When the view operator is a rearrangement view operator, determining that the data handling operator to be called is a data rearrangement operator; or When the view class operator is an extended view class operator, it is determined that the data handling operator to be called is a data extension operator.

6. The method according to claim 2, wherein determining the parameters required to call the data handling operator comprises: Determining second descriptive information of a second tensor as an input tensor of the data handling operator; as well as Determine the operation parameter information of the data handling operator.

7. The method according to claim 6, wherein when the data manipulation operator is a data rearrangement operator, determining the second description information of the second tensor comprises: Determine the descending order of the first dimension step information in the first description information as the second dimension step information in the second description information of the second tensor; as well as According to the change rule of converting the first dimensional step information into the descending order, the first data shape information in the first description information is converted to obtain the second data shape information in the second description information.

8. The method according to claim 6, wherein when the data manipulation operator is a data expansion operator, determining the second description information of the second tensor comprises: Obtaining a position index corresponding to a value of 0 from the first dimension step information in the first description information; According to the position index of the 0 value, a corresponding position of the first data shape information in the first description information is set to 1 to determine the second data shape information in the second description information; as well as The second dimension step information in the second description information is determined according to the second data shape information and the memory continuity rule.

9. The method according to any one of claims 6 to 8, wherein when the data handling operator is a data rearrangement operator, determining the operation parameter information of the data handling operator comprises: Using the second tensor as input to the data handling operator; Using the first tensor as the output of the data handling operator; as well as The operation parameter information of the data handling operator is inferred based on the first description information and the second description information.

10. The method according to any one of claims 6 to 8, wherein when the data handling operator is a data expansion operator, determining the operation parameter information of the data handling operator comprises: The first data shape information is used as the operation parameter information.

11. A computing device comprising: a processor configured to execute program instructions; as well as A memory configured to store the program instructions, which, when loaded and executed by the processor, enables the processor to execute the data processing method according to any one of claims 1 to 10.

12. A computer-readable storage medium storing program instructions, wherein when the program instructions are loaded and executed by a processor, the processor is caused to execute the data processing method according to any one of claims 1 to 10.

13. A computer program product, comprising a computer program or instructions, which implements the data processing method according to any one of claims 1 to 10 when executed by a processor.

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