Video memory access method, device, system, storage medium and program product

Abstract

The present application provides a method, device, system, storage medium and program product for accessing video memory. For a computer system in which an external graphics card and a central processing unit adopt different types of architectural designs, the method includes: obtaining data operation instructions of the graphics card via the central processing unit, wherein the data address of the data operation instruction is a VRAM space address; determining the bridge chip address corresponding to the data address via the central processing unit using a preset address mapping relationship; sending the bridge chip address to the hypertransmission module of the bridge chip via the first hypertransmission bus; mapping the bridge chip address to a high-speed bus bridge address via the hypertransmission module; and sending the data to be operated to the address in the VRAM space corresponding to the data address via the high-speed bus bridge according to the high-speed bus bridge address. The solution of the present application can realize access to the VRAM space of the independent graphics card without modifying the VBIOS program, thereby improving the CPU compatibility with the independent graphics card.

Description

Technical Field

[0001] The present application relates to computer technology, and in particular to a method, device, system, storage medium, and program product for accessing video memory. Background Art

[0002] Graphics cards are used to control the computer's image display. Commonly used graphics cards are divided into two types based on their settings: discrete graphics cards and integrated graphics cards. Discrete graphics cards generally offer better performance and technological advancement than integrated graphics cards. Therefore, in scenarios with special requirements for graphics processing performance (such as large-screen display scenarios like gaming), users typically use discrete graphics cards.

[0003] Video memory (GPU memory) is a storage device used by graphics cards to store image data being processed or about to be processed. Video RAM (VRAM) is a form of video memory. When displaying an image, the graphics card or central processing unit (CPU) accesses VRAM to allocate display data. After a series of calculations, the image information is ultimately presented on the display interface. Currently, different discrete graphics cards can be based on different architectures. For example, some graphics cards are designed based on the x86 architecture, while others are based on non-x86 architectures. The x86 architecture and non-x86 architecture each encompass different types of architectures, such as ARM and RISC-V. Due to differences in instruction sets and microarchitectures across processor architectures, when a non-x86 processor and an x86 graphics card (hereafter referred to as an x86 graphics card) are used together, the non-x86 processor cannot directly access the required data using the default VRAM address. This means that non-x86 processors and x86 graphics cards cannot directly work together.

[0004] In the related art, in order to properly use an x86 architecture (e.g., x86 architecture type A) graphics card in a non-x86 architecture system, it is necessary to modify the Video Basic Input / Output System (VBIOS) program based on the A-architecture graphics card. However, after modifying the VBIOS, the system is only compatible with the A-architecture graphics card and may still be incompatible with graphics cards of other architectures, which may also cause inconvenience in subsequent maintenance. Summary of the Invention

[0005] The present application provides a video memory access method, device, system, storage medium and program product to enable normal access to the VRAM space of an independent graphics card by a non-x86 architecture, thereby improving the compatibility of the CPU with the independent graphics card.

[0006] In a first aspect, the present application provides a method for accessing video memory, the method comprising: obtaining, via a central processing unit, a data operation instruction of a graphics card, the data operation instruction comprising data to be operated and a data address, the data address being an address in a video random access memory (VRAM) space; determining, via the central processing unit, a bridge chip address corresponding to the data address using a preset address mapping relationship; wherein the preset address mapping relationship comprises a correspondence between a VRAM space address and a bridge chip address; and sending, via the bridge chip, the data to be operated to an address in the VRAM space corresponding to the data address through the bridge chip address corresponding to the data address.

[0007] Optionally, after the central processor determines the bridge chip address corresponding to the data address using a preset address mapping relationship, the method further includes:

[0008] The bridge chip address is sent to the HyperTransport module of the bridge chip via the first HyperTransport bus; the bridge chip address is mapped to a high-speed bus bridge address via the HyperTransport module, wherein the high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is part of the bridge chip and is a conversion component corresponding to the high-speed bus.

[0009] Correspondingly, sending the data to be operated to the address in the VRAM space corresponding to the data address via the bridge chip through the bridge chip address includes:

[0010] The data to be operated is sent to an address in the VRAM space corresponding to the data address via the high-speed bus bridge and according to the high-speed bus bridge address.

[0011] Optionally, the high-speed bus is a PCIE bus, the high-speed bus bridge is a PCIE bridge, and the high-speed bus bridge address is a PCIE bridge address, and the method further includes:

[0012] The base address register of the PCIE bridge is configured via the central processing unit so that the PCIE bridge address of the PCIE bridge corresponds to the address of the VRAM space.

[0013] Optionally, obtaining data operation instructions from the graphics card via the central processing unit includes:

[0014] The data operation instruction in the VBIOS program is read through the central processing unit; if the data operation instruction is an x86 instruction, the x86 simulator in the central processing unit is called to execute the data operation instruction to obtain the data to be operated and the VRAM space address corresponding to the data operation instruction.

[0015] Optionally, the method further includes:

[0016] The high-speed bus scanning program is executed via the central processor to scan the devices connected to the bridge chip via the high-speed bus; if a graphics card is scanned, the graphics card firmware (VBIOS) is loaded and the VBIOS program corresponding to the graphics card is read.

[0017] Optionally, the preset address mapping relationship includes: a correspondence between VRAM space addresses 0xA_0000 to 0xC_0000 and bridge chip addresses VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000.

[0018] In a second aspect, the present application provides a video memory access device for use in a computer system, the computer system comprising at least a central processing unit (CPU), a bridge chip, and external components, wherein the CPU and the bridge chip are connected via a first HyperTransport bus, and the bridge chip and the external components are connected via a high-speed bus; the external components include a graphics card, and the CPU and the graphics card are designed based on different types of architectures; the device comprises:

[0019] An instruction acquisition module is used to obtain data operation instructions of the graphics card via the CPU, and the data operation instructions include data to be operated and a data address, and the data address is an address in the video random access memory (VRAM) space; a bridge chip address determination module is used to determine the bridge chip address corresponding to the data address via the CPU using a preset address mapping relationship; wherein the preset address mapping relationship includes a correspondence between the VRAM space address and the bridge chip address; a data to be operated sending module is used to send the data to be operated to the address in the VRAM space corresponding to the data address via the bridge chip through the bridge chip address corresponding to the data address.

[0020] Optionally, the device further includes:

[0021] A bridge chip address transmission module is used to determine the bridge chip address corresponding to the data address via the CPU using a preset address mapping relationship, and then send the bridge chip address to the hypertransport module of the bridge chip via the first hypertransport bus; the bridge chip address is mapped to a high-speed bus bridge address via the hypertransport module, wherein the high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is a part of the bridge chip and is a conversion component corresponding to the high-speed bus.

[0022] The module for sending data to be operated is specifically used for:

[0023] The data to be operated is sent to an address in the VRAM space corresponding to the data address via the high-speed bus bridge and according to the high-speed bus bridge address.

[0024] Optionally, the high-speed bus is a PCIE bus, the high-speed bus bridge is a PCIE bridge, the high-speed bus bridge address is a PCIE bridge address, and the device further includes:

[0025] The address configuration module is used to configure the base address register of the PCIE bridge via the CPU so that the PCIE bridge address of the PCIE bridge corresponds to the address of the VRAM space.

[0026] Optional instruction acquisition module, specifically used to:

[0027] The CPU reads a data operation instruction in the VBIOS program; if the data operation instruction is an x86 instruction, the x86 simulator in the CPU is called to execute the data operation instruction to obtain the data to be operated and the VRAM space address corresponding to the data operation instruction.

[0028] Optionally, the device further includes:

[0029] The program reading module is used to execute the high-speed bus scanning program through the CPU to scan the devices connected to the bridge chip through the high-speed bus; if a graphics card is scanned, the graphics card firmware is loaded and the VBIOS program corresponding to the graphics card is read.

[0030] In a third aspect, the present application provides a computer system comprising: a central processing unit (CPU), a bridge chip, and external components, wherein the CPU and the bridge chip are connected via a first HyperTransport bus, and the bridge chip is connected to the external components via a high-speed bus; the external components include a graphics card, and the CPU and the graphics card are designed based on graphics cards of different types of architectures; the CPU is used to obtain data operation instructions from the graphics card, the data operation instructions including data to be operated and a data address, the data address being an address in a video random access memory (VRAM) space; and using a preset address mapping relationship to determine a bridge chip address corresponding to the data address; wherein the preset address mapping relationship includes a correspondence between a VRAM space address and a bridge chip address; via the first HyperTransport bus, the bridge chip address is sent to a HyperTransport module of the bridge chip; via the HyperTransport module, the bridge chip address is mapped to a high-speed bus bridge address, wherein the high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is part of the bridge chip and is a conversion component corresponding to the high-speed bus; via the high-speed bus bridge, according to the high-speed bus bridge address, the data to be operated is sent to an address in the VRAM space corresponding to the data address.

[0031] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a central processing unit, the method described in the first aspect is implemented.

[0032] In a fifth aspect, the present application provides a program product, which includes a computer program, and the computer program is stored in a readable storage medium. The central processing unit of an electronic device can read the computer program from the readable storage medium, and the central processing unit executes the computer program so that the electronic device implements the method described in the first aspect.

[0033] The present application provides a method, device, system, storage medium and program product for accessing video memory. When the central processing unit receives a data operation instruction for accessing a graphics card, that is, the data address of the data operation instruction is a VRAM address, the central processing unit maps the data address to the corresponding bridge chip address based on a pre-stored address mapping relationship, thereby sending the data operation instruction to the bridge chip. The bridge chip then sends its data to be operated to the VRAM space corresponding to the data address based on the bridge chip address corresponding to the data operation instruction, thereby achieving access to the independent graphics card. The solution of the present application can achieve normal access to the VRAM space of the independent graphics card through address mapping without modifying the VBIOS program, thereby improving the compatibility of the central processing unit with various independent graphics cards. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1 A schematic diagram of an application scenario provided by this application;

[0036] Figure 2 A flowchart of a video memory access method provided in an embodiment of the present application;

[0037] Figure 3 A flowchart of another video memory access method provided in an embodiment of the present application;

[0038] Figure 4 A schematic structural diagram of a video memory access device provided in an embodiment of the present application;

[0039] Figure 5 A schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the structure of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0042] First, let’s explain the terms involved in this application:

[0043] Central processing unit (CPU): The computing and control core of a computer system, and the final execution unit for information processing and program execution.

[0044] Video Random Access Memory (VRAM): A form of video memory used by graphics cards and graphics cards.

[0045] Basic Input / Output System (BIOS): A set of programs stored on a ROM chip on the computer's motherboard. It stores the computer's most important basic input / output (BIO) routines, the power-on self-test (PTT) routine, and the system startup routine. It reads and writes detailed system configuration information from the Complementary Metal-Oxide-Semiconductor (CMOS). Its primary function is to provide the lowest-level, most direct hardware configuration and control for the computer. The BIOS also provides system parameters to the operating system.

[0046] BIOS stage: power-on self-test, hardware initialization program, CMOS setup program, system automatic loading program, main I / O driver and interrupt service and other stages.

[0047] Video Basic Input Output System (VBIOS): It is the BIOS on the graphics card, which is stored in a dedicated memory on the graphics card and is mainly used to store the control program between the display chip and the driver.

[0048] Hyper Transport (HT): An end-to-end bus technology designed for interconnecting integrated circuits on a motherboard.

[0049] Peripheral Component Interconnect Express (PCIE): A new bus and interface standard with high data transfer rates and great potential. All mainstream motherboards support the PCIE bus.

[0050] Graphics Processing Unit (GPU): also known as display core, visual processor, or display chip, it is a microprocessor specifically designed to perform image and graphics-related calculations on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones).

[0051] North and South Bridge: A widely used motherboard chipset architecture, generally connected through the PCI (Peripheral Component Interconnect) bus.

[0052] Bridge chip: Mainly responsible for controlling the data exchange between the AGP (Accelerate Graphical Port) graphics card, memory and CPU, as well as responsible for the data exchange between the driver, hard disk, keyboard and add-in card.

[0053] Most graphics cards are designed based on the x86 architecture, so using x86 architecture graphics cards in non-x86 architecture (such as RISC architecture) CPU platforms will have great compatibility issues, thereby reducing the selectivity of graphics cards for other platforms.

[0054] In specific applications, the graphics card needs to be initialized before use. During the graphics card initialization process, the CPU generally executes the VBIOS program to write the graphics card initialization parameters into the video memory (i.e., VRAM space). The VRAM space address of the x86 architecture graphics card generally defaults to 0xA_0000~0xC_0000. Because most graphics cards are adapted to the x86 architecture, the CPU of the x86 architecture platform can directly access this address to complete the writing of the initialization parameters. However, on non-x86 architecture platforms, the CPU cannot directly access this address space, and therefore cannot directly write the initialization parameters into the VRAM space, thus failing to successfully complete the graphics card initialization process.

[0055] To adapt an x86 graphics card to a non-x86 architecture platform, GPU chip manufacturers may choose to modify the VBIOS program based on the architecture type, so that the modified VBIOS program can be executed by the CPU and the initialization parameters can be written to the video memory smoothly. Although this modification can make the graphics card compatible with the corresponding architecture platform, it may still not be applicable to other architecture platforms. Accordingly, to adapt to other architecture platforms, adaptive modifications for specific architecture platforms are still required. This will reduce the compatibility of the graphics card itself, and the increase in VBIOS program versions will also increase the workload of subsequent maintenance.

[0056] Therefore, how to make a graphics card designed based on one architecture work well on another architecture platform is a technical problem that needs to be solved urgently.

[0057] Based on this, this application proposes another solution that can improve the compatibility of one architecture platform (e.g., non-x86) with graphics cards designed based on another architecture platform (e.g., x86) without modifying the VBIOS program. Based on the principle of address mapping, this solution maps the data address of instructions accessing VRAM space to a bridge chip address, thereby enabling access to VRAM space through the bridge chip address, such as for graphics card initialization.

[0058] Figure 1 This is a schematic diagram of an application scenario provided by this application. Figure 1 As shown, the solution of the present application can be applied to terminal devices. An independent graphics card is installed for the terminal device, and the independent graphics card is connected to the CPU of the terminal device through a bridge chip; wherein, the CPU is used to execute relevant software programs to issue control instructions; the bridge chip serves as a bridge for communication between the CPU and the external components of the CPU, and is used to transmit data between the CPU and the external components of the CPU; the independent graphics card is used to receive the control instructions of the CPU sent by the bridge chip to display the corresponding data on the display device. First, the CPU executes the method of the present application to write the initialization parameters into the VRAM space to initialize the independent graphics card. Among them, the architecture types of the CPU and the graphics card are different, such as the CPU can be a non-x86 architecture processor, etc.; the GPU chip in the independent graphics card is a chip designed with the x86 architecture, and the VRAM space reserved when the graphics card is initialized is the default storage space of the x86 architecture. The CPU and the bridge chip are connected through the HT bus, and the bridge chip and the independent graphics card are connected through a high-speed bus (such as a PCI bus or a PCIE bus). For specific implementation methods, please refer to the following embodiments.

[0059] Figure 2A flowchart of a video memory access method provided in one embodiment of the present application is applied to a computer system, wherein the computer system includes a CPU, a bridge chip, and external components, wherein the CPU and the bridge chip are connected via a first HyperTransport bus, and the bridge chip and the external components are connected via a high-speed bus, wherein the external components include a graphics card, and the CPU and the graphics card are designed based on different types of architectures.

[0060] It should be noted that, unless otherwise specified, the processor referred to in this application is a central processing unit.

[0061] In this embodiment, the CPU and graphics card have different architecture types. For example, the architecture corresponding to the CPU is the x86 architecture, and the architecture corresponding to the GPU in the graphics card is the non-x86 architecture. In the BIOS stage of the computer system, in order to access the video memory of the external graphics card with a different architecture from the CPU of the computer system, a video memory access method is provided, such as Figure 2 As shown, the video memory access method provided in this embodiment includes the following steps:

[0062] S201. In the BIOS stage of the computer system, a data operation instruction of a graphics card is obtained via a CPU. The data operation instruction includes data to be operated and a data address. The data address is an address in a VRAM space.

[0063] In this embodiment, the data operation instruction may be an instruction for accessing a graphics card, and the graphics card may be an independent graphics card, such as a graphics card designed based on an x86 architecture.

[0064] The data operation instruction may be an initialization configuration instruction of the graphics card, so as to initialize the graphics card through the initialization parameters in the initialization configuration instruction. The initialization parameter is a type of data to be operated.

[0065] During graphics card initialization, the data manipulation instruction can be a write instruction or an initialization configuration instruction. When the data manipulation instruction is a write instruction, the data to be manipulated is the data to be written. Specifically, the data to be written can be graphics card initialization parameters, which are stored in the corresponding addresses of the graphics card's VRAM space to initialize the graphics card.

[0066] Furthermore, the data address is the address in the video memory where the data to be written is to be written, and the address in the video memory is the address in the VRAM space of the graphics card.

[0067] S202: The CPU uses a preset address mapping relationship to determine a bridge chip address corresponding to the data address.

[0068] The preset address mapping relationship includes a corresponding relationship between a VRAM space address and a bridge chip address.

[0069] In one embodiment, the CPU includes a cross-mapping module, in which the address mapping relationship is stored.

[0070] The CPU can read the address mapping relationship from the cross-mapping module, and then map the data address in the above data operation instruction to the corresponding bridge chip address based on the address mapping relationship.

[0071] Specifically, the data address in the above data operation instruction can be mapped to the corresponding bridge chip address through address mapping via a cross-mapping module in the CPU based on the stored address mapping relationship.

[0072] In this embodiment of the application, the independent graphics card is connected to the bridge chip via a high-speed bus (such as the PCIE bus / PCI bus). Therefore, to perform data operations on the VRAM space in the graphics card, it is first necessary to open a path between the bridge chip and the VRAM. Here, address mapping is used to establish a connection between the bridge chip address and the VRAM address.

[0073] A range of bridge chip addresses, such as the space from 0xA_0000 to 0xC_0000, can be pre-selected from the bridge chip as the mapping space of the VRAM space, thereby obtaining the above-mentioned preset address mapping relationship. The mapping between the bridge chip address and the address in the VRAM space can be achieved through the corresponding mapping code, that is, the above-mentioned preset address mapping relationship is achieved. When the data address in the data operation instruction is obtained, the data address in the VRAM space is translated or mapped to the corresponding bridge chip address in the bridge chip through the mapping code corresponding to the address mapping relationship.

[0074] For example, taking the data address 0xA_1234 as an example, the data address can be mapped to the bridge address 0x90000e00_000a1234 through the above address mapping.

[0075] Furthermore, the CPU may send data operation instructions to the bridge chip through a corresponding high-speed bus based on the bridge chip address.

[0076] S203 , sending the data to be operated to the address in the VRAM space corresponding to the data address via the bridge chip and the bridge chip address corresponding to the data address.

[0077] Based on the mapping relationship between the VRAM space address and the bridge chip address, when writing data to the VRAM space, the data can be transferred to the VRAM space via the bridge chip.

[0078] After obtaining the bridge address corresponding to the data address, the bridge address is automatically mapped to the high-speed bus, and the address in the VRAM space corresponding to the bridge address is accessed through the high-speed bus, thereby sending the operand to the address in the VRAM space corresponding to the data address.

[0079] After the data operation instruction is sent to the bridge chip through the corresponding bridge chip address, the bridge chip forwards the data operation instruction through the high-speed bus based on the bridge chip address corresponding to the data operation instruction, thereby sending the data to be operated to the corresponding VRAM space for accessing the VRAM space, such as writing the data to be operated.

[0080] The video memory access method provided by this embodiment is that when the CPU of a computer system receives a data operation instruction to access a graphics card, that is, the data address of the data operation instruction is a VRAM address, the processor maps the data address to the corresponding bridge chip address based on a pre-stored address mapping relationship, thereby sending the data operation instruction to the bridge chip. The bridge chip address corresponding to the data operation instruction will be mapped to the high-speed bus. The bridge chip can send the data to be operated to the VRAM space of the graphics card corresponding to the data address via the high-speed bus based on the VRAM address corresponding to the bridge chip address, thereby realizing access to the independent graphics card. The solution of this application can realize normal access to the VRAM space of the independent graphics card through address mapping without modifying the VBIOS program, thereby improving the compatibility of the CPU with independent graphics cards of various types of architectures.

[0081] If multiple external components are connected to the bridge chip through a high-speed bus (such as a PCIE bus), address resource allocation needs to be performed through the PCIE bridge, that is, a set of corresponding PCIE bridge addresses is allocated to the multiple external components connected to the PCIE bridge.

[0082] Correspondingly, the above-mentioned video memory access method further includes: allocating a PCIE bridge address corresponding to the data address to the PCIE bridge according to the VRAM space address. The above-mentioned step S203 may specifically include: sending the data to be operated to the VRAM space corresponding to the data address via the bridge chip according to the bridge chip address corresponding to the data address and the PCIE bridge address corresponding to the data address.

[0083] The bridge chip is connected to the processor via a first HyperTransport bus HT1. The bridge chip includes a first HyperTransport module, a PCIE bridge and other modules.

[0084] Figure 3 A flowchart of another method for accessing video memory provided in an embodiment of the present application. Figure 2 On the basis of the embodiment shown, a step of mapping the bridge chip address to the high-speed bus bridge address is added after step S202, such as Figure 3 As shown, the video memory access method provided in this embodiment may include the following steps:

[0085] S301. In the BIOS stage of the computer system, obtain data operation instructions of a graphics card via the CPU.

[0086] S302: Determine, via the CPU, a bridge chip address corresponding to the data address using a preset address mapping relationship.

[0087] S303: Send the bridge chip address to the HyperTransport module of the bridge chip via the first HyperTransport bus.

[0088] S304: Map the bridge chip address to a high-speed bus bridge address via the HyperTransport module.

[0089] The high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is a part of the bridge chip, and is a conversion component corresponding to the high-speed bus.

[0090] S305 : Send the initialization parameter to the address in the VRAM space corresponding to the data address via the high-speed bus bridge and according to the high-speed bus bridge address.

[0091] The bridge chip address corresponding to the data operation instruction can be sent to the HyperTransport module of the bridge chip via the first HyperTransport bus HT1, and the bridge chip address can be mapped to the high-speed bus bridge address via the HyperTransport module, so as to obtain the high-speed bus bridge address corresponding to the data operation instruction; then, via the high-speed bus bridge, according to the high-speed bus bridge address corresponding to the data operation instruction, the data to be operated in the data operation instruction is sent to the VRAM space corresponding to the data address in the data operation instruction via the high-speed bus, thereby realizing access to the graphics card.

[0092] The address corresponding to the VRAM space is the default address of the graphics card and is an implicit address. When the CPU allocates address resources for the graphics card, this address space is not allocated. Therefore, this address space is not included in the high-speed bus bridge. This address space must be allocated separately for the high-speed bus bridge so that when data reaches the high-speed bus bridge, it can be transferred to the external component corresponding to the target address, that is, the graphics card's VRAM space.

[0093] Optionally, the high-speed bus is a PCIE bus, the high-speed bus bridge is a PCIE bridge, and the high-speed bus bridge address is a PCIE bridge address.

[0094] Specifically, the base address register of the PCIE bridge may be configured via the processor so that the PCIE bridge address of the PCIE bridge corresponds to the address of the VRAM space.

[0095] Since the addresses of the VRAM space are typically 0xA_0000 to 0xC_0000, sufficient addresses, such as 250MB, can be configured for the VRAM space in the PCIE bridge to cover access to all addresses in the VRAM space. In a specific embodiment, the base address register (Memory Base) of the PCIE bridge address corresponding to the VRAM space in the PCIE bridge can be set to a, and the upper limit address register (Memory Limit) can be set to b. The address space between a and b contains no less than 250MB of address space. This allows the PCIE bus between the PCIE bridge and the graphics card to receive bus transactions accessing the space from 0 to 250MB, and an address sequence within 0 to 250MB is generated on the PCIE bus. Combined with the newly allocated address, the address sequence from 0xA_0000 to 0xC_0000 can be generated on the bus where the graphics card is located, allowing the graphics card to receive access transactions to the VRAM space.

[0096] Among them, the base address register and the upper limit address register determine the starting address and ending address of the PCIE bridge respectively.

[0097] In some embodiments, after the graphics card is initialized, the address of the PCIE bridge may be restored to its previous state to avoid errors in subsequent other data operations.

[0098] In a specific implementation process, the above method may be encapsulated into a software program, and the CPU executes the software program to implement the above method.

[0099] The programming language of the software program may affect the character type and length of the corresponding operation instructions. Among them, the address space mapping may involve different address space bit numbers.

[0100] In some embodiments, if the programming language is inconsistent with the address length supported by the CPU, the above-mentioned step S202 may specifically include: determining the bridge address corresponding to the data address based on the preset address mapping relationship and the preset X1 Switch mapping. That is, adding the X1 Switch mapping, establishing a correspondence between addresses of different lengths (i.e., the address obtained by the programming language is different from the address length of the bridge address read by the CPU), converting the length of the address obtained by the programming language that is inconsistent with the address length supported by the CPU to the address length supported by the CPU, so that the final determined bridge address is an address that can be directly recognized by the CPU. Among them, the X1 Switch (first-level crossbar switch) is a manager for managing space address mapping.

[0101] In one embodiment, the preset address mapping relationship may be: a correspondence relationship between VRAM space addresses 0xA_0000 to 0xC_0000 and bridge chip addresses VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000.

[0102] VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000 are the address ranges pointing to the bridge chip. VGA_BASE is the first address in the address space corresponding to the bridge chip, such as 0x1E00_0000, 0xBE00_0000, or other addresses, which can be determined by the CPU.

[0103] The physical space corresponding to VGA_BASE+0xA_0000~VGA_BASE+0xC_0000 of the bridge chip, such as the physical space 0x1E00_000+0xA_0000~0x1E00_000+0xC_0000, will be mapped by the X1 Switch to a bridge chip address range, such as 0x90000e00_000a0000~0x90000e00_000c0000. Then, the data operation instructions corresponding to this bridge chip address range are sent to the PCIE address space of the bridge chip 0xA_0000~0xC_0000 through the PCIE bus, and the data operation instructions corresponding to this PCIE address space are sent to the corresponding VRAM space through the PCIE bus.

[0104] In some embodiments, the method for determining the data to be operated and the VRAM space address in the above-mentioned data operation instruction may include: reading the data operation instruction in the VBIOS program from the graphics card via the processor; if the data operation instruction is an x86 instruction, calling the x86 emulator to execute the data operation instruction to obtain the data to be operated in the data operation instruction, such as graphics card initialization parameters, and the VRAM space address.

[0105] The x86 simulator can simulate the x86 architecture, execute the data operation instructions in the VBIOS program, and obtain the parameters corresponding to the data operation instructions from the execution results, including the above-mentioned data to be operated and the VRAM space address.

[0106] In one embodiment, the x86 simulator can also translate data operation instructions to translate the data addresses therein into corresponding addresses within the address range of VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000, and then map the addresses translated by the x86 simulator into bridge addresses based on the address mapping relationship stored in the processor.

[0107] In one embodiment, the address mapping relationship may include: a correspondence between the VRAM space addresses 0xA_0000 to 0xC_0000 and the translation addresses VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000, and a one-to-one mapping correspondence between the translation addresses VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000 VRAM and the bridge chip addresses 0x90000e00_00000000+0xA_0000 to 0x90000e00_00000000+0xC_0000. That is, through the address mapping relationship, the addresses in 0xA_0000 to 0xC_0000 are first mapped or translated into addresses in VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000, and then VGA_BASE+offset is mapped to 0x90000e00_00000000+offset, where offset is the offset address, and its range is in the range of 0xA_0000 to 0xC_0000.

[0108] In some embodiments, the specific process of calling the x86 simulator to execute the VBIOS program may include: initializing the x86 simulator; and calling the x86 simulator to execute the VBIOS program.

[0109] Before reading the VBIOS program from the graphics card, the above method also includes: executing a PCIE scanning program via the processor, through which the device connected to the bridge chip via the PCIE bus can be scanned; if a graphics card is scanned, resources are allocated to the graphics card, graphics card firmware is loaded and the VBIOS program corresponding to the graphics card is read.

[0110] The allocated resources may include IO resources, memory resources, etc. Allocating resources to the graphics card includes configuring the above-mentioned address mapping relationship and configuring the PCIE bridge address.

[0111] In a specific embodiment, the terminal device is equipped with a CPU and an independent graphics card, and the CPU initializes the independent graphics card through the BIOS. After the CPU is powered on, it runs the BIOS. At a certain stage, a PCIE scanning program is executed to scan the PCIE devices connected to the bridge chip. Based on the analysis results of the device register identifier, the PCIE device type and required resources are determined. When the CPU scans the independent graphics card, IO resources and memory resources are allocated to the independent graphics card. Then, the CPU obtains the VBIOS program from the memory specified by the independent graphics card to initialize the independent graphics card. The graphics card initialization program is then executed to initialize the x86 simulator, load the VBIOS program, and call the x86 simulator to execute the instructions in the VBIOS program.

[0112] The solution of the present application fills the gap in accessing the VRAM space in the on-chip graphics card of the bridge during the BIOS stage, and improves the compatibility and selectivity of a CPU architecture with graphics cards of various architectures.

[0113] Figure 4 A schematic diagram of the structure of a video memory access device provided in one embodiment of the present application is shown in FIG. Figure 4 As shown, the video memory access device 400 of this embodiment may include: an instruction acquisition module 401 , a bridge address determination module 402 , and a to-be-operated data sending module 403 .

[0114] The instruction acquisition module 401 is used to obtain data operation instructions from the graphics card via the central processing unit. The data operation instructions include the data to be operated and the data address, where the data address is an address in the video random access memory (VRAM) space. The bridge chip address determination module 402 is used to determine the bridge chip address corresponding to the data address via the central processing unit using a preset address mapping relationship; the preset address mapping relationship includes a correspondence between VRAM space addresses and bridge chip addresses. The data to be operated transmission module 403 is used to transmit the data to be operated via the bridge chip, using the bridge chip address corresponding to the data address, to the address in the VRAM space corresponding to the data address.

[0115] Optionally, the video memory access device further includes:

[0116] A bridge chip address transmission module is used to determine the bridge chip address corresponding to the data address via a central processing unit using a preset address mapping relationship, and then send the bridge chip address to the hypertransport module of the bridge chip via a first hypertransport bus; the bridge chip address is mapped to a high-speed bus bridge address via the hypertransport module; wherein the high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is a part of the bridge chip and is a conversion component corresponding to the high-speed bus.

[0117] Correspondingly, the data to be operated sending module 403 is specifically configured to:

[0118] The data to be operated is sent to the VRAM space corresponding to the data address via the high-speed bus bridge and according to the high-speed bus bridge address.

[0119] Optionally, the high-speed bus is a PCIE bus, the high-speed bus bridge is a PCIE bridge, the high-speed bus bridge address is a PCIE bridge address, and the video memory access device further includes an address configuration module 404 for:

[0120] The central processing unit allocates a PCIE bridge address corresponding to the data address to the PCIE bridge according to the VRAM space address.

[0121] Correspondingly, the data to be operated sending module 403 is specifically configured to:

[0122] According to the bridge chip address corresponding to the data address and the PCIE bridge address corresponding to the data address, the data to be operated is sent to the address in the VRAM space corresponding to the data address.

[0123] Optionally, the address configuration module 404 is specifically configured to:

[0124] The base address register of the PCIE bridge is configured via the central processing unit so that the PCIE bridge address of the PCIE bridge corresponds to the address of the VRAM space.

[0125] Optionally, the instruction acquisition module 401 is specifically configured to:

[0126] The data operation instruction in the VBIOS program is read through the central processing unit; if the data operation instruction is an x86 instruction, the x86 simulator in the central processing unit is called to execute the data operation instruction to obtain the data to be operated and the VRAM space address corresponding to the data operation instruction.

[0127] Optionally, when the bridge address determining module 402 determines the bridge address corresponding to the data address by using a preset address mapping relationship, it is specifically configured to:

[0128] According to the preset address mapping relationship and the preset X1 Switch mapping, the bridge chip address corresponding to the data address is determined.

[0129] Optionally, the video memory access device further includes:

[0130] The program reading module 405 is used to read the data operation instructions in the VBIOS program from the graphics card via the central processing unit; the instruction processing module 406 is used to call the x86 simulator to execute the data operation instructions if the data operation instructions are x86 instructions, and obtain the data to be operated and the VRAM space address corresponding to the data operation instructions.

[0131] Optionally, when calling the x86 simulator to execute the VBIOS program, the instruction processing module 406 is specifically configured to:

[0132] Initialize the x86 simulator; call the x86 simulator to execute the VBIOS program.

[0133] Optionally, the video memory access device further includes:

[0134] The program reading module is used to execute the high-speed bus scanning program through the central processing unit to scan the devices connected to the bridge chip through the high-speed bus; if a graphics card is scanned, resources are allocated to the graphics card, graphics card firmware is loaded and the VBIOS program corresponding to the graphics card is read.

[0135] Optionally, the preset address mapping relationship includes: a correspondence between VRAM space addresses 0xA_0000 to 0xC_0000 and bridge chip addresses VGA_BASE+0xA_0000 to VGA_BASE+0xC_0000.

[0136] The device of this embodiment can be used to execute the method provided by any of the above embodiments. Its implementation principles and technical effects are similar and will not be described in detail here.

[0137] Figure 5 A schematic diagram of the structure of a computer system provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the computer system 500 of this embodiment may include: a central processing unit 510, a bridge chip 520 and an external component 530. The central processing unit 510 and the bridge chip 520 are connected via a first HyperTransport bus, and the bridge chip 520 and the external component 530 are connected via a high-speed bus; the external component 530 includes a graphics card 531, and the central processing unit 510 and the graphics card 531 are designed based on different types of architectures.

[0138] In some embodiments, the external component 530 may include multiple graphics cards, at least one of which has an architecture type different from that of the central processor 510 .

[0139] Among them, the central processing unit 510 is used to obtain data operation instructions from the graphics card 531, and the data operation instructions include the data to be operated and the data address, and the data address is the address in the image random access memory VRAM space; and uses the preset address mapping relationship to determine the bridge chip address corresponding to the data address; wherein the preset address mapping relationship includes the correspondence between the VRAM space address and the bridge chip address; the bridge chip 520 is used to send the data to be operated to the address in the VRAM space corresponding to the data address through the bridge chip address to access the graphics card 531.

[0140] The graphics card 531 can be a discrete graphics card designed based on the x86 architecture. The central processing unit 510 and the bridge chip 520 are designed based on a non-x86 architecture. To be compatible with the x86-based graphics card 531, the central processing unit 510 and the bridge chip 520 execute the method provided in any of the above embodiments to access the VRAM space of the graphics card 531, thereby initializing the graphics card 531.

[0141] Figure 6A schematic diagram of another computer system provided in an embodiment of the present application, combined with Figure 5 and Figure 6 The central processing unit 510 of the computer system 500 provided in this embodiment includes a cross-mapping module. The central processing unit 510 is connected to the bridge chip 520 through the first HyperTransport HT1 bus. The bridge chip 520 includes a HyperTransport HT module, a PCIE bridge and other modules. The bridge chip 520 is connected to the graphics card 531 through the PCIE bus.

[0142] The CPU 510 can configure a cross-mapping module to establish a correspondence between the VRAM space and the bridge chip address, thereby obtaining the aforementioned address mapping relationship. When the CPU 510 obtains a data operation instruction to access the graphics card 531, it uses this address mapping relationship to obtain the corresponding bridge chip address, thereby sending the data operation instruction to the bridge chip via the HT1 bus.

[0143] Taking the central processing unit 510 as a 3A3000 processor as an example, addresses in the address range 0x90000e00_00000000 to 0x90000eff_ffffffff can be sent to the downstream device, i.e., the bridge chip, via the HT1 bus, and addresses in other ranges can be sent to other devices via other buses, such as the HT0 bus.

[0144] The HT module of the bridge chip 520 forwards the bridge chip address and its corresponding data to be operated from the HT1 bus to the PCIE bridge of the bridge chip, so that the PCIE bridge sends its corresponding data to be operated to the device corresponding to the bridge chip address based on the bridge chip address, that is, the device receiving the bridge chip address, that is, the graphics card 430.

[0145] Specifically, after passing through the HT1 bus, the bridge address is converted, for example, from 0x90000e00_000a0000 to 0x90000e00_000c0000 to 0x00_000a0000 to 0x00_000c0000, or 0xa_0000 to 0xc_0000. The PCIE bridge is responsible for sending addresses in the range of 0xa_0000 to 0xc_0000 to the corresponding device, i.e., the graphics card 531.

[0146] The central processing unit 510 can pre-configure a PCIE bridge for the VRAM space of the graphics card 531. By modifying the base address register of the PCIE bridge, the PCIE bridge can receive access operations of the address segment 0xa_0000 to 0xc_0000, thereby sending the access operations corresponding to this address segment to the device that can receive access operations of this address segment, that is, the above-mentioned graphics card 430.

[0147] The central processing unit 510 can also restore the PCIE address of the PCIE bridge after the PCIE bridge sends the pending operation data corresponding to the PCIE bridge address to the VRAM space corresponding to the graphics card 531, that is, restore the address segment 0xa_0000~0xc_0000 in the PCIE bridge to the original mapping relationship, so that after the graphics card 531 is initialized, it will not affect other devices accessing this address segment.

[0148] The computer system 500 of this embodiment can be used to execute the method provided by any of the above embodiments. The implementation principles and technical effects are similar and will not be described in detail here.

[0149] The computer system 500 of this embodiment may be a computer system of a terminal device such as a computer, a mobile phone, or a tablet computer.

[0150] The present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a central processing unit, the method provided in any of the above embodiments is implemented.

[0151] The present application also provides a computer program product, including a computer program, which implements the method provided in any of the above embodiments when executed by a central processing unit.

[0152] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A video memory access method, characterized in that: The method is applied to a computer system, the computer system comprising at least a central processing unit (CPU), a bridge chip, and external components, wherein the CPU and the bridge chip are connected via a first HyperTransport bus, and the bridge chip and the external components are connected via a high-speed bus; the external components include a graphics card, the graphics card includes video memory, and the CPU and the graphics card are designed based on different types of architectures; the method comprises: During a BIOS phase of the computer system, the CPU obtains a data operation instruction from a graphics card, wherein the data operation instruction includes data to be operated and a data address, and the data address is an address in a video random access memory (VRAM) space of the video memory; Determining, by the CPU, a bridge chip address corresponding to the data address using a preset address mapping relationship; wherein the preset address mapping relationship includes a correspondence between a VRAM space address and a bridge chip address; sending the bridge chip address to the HyperTransport module of the bridge chip via a first HyperTransport bus; Mapping the bridge chip address to a high-speed bus bridge address via the hypertransport module; wherein the high-speed bus bridge address is the address of the high-speed bus bridge; and the high-speed bus bridge is a conversion component corresponding to the high-speed bus; The data to be operated is sent to an address in the VRAM space corresponding to the data address via the high-speed bus bridge and according to the high-speed bus bridge address.

2. The method according to claim 1, characterized in that The high-speed bus is a PCIE bus, the high-speed bus bridge is a PCIE bridge, the high-speed bus bridge address is a PCIE bridge address, and the method further includes: The CPU configures a base address register of the PCIE bridge so that a PCIE bridge address of the PCIE bridge corresponds to an address of a VRAM space.

3. The method according to claim 1 or 2, characterized in that Obtain data operation instructions from the graphics card via the CPU, including: Read the data operation instructions in the VBIOS program through the CPU; If the data operation instruction is an x86 instruction, the x86 simulator in the CPU is called to execute the data operation instruction to obtain the data to be operated and the VRAM space address corresponding to the data operation instruction.

4. The method according to claim 3, characterized in that Also includes: Executing a high-speed bus scanning program via the CPU to scan devices connected to the bridge chip via the high-speed bus; If a graphics card is scanned, the graphics card is loaded and a VBIOS program corresponding to the graphics card is read, so that the initialization configuration instructions in the VBIOS program are read by the CPU.

5. A video memory access device, characterized in that: Applicable to a computer system, the computer system comprising at least a central processing unit (CPU), a bridge chip, and external components, wherein the CPU and the bridge chip are connected via a first HyperTransport bus, and the bridge chip and the external components are connected via a high-speed bus; the external components include a graphics card, and the CPU and the graphics card are designed based on different types of architectures; including: An instruction acquisition module is used to acquire a data operation instruction of a graphics card via the CPU, wherein the data operation instruction includes data to be operated and a data address, wherein the data address is a video random access memory (VRAM) space address; a bridge chip address determination module, configured to determine, via the CPU, a bridge chip address corresponding to the data address using a preset address mapping relationship; wherein the preset address mapping relationship includes a correspondence between a VRAM space address and a bridge chip address; a bridge chip address transmission module, configured to transmit the bridge chip address to the HyperTransport module of the bridge chip via a first HyperTransport bus; Mapping the bridge chip address to a high-speed bus bridge address via the hypertransport module, wherein the high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is a conversion component corresponding to the high-speed bus; The module for sending data to be operated is used to send the data to be operated to the VRAM space corresponding to the data address through the high-speed bus bridge according to the high-speed bus bridge address.

6. The device according to claim 5, characterized in that The high-speed bus is a PCIE bus, the high-speed bus bridge is a PCIE bridge, the high-speed bus bridge address is a PCIE bridge address, and the device further includes: The address configuration module is used to configure the base address register of the PCIE bridge via the CPU so that the PCIE bridge address of the PCIE bridge corresponds to the address of the VRAM space.

7. The device according to claim 5 or 6, characterized in that The instruction acquisition module is specifically used to: Reading data operation instructions in the VBIOS program via the CPU; If the data operation instruction is an x86 instruction, the x86 simulator in the CPU is called to execute the data operation instruction to obtain the data to be operated and the VRAM space address corresponding to the data operation instruction.

8. A computer system, characterized in that: include: A central processing unit (CPU), a bridge chip, and external components, wherein the CPU and the bridge chip are connected via a first HyperTransport bus, and the bridge chip and the external components are connected via a high-speed bus; the external components include a graphics card, and the CPU and the graphics card are designed based on different types of architectures; The CPU is configured to obtain a data operation instruction from the graphics card, the data operation instruction including data to be operated and a data address, the data address being a video random access memory (VRAM) space address; and determine a bridge chip address corresponding to the data address using a preset address mapping relationship; wherein the preset address mapping relationship includes a correspondence between the VRAM space address and the bridge chip address; sending the bridge chip address to the HyperTransport module of the bridge chip via a first HyperTransport bus; Mapping the bridge chip address to a high-speed bus bridge address via the hypertransport module, wherein the high-speed bus bridge address is the address of the high-speed bus bridge; the high-speed bus bridge is a conversion component corresponding to the high-speed bus; The data to be operated is sent to the VRAM space corresponding to the data address via the high-speed bus bridge and according to the high-speed bus bridge address.

9. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a central processing unit, the method according to any one of claims 1 to 4 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a central processing unit, the method according to any one of claims 1 to 4 is implemented.

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