Shift register, gate drive circuit, display substrate and display device

Abstract

This disclosure provides a shift register unit, including: a first precharge reset circuit configured to precharge and reset a first pull-up node; a first pull-down control circuit configured to control the voltage at the first pull-down node; a first drive output circuit configured to write a signal provided by a first clock signal input terminal to a first drive output terminal in response to a valid level signal at the first pull-up node, and to write a voltage provided by a fifth power supply terminal to the first drive output terminal in response to a valid level signal at the first pull-down node; and a first output reset circuit configured to write a voltage provided by a fifth power supply terminal to the first drive output terminal in response to a valid level signal provided by a first reset signal input terminal. Embodiments of this disclosure also provide a gate drive circuit, a display substrate, a display device, and a gate drive method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display, in particular to a shift register, a gate driving circuit, a display substrate, a display device and a gate driving method. BACKGROUND

[0002] With the development trend of high integration of display panels, GOA (Gae Driver On Array) technology appears, which directly integrates the gate driving circuit on the array substrate to replace the external driving chip, and has the advantages of low cost, fewer processes, high production capacity, etc.

[0003] The gate driving circuit generally includes a plurality of cascaded shift register units. Since the driving signal at the output of each shift register unit is in an effective level state for a short time within a frame time, noise reduction processing needs to be performed on the driving output end of the shift register unit after the shift register unit outputs the driving signal. SUMMARY

[0004] In a first aspect, the embodiments of the present disclosure provide a shift register unit, comprising:

[0005] A first pre-charge reset circuit is connected with a first cascaded signal input end, a first reset signal input end, a first power supply end, a second power supply end, and a first pull-up node, and is configured to write a voltage provided by the first power supply end to the first pull-up node in response to a control of an effective level signal provided by the first cascaded signal input end, and write a voltage provided by the second power supply end to the first pull-up node in response to a control of an effective level signal provided by the first reset signal input end;

[0006] A first pull-down control circuit is connected with the first pull-up node, a first pull-down node, the second power supply end, a third power supply end, and a fourth power supply end, and is configured to write an effective level signal to the first pull-down node when the third power supply end provides an effective level signal and the voltage at the first pull-up node is in a non-effective level state, and write a non-effective level signal to the first pull-down node when the fourth power supply end provides an effective level signal or when the first pull-up node is in an effective level state;

[0007] A first driving output circuit is connected with the first pull-up node, the first pull-down node, a first clock signal input end, a fifth power supply end, and a first driving output end, and is configured to write a signal provided by the first clock signal input end to the first driving output end in response to a control of an effective level signal at the first pull-up node, and write a voltage provided by the fifth power supply end to the first driving output end in response to a control of an effective level signal at the first pull-down node;

[0008] The first output reset circuit is connected with the first reset signal input end, the fifth power supply end and the first drive output end, and is configured to write the voltage provided by the fifth power supply end to the first drive output end in response to the control of the valid level signal provided by the first reset signal input end.

[0009] Optionally, the shift register unit further comprises:

[0010] The first cascade output circuit is connected with the first pull-up node, the first pull-down node, the first clock signal input end, the second power supply end and the first cascade output end, and is configured to write the signal provided by the first clock signal input end to the first cascade output end in response to the control of the valid level signal at the first pull-up node, and write the voltage provided by the fifth power supply end to the first cascade output end in response to the control of the valid level signal at the first pull-down node.

[0011] Optionally, the second power supply end is insulated from the fifth power supply end.

[0012] Optionally, the shift register unit further comprises:

[0013] The second pre-charge reset circuit is connected with the second cascade signal input end, the second reset signal input end, the first power supply end, the second power supply end and the second pull-up node, and is configured to write the voltage provided by the first power supply end to the second pull-up node in response to the control of the valid level signal provided by the second cascade signal input end, and write the voltage provided by the second power supply end to the second pull-up node in response to the control of the valid level signal provided by the second reset signal input end.

[0014] The second pull-down control circuit is connected with the second pull-up node, the second pull-down node, the second power supply end, the third power supply end and the fourth power supply end, and is configured to write the valid level signal to the second pull-down node when the fourth power supply end provides the valid level signal and the voltage at the second pull-up node is in the non-valid level state, and write the non-valid level signal to the second pull-down node when the third power supply end provides the valid level signal or when the second pull-up node is in the valid level state.

[0015] The second drive output circuit is connected with the second pull-up node, the second pull-down node, the second clock signal input end, the fifth power supply end and the second drive output end, and is configured to write the signal provided by the second clock signal input end to the second drive output end in response to the control of the valid level signal at the second pull-up node, and write the voltage provided by the fifth power supply end to the second drive output end in response to the control of the valid level signal at the second pull-down node.

[0016] The second output reset circuit is connected with the second reset signal input end, the fifth power supply end and the second drive output end, and is configured to write the voltage provided by the fifth power supply end to the second drive output end in response to the control of the valid level signal provided by the second reset signal input end.

[0017] Optionally, the shift register unit further comprises:

[0018] The first cascade output circuit is connected with the first pull-up node, the first pull-down node, the first clock signal input end, the second power supply end and the first cascade output end, and is configured to write the signal provided by the first clock signal input end to the first cascade output end in response to the control of the valid level signal at the first pull-up node, and write the voltage provided by the fifth power supply end to the first cascade output end in response to the control of the valid level signal at the first pull-down node.

[0019] The second cascade output circuit is connected with the second pull-up node, the second pull-down node, the second clock signal input end, the second power supply end and the second cascade output end, and is configured to write the signal provided by the second clock signal input end to the second cascade output end in response to the control of the valid level signal at the second pull-up node, and write the voltage provided by the fifth power supply end to the first cascade output end in response to the control of the valid level signal at the second pull-down node.

[0020] The first cascade output end is connected with the second cascade signal input end, and the second cascade output end is connected with the first reset signal input end.

[0021] Optionally, the first pull-down control circuit is further connected with the second pull-up node, and the first pull-down control circuit comprises:

[0022] The first control sub-circuit is connected with the first pull-up node, the second pull-up node, the first pull-down control node, the second power supply end and the third power supply end, and is configured to write the voltage provided by the second power supply end to the first pull-down control node when at least one of the voltage at the first pull-up node and the voltage at the second pull-up node is in a valid level state, and write the valid level signal to the first pull-down control node when the voltage at the first pull-up node and the voltage at the second pull-up node are both in a non-valid level state and the third power supply end provides a valid level signal.

[0023] The second control sub-circuit is connected with the first pull-down control node, the first pull-up node, the second pull-up node, the first pull-down node, the second power supply end and the third power supply end, and is configured to write a valid level signal to the first pull-down node when the voltage at the first pull-down control node is in a valid level state, and write the voltage provided by the second power supply end to the first pull-down node when at least one of the voltage at the first pull-up node and the voltage at the second pull-up node is in a valid level state;

[0024] The third control sub-circuit is connected with the first pull-down node, the second power supply end and the fourth power supply end, and is configured to write the voltage provided by the second power supply end to the first pull-down node when the fourth power supply end provides a valid level signal.

[0025] The second pull-down control circuit is further connected with the first pull-up node, and the second pull-down control circuit comprises:

[0026] The fourth control sub-circuit is connected with the first pull-up node, the second pull-up node, the second pull-down control node, the second power supply end and the fourth power supply end, and is configured to write the voltage provided by the second power supply end to the second pull-down control node when at least one of the voltage at the first pull-up node and the voltage at the second pull-up node is in a valid level state, and write a valid level signal to the second pull-down control node when the voltage at the first pull-up node and the voltage at the second pull-up node are both in a non-valid level state and the fourth power supply end provides a valid level signal.

[0027] The fifth control sub-circuit is connected with the second pull-down control node, the first pull-up node, the second pull-up node, the second pull-down node, the second power supply end and the fourth power supply end, and is configured to write a valid level signal to the second pull-down node when the voltage at the second pull-down control node is in a valid level state, and write the voltage provided by the second power supply end to the second pull-down node when at least one of the voltage at the first pull-up node and the voltage at the second pull-up node is in a valid level state.

[0028] The sixth control sub-circuit is connected with the second pull-down node, the second power supply end and the third power supply end, and is configured to write the voltage provided by the second power supply end to the second pull-down node when the third power supply end provides a valid level signal.

[0029] Optionally, the first drive output circuit is further connected with the second pull-down node, and the first drive output circuit is further configured to write the voltage provided by the fifth power supply end to the first drive output end in response to the control of the valid level signal at the second pull-down node.

[0030] The second drive output circuit is also connected with the first pull-down node, and the second drive output circuit is configured to write the voltage provided by the fifth power supply end to the second drive output end in response to the control of the valid level signal at the first pull-down node.

[0031] Optionally, the first output reset circuit comprises a fourth transistor.

[0032] The control electrode of the fourth transistor is connected with the first reset signal input end, the first electrode of the fourth transistor is connected with the first drive output end, and the second electrode of the fourth transistor is connected with the fifth power supply end.

[0033] In a second aspect, the embodiments of the present disclosure further provide a gate drive method based on a shift register unit, wherein the shift register unit is the shift register unit provided in the first aspect, and the gate drive method comprises the following steps:

[0034] In the pre-charging stage, the first pre-charging reset circuit writes the voltage provided by the first power supply end to the first pull-up node in response to the control of the valid level signal provided by the first cascade signal input end, so as to pre-charge the first pull-up node;

[0035] In the output stage, the first drive output circuit writes the signal provided by the first clock signal input end to the first drive output end in response to the control of the valid level signal at the first pull-up node;

[0036] In the reset stage, the first pre-charging reset circuit writes the voltage provided by the second power supply end to the first pull-up node in response to the control of the valid level signal provided by the first reset signal input end, so as to reset the first pull-up node, and the first output reset circuit writes the voltage provided by the fifth power supply end to the first drive output end in response to the control of the valid level signal provided by the first reset signal input end, so as to reset the first drive output end;

[0037] In the noise reduction stage, the first pull-down control circuit writes the valid level signal to the first pull-down node when the third power supply end provides the valid level signal and the voltage at the first pull-up node is in the non-valid level state, and writes the non-valid level signal to the first pull-down node when the fourth power supply end provides the valid level signal.

[0038] In a third aspect, the embodiments of the present disclosure further provide a gate drive circuit, comprising: a plurality of cascaded shift register units, at least one of the shift register units being the shift register unit provided in the first aspect.

[0039] In a fourth aspect, the display substrate is provided by the display substrate provided in the third aspect.

[0040] In a fifth aspect, the display substrate is provided by the display substrate provided in the fourth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A circuit structure diagram of a shift register unit involved in the related art;

[0042] Figure 2 A working timing diagram of the shift register unit involved in the related art in an ideal state;

[0043] Figure 3 A working timing diagram of the shift register unit involved in the related art in an actual working state;

[0044] Figure 4 A comparison diagram of the timing corresponding to the pull-up node and the driving output end of the shift register unit involved in the related art in the ideal state and the actual working state;

[0045] Figure 5 A circuit structure diagram of a shift register unit provided by the embodiments of the present disclosure;

[0046] Figure 6 Another circuit structure diagram of a shift register unit provided by the embodiments of the present disclosure;

[0047] Figure 7 A working timing diagram of the shift register unit shown in FIG. 10; Figure 6

[0048] Another circuit structure diagram of a shift register unit provided by the embodiments of the present disclosure; Figure 8

[0049] Still another circuit structure diagram of a shift register unit provided by the embodiments of the present disclosure; Figure 9

[0050] Still another circuit structure diagram of a shift register unit provided by the embodiments of the present disclosure; Figure 10

[0051] Still another circuit structure diagram of a shift register unit provided by the embodiments of the present disclosure; Figure 11

[0052] A working timing diagram of the shift register unit shown in FIG. 11; Figure 12 Figure 11 A working timing diagram of the shift register unit shown in FIG. 11;​

[0053] Figure 13 A circuit structure schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure is shown in FIG. 1.

[0054] Figure 14 A circuit structure schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure is shown in FIG. 1.

[0055] Figure 15 A flow chart of a gate drive method provided by an embodiment of the present disclosure is shown in FIG. 4. DETAILED DESCRIPTION

[0056] In order for those skilled in the art to better understand the technical solutions of the present application, the shift register, the gate drive circuit, the display substrate, the display device and the gate drive method provided by the present application are described in detail below with reference to the drawings.

[0057] The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. Similarly, the terms "comprise" or "include" and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical coupling, but can include electrical coupling, whether direct or indirect.

[0058] The transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments, the coupling mode of the drain and the source of each transistor can be interchangeable, so the drain and the source of each transistor in the embodiments of the present disclosure are actually indistinguishable. Here, only to distinguish the two poles of the transistor other than the control pole (i.e. the gate), one pole is called the drain and the other pole is called the source. The thin film transistors used in the embodiments of the present disclosure can be N-type transistors or P-type transistors. In the embodiments of the present disclosure, when N-type thin film transistors are used, the first pole can be the source and the second pole can be the drain. The "effective level" in the present disclosure refers to the level that can control the conduction of the corresponding transistor, and the "non-effective level" in the present disclosure refers to the level that can control the cut-off of the corresponding transistor. For N-type transistors, the effective level is high and the non-effective level is low; for P-type transistors, the effective level is low and the non-effective level is high. In the following embodiments, N-type thin film transistors are taken as an example for description, i.e. when the signal of the control pole is high, the thin film transistor is turned on; it can be conceived that when P-type transistors are used, the timing change of the drive signal needs to be adjusted accordingly. The specific details are not described here, but should be within the protection scope of the present disclosure.

[0059] In the related art, in order to realize the noise reduction of the driving output end of the shift register unit, a pull-down control circuit and a pull-down node are generally arranged inside the shift register. The pull-down control circuit can adjust the potential of the pull-down node, and the driving output circuit can write a non-active level signal into the driving output end in response to the control of the pull-down node to reduce the noise of the driving output end. However, in actual application, it is found that after the driving output end outputs a driving signal, the pull-down node is controlled by the pull-down control circuit to maintain an active level state, so that the driving output circuit continuously writes a non-active level signal into the driving output end. Although this technical means achieves the purpose of reducing the noise of the driving output end, the transistor (hereinafter referred to as "noise reduction transistor") connected between the control electrode in the driving output circuit and the pull-down node will be in a high-voltage conduction state for a long time, which will cause the electrical characteristics of the noise reduction transistor to drift seriously, and the service life of the noise reduction transistor will be greatly reduced.

[0060] In order to solve the problem that the service life of the noise reduction transistor is reduced due to the long time of the noise reduction transistor in the high-voltage conduction state, the pull-down control circuit is improved in the related art, that is, the pull-down control circuit alternately writes an active level signal and a non-active level signal into the pull-down node after the driving output end outputs a driving signal. When the pull-down control circuit writes an active level signal into the pull-down node, the noise reduction transistor is turned on and writes a non-active level signal into the driving output end to achieve the purpose of reducing the noise of the driving output end. When the pull-down control circuit writes a non-active level signal into the pull-down node, the noise reduction transistor is switched to an off state. In this way, the noise reduction of the driving output end can be realized while avoiding the long time of the noise reduction transistor in the high-voltage conduction state. However, this technical solution of alternately writing an active level signal and a non-active level signal into the pull-down node by the pull-down control circuit brings new technical problems in actual application.

[0061] Figure 1 A circuit structure diagram of a shift register unit involved in the related art, Figure 2 A working timing diagram of a shift register unit involved in the related art in an ideal state, as shown in Figure 1 and Figure 2 The shift register unit involved in the related art includes a pre-charge reset circuit, a pull-down control circuit and a driving output circuit. The pre-charge reset circuit is connected with a pull-up node PU, the pull-down control circuit is connected with the pull-up node PU and a pull-down node PD, the driving output circuit is connected with the pull-up node PU, the pull-down node PD, a clock signal input end and a driving output end OUTPUT, and the driving output circuit is provided with an output transistor MO, a noise reduction transistor MD and a capacitor C. Taking the output transistor MO and the noise reduction transistor MD as N-type transistors as an example.

[0062] The working process of the shift register unit generally includes a pre-charge phase t_1, an output phase t_2, a reset phase t_3 and a noise reduction phase t_4. In the pre-charge phase t_1, the pre-charge reset circuit pre-charges the pull-up node PU, so that the pull-up node PU is in a high level state, at this time the output transistor MO is turned on, and the output transistor MO writes the low level signal provided by the clock signal input end CLK to the driving output end OUTPUT; in the output phase t_2, the clock signal input end CLK first provides a high level signal, and then provides a low level signal, wherein when the clock signal input end CLK first provides a high level signal, the output transistor MO writes the high level signal provided by the clock signal input end CLK to the driving output end OUTPUT, and the driving output end OUTPUT outputs a driving signal in a high level state, at this time the voltage at the pull-up node PU is pulled up to a higher level due to the bootstrap effect of the capacitor C, and when the clock signal input end CLK provides a low level, the output transistor MO writes the low level signal provided by the clock signal input end CLK to the driving output end OUTPUT, and the driving output end OUTPUT outputs a low level signal. In the reset phase t_3, the pre-charge reset circuit resets the pull-up node PU, so that the pull-up node PU is in a low level state, at this time the output transistor MO is cut off, and the pull-down control circuit also maintains the pull-down node PD in a low level state, and the noise reduction transistor is also cut off, and the driving output end OUTPUT is in a floating state to maintain a low level; in the noise reduction phase t_4, the pull-down control circuit controls the voltage at the pull-down node PD to switch between high level and low level to control the noise reduction transistor to switch between on and off states, and when the noise reduction transistor is in the on state, the low level voltage can be written to the driving output end OUTPUT to reduce the noise of the driving output end OUTPUT.

[0063] Figure 3 For a working timing diagram of the shift register unit involved in the related art in the actual working state, Figure 4 For a comparison diagram of the pull-up node and the driving output end corresponding to the timing in the related art shift register unit in the ideal state and the actual working state, as shown in Figure 3 and Figure 4 In the actual working process of the shift register unit involved in the related art, during the output phase t_2 and when the clock signal input end CLK provides a high level signal, the voltage at the pull-up node PU is high due to the bootstrap effect of the capacitor C, and because the pull-up node PU is connected to a large number of transistors, there is obvious leakage at the pull-up node PU at this time, which causes the voltage at the pull-up node PU to drop.

[0064] Assuming that the voltage at the pull-up node PU is VGH at the pre-charge node, the high level signal and the low level signal provided by the clock signal input terminal CLK correspond to the voltages VGH and VGL respectively, at the initial moment of the output stage t_2 and the clock signal input terminal CLK providing the high level signal, the voltage at the pull-up node PU will be pulled up to the level of 2*VGH-VGL. Assuming that the voltage drop △V at the pull-up node PU due to the leakage current in the period of the clock signal input terminal CLK providing the high level signal, at the end of the output stage t_2, the voltage at the pull-up node PU is 2*VGH-VGL-△V. Thereafter, the clock signal input terminal CLK is switched from providing the high level signal to providing the low level signal, and the voltage of the driving output terminal OUTPUT starts to drop, under the action of the capacitor C, the voltage at the pull-up node PU will also be pulled down, wherein the voltage at the pull-up node PU will be pulled down to the level of VGH first, and then continue to drop. In theory, when the voltage of the driving output terminal OUTPUT drops from VGH to VGL, the voltage at the pull-up node PU will be pulled down from 2*VGH-VGL-△V to VGH-△V. However, when△V is too large and VGH-△V is less than VGL+Vth (Vth is the threshold voltage of the output transistor MO, Vth≥0), then the output transistor MO will be in the off state after the voltage at the pull-up node PU drops from 2*VGH-VGL-△V to VGL+Vth, and the voltage of the driving output terminal OUTPUT at this time is 2*VGL-VGH+△V+Vth, since VGH-△V<VGL+Vth, 2*VGL-VGH+△V+Vth>VGL.

[0065] That is, at the end of the output stage t_2 and in the reset stage t_3, the voltage of the driving output terminal OUTPUT will be in a state greater than VGL, specifically equal to 2*VGL-VGH+△V+Vth, and the larger△V is, the larger 2*VGL-VGH+△V+Vth is. As can be seen, when the leakage current is too large, making△V too large, there is a risk that the driving output terminal OUTPUT outputs a high level voltage (lower than VGH, but higher than the threshold voltage of some transistors connected to the control electrode and the driving output terminal OUTPUT) in the reset stage t_3, thereby causing the shift register unit to be overcharged in the reset stage t_3.

[0066] To effectively improve the above technical problems, the technical scheme of the present disclosure provides a corresponding solution. Figure 5 A circuit structure diagram of a shift register unit provided by an embodiment of the present disclosure is shown in Figure 5 As shown, the shift register unit comprises a first pre-charge reset circuit 1, a first pull-down control circuit 2, a first driving output circuit 3 and a first output reset circuit 4.

[0067] The first pre-charge reset circuit 1 is connected with the first cascaded signal input end INPUT1, the first reset signal input end RST1, the first power supply end, the second power supply end, and the first pull-up node PU1. The first pre-charge reset circuit 1 is configured to write the voltage provided by the first power supply end to the first pull-up node PU1 in response to the control of the effective level signal provided by the first cascaded signal input end INPUT1, and write the voltage provided by the second power supply end to the first pull-up node PU1 in response to the control of the effective level signal provided by the first reset signal input end RST1.

[0068] The first pull-down control circuit 2 is connected with the first pull-up node PU1, the first pull-down node PD1, the second power supply end, the third power supply end, and the fourth power supply end. The first pull-down control circuit 2 is configured to write the effective level signal to the first pull-down node PD1 when the third power supply end provides the effective level signal and the voltage at the first pull-up node PU1 is in the non-effective level state, and write the non-effective level signal to the first pull-down node PD1 when the fourth power supply end provides the effective level signal or when the first pull-up node PU1 is in the effective level state.

[0069] The first drive output circuit 3 is connected with the first pull-up node PU1, the first pull-down node PD1, the first clock signal input end, the fifth power supply end, and the first drive output end OUTPUT1. The first drive output circuit 3 is configured to write the signal provided by the first clock signal input end to the first drive output end OUTPUT1 in response to the control of the effective level signal at the first pull-up node PU1, and write the voltage provided by the fifth power supply end to the first drive output end OUTPUT1 in response to the control of the effective level signal at the first pull-down node PD1.

[0070] The first output reset circuit 4 is connected with the first reset signal input end RST1, the fifth power supply end, and the first drive output end OUTPUT1. The first output reset circuit 4 is configured to write the voltage provided by the fifth power supply end to the first drive output end OUTPUT1 in response to the control of the effective level signal provided by the first reset signal input end RST1.

[0071] Similar to the working process of the shift register unit in the related art, the working process of the shift register unit provided by the embodiment of the present disclosure also includes a pre-charge phase t_1, an output phase t_2, a reset phase t_3, and a noise reduction phase t_4.

[0072] In the pre-charge phase t_1, the first pre-charge reset circuit 1 writes the voltage provided by the first power supply end to the first pull-up node PU1 in response to the control of the effective level signal provided by the first cascaded signal input end INPUT1, so as to pre-charge the first pull-up node PU1.

[0073] In the output stage t_2, the first driving output circuit 3 writes the signal provided by the first clock signal input end to the first driving output end OUTPUT1 in response to the control of the valid level signal at the first pull-up node PU1.

[0074] In the reset stage t_3, the first pre-charge reset circuit 1 writes the voltage provided by the second power supply end to the first pull-up node PU1 in response to the control of the valid level signal provided by the first reset signal input end RST1, so as to reset the first pull-up node PU1, and the first output reset circuit 4 writes the voltage provided by the fifth power supply end to the first driving output end OUTPUT1 in response to the control of the valid level signal provided by the first reset signal input end RST1, so as to reset the first driving output end OUTPUT1.

[0075] In the noise reduction stage t_4, the first pull-down control circuit 2 writes the valid level signal to the first pull-down node PD1 when the third power supply end provides the valid level signal and the voltage at the first pull-up node PU1 is in the non-valid level state, and writes the non-valid level signal to the first pull-down node PD1 when the fourth power supply end provides the valid level signal.

[0076] In the embodiments of the present disclosure, in the case that the first pull-down control circuit 2 capable of alternately outputting the valid level signal and the non-valid level signal to the pull-down node is arranged in the shift register unit, the first output reset circuit 4 is additionally arranged, and the voltage provided by the fifth power supply end (the voltage VGL2 provided by the fifth power supply end) is written to the first driving output end OUTPUT1 by the first output reset circuit 4 in the reset stage t_3, so as to reset the first driving output end OUTPUT1, so that the voltage of the first driving output end OUTPUT1 can quickly reach VGL2 after entering the reset stage t_3, thereby avoiding the problem of incorrect charging of the shift register unit in the reset stage t_3.

[0077] In some embodiments, the first output reset circuit 4 comprises a fourth transistor M4, the control electrode of the fourth transistor M4 is connected with the first reset signal input end RST1, the first electrode of the fourth transistor M4 is connected with the first driving output end OUTPUT1, and the second electrode of the fourth transistor M4 is connected with the fifth power supply end.

[0078] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the following will make a detailed description in combination with specific examples. In the examples, the first power supply end provides a high level voltage VGH1, the second power supply end provides a low level voltage VGL1, the third power supply end provides a voltage V3, the fourth power supply end provides a voltage V4, and the fifth power supply end provides a low level voltage VGL2. In the examples, V3 and V4 alternately provide a high level voltage, and VGL2≤VGL1≤0V.

[0079] Optionally, the second power terminal and the fifth power terminal are insulated, and VGL2 is less than VGL1; further optionally, 0V < VGL1-VGL2≤2V, for example, VGL1 is -8V, and VGL2 is -10V.

[0080] Figure 6 Another circuit structure diagram of the shift register unit provided by the embodiments of the present disclosure is shown in FIG. 6. Figure 6 Figure 6 The shift register unit shown in FIG. 6 is based on a specific implementation of the shift register unit shown in FIG. 5. Figure 5 The shift register unit shown in FIG. 6 is based on a specific implementation of the shift register unit shown in FIG. 5.

[0081] In some embodiments, the first pre-charge reset circuit 1 includes a first transistor M1 and a second transistor M2.

[0082] The control electrode of the first transistor M1 is connected with the first cascade signal input terminal INPUT1, the first electrode of the first transistor M1 is connected with the first power terminal, and the second electrode of the first transistor M1 is connected with the first pull-up node PU1.

[0083] The control electrode of the second transistor M2 is connected with the first reset signal input terminal RST1, the first electrode of the second transistor M2 is connected with the first pull-up node PU1, and the second electrode of the second transistor M2 is connected with the second power terminal.

[0084] The first pull-down control circuit 2 includes a first control sub-circuit 201, a second control sub-circuit 202, and a third control sub-circuit 203.

[0085] The first control sub-circuit 201 is connected with the first pull-up node PU1, the first pull-down control node PNC1, the second power terminal, and the third power terminal, and is configured to write the voltage provided by the second power terminal to the first pull-down control node PNC1 when the voltage at the first pull-up node PU1 is at an effective level, and write an effective level signal to the first pull-down control node PNC1 when the voltages at the first pull-up node PU1 are all at a non-effective level and the third power terminal provides an effective level signal.

[0086] The second control sub-circuit 202 is connected with the first pull-down control node PNC1, the first pull-up node PU1, the first pull-down node PD1, the second power terminal, and the third power terminal, and is configured to write an effective level signal to the first pull-down node PD1 when the voltage at the first pull-down control node PNC1 is at an effective level, and write the voltage provided by the second power terminal to the first pull-down node PD1 when the voltage at the first pull-up node PU1 is at an effective level.

[0087] ​The third control sub-circuit 203 is connected with the first pull-down node PD1, the second power supply end and the fourth power supply end, and is configured to write the voltage provided by the second power supply end to the first pull-down node PD1 when an effective level signal is provided at the fourth power supply end.

[0088] In some embodiments, the first control sub-circuit 201 includes an eighth transistor M8 and a ninth transistor M9, the second control sub-circuit 202 includes a tenth transistor M10 and an eleventh transistor M11, and the third control sub-circuit 203 includes a twelfth transistor M12.

[0089] The control electrode and the first electrode of the eighth transistor M8 are connected with the third power supply end, and the second electrode of the eighth transistor M8 is connected with the first pull-down control node PNC1.

[0090] The control electrode of the ninth transistor M9 is connected with the first pull-up node PU1, the first electrode of the ninth transistor M9 is connected with the first pull-down control node PNC1, and the second electrode of the ninth transistor M9 is connected with the second power supply end.

[0091] The control electrode of the tenth transistor M10 is connected with the first pull-down control node PNC1, the first electrode of the tenth transistor M10 is connected with the third power supply end, and the second electrode of the tenth transistor M10 is connected with the first pull-down node PD1.

[0092] The control electrode of the eleventh transistor M11 is connected with the first pull-up node PU1, the first electrode of the eleventh transistor M11 is connected with the first pull-down node PD1, and the second electrode of the eleventh transistor M11 is connected with the second power supply end.

[0093] The control electrode of the twelfth transistor M12 is connected with the fourth power supply end, the first electrode of the twelfth transistor M12 is connected with the first pull-down node PD1, and the second electrode of the twelfth transistor M12 is connected with the second power supply end.

[0094] In some embodiments, the first drive output circuit 3 includes a fifth transistor M5, a sixth transistor M6 and a first capacitor C1.

[0095] The control electrode of the fifth transistor M5 is connected with the first pull-up node PU1, the first electrode of the fifth transistor M5 is connected with the first clock signal input end CLK, and the second electrode of the fifth transistor M5 is connected with the first drive output end OUTPUT1.

[0096] The control electrode of the sixth transistor M6 is connected with the first pull-down node PD1, the first electrode of the sixth transistor M6 is connected with the first drive output end OUTPUT1, and the second electrode of the sixth transistor M6 is connected with the fifth power supply end.

[0097] A first end of the first capacitor C1 is connected with the first pull-up node PU1, and a second end of the first capacitor C1 is connected with the first driving output end OUTPUT1.

[0098] In some embodiments, the shift register unit further comprises a first pull-up noise reduction circuit 5 connected with the first pull-up node PU1, the first pull-down node PD1 and the second power end, and the first pull-up noise reduction circuit 5 is configured to write the voltage provided by the second power end to the first pull-up node PU1 in response to the control of the valid level signal at the first pull-down node PD1.

[0099] In some embodiments, the first pull-up noise reduction circuit 5 comprises a third transistor M3. A control electrode of the third transistor M3 is connected with the first pull-down node PD1, a first electrode of the third transistor M3 is connected with the first pull-up node PU1, and a second electrode of the third transistor M3 is connected with the second power end.

[0100] Figure 7 For Figure 6 A working timing diagram of the shift register unit is shown in FIG. 4. The working process of the shift register unit includes a pre-charge phase t_1, an output phase t_2, a reset phase t_3 and a noise reduction phase t_4. Figure 7

[0101] In the pre-charge phase t_1, the first cascade signal input end INPUT1 provides a high level signal, the first reset signal input end RST1 provides a low level signal, the voltage V3 provided by the third power end is a low level voltage, the voltage V4 provided by the fourth power end is a high level voltage, and the first clock signal input end CLK provides a low level voltage.

[0102] In the pre-charge phase t_1, the first cascade signal input end INPUT1 provides a high level signal, the first reset signal input end RST1 provides a low level signal, the voltage V3 provided by the third power end is a low level voltage, the voltage V4 provided by the fourth power end is a high level voltage, and the first clock signal input end CLK provides a low level voltage.

[0103] ​The voltage V3 provided by the third power supply end is a low-level voltage, and the voltage V4 provided by the fourth power supply end is a high-level voltage, so the eighth transistor M8 is cut off, and the twelfth transistor M12 is turned on, and the low-level voltage VGL1 provided by the second power supply end is written to the first pull-down node PD1 through the twelfth transistor M12.

[0104] The first reset signal input end RST1 provides a low-level signal, so the second transistor M2 and the fourth transistor M4 are both cut off.

[0105] At this time, since the fifth transistor M5 is turned on, the low-level voltage provided by the first clock signal input end CLK is written to the first drive output end OUTPUT1 through the fifth transistor M5, and the first drive output end OUTPUT1 outputs a low level.

[0106] In the output stage t_2, the first cascade signal input end INPUT1 provides a low-level signal, the first reset signal input end RST1 provides a low-level signal, the voltage V3 provided by the third power supply end is a high-level voltage, the voltage V4 provided by the fourth power supply end is a low-level voltage, and the first clock signal input end CLK provides a high-level voltage.

[0107] The first cascade signal input end INPUT1 and the first reset signal input end RST1 both provide low-level signals, so the first transistor M1, the second transistor M2 and the fourth transistor M4 are all cut off. At this time, the first pull-up node PU1 is in a floating state (Floating), and the fifth transistor M5, the ninth transistor M9 and the eleventh transistor M11 are all maintained in a turned-on state.

[0108] The voltage V3 provided by the third power supply end is a high-level voltage, but since the ninth transistor M9 is in a turned-on state, the first pull-down control node PNC1 maintains a low-level state, at this time, the eighth transistor M8 is equivalent to a resistor, and the tenth transistor M10 is maintained in a cut-off state. The voltage V4 provided by the fourth power supply end is a low-level voltage, so the twelfth transistor M12 is in a cut-off state. But since the eleventh transistor M11 is in a turned-on state, the low-level voltage VGL1 provided by the second power supply end is written to the first pull-down node PD1 through the eleventh transistor M11, so the first pull-down node PD1 maintains a low-level state.

[0109] Since the fifth transistor M5 is maintained in the on state, the high level voltage provided by the first clock signal input terminal CLK is written to the first drive output terminal OUTPUT1 through the fifth transistor M5, and the first drive output terminal OUTPUT1 outputs a high level. At this time, since the first pull-up node PU1 is in a floating state, when the voltage at the first drive output terminal OUTPUT1 rises from a low level state to a high level state, the voltage at the first pull-up node PU1 will be pulled up to a higher level state under the bootstrap action of the first capacitor C1. At this time, since the voltage at the first pull-up node PU1 (about 2VGH-VGL) is too high, there will be obvious leakage at the first pull-up node PU1; for example, the first pull-up node PU1 will generate leakage through the first transistor M1 and the second transistor M2.

[0110] At the end of the output stage t_2, the voltage provided by the first clock signal input terminal CLK decreases from a high level voltage to a low level voltage, and at this time the voltage at the first drive output terminal OUTPUT1 will also decrease accordingly; at the same time, the voltage at the first pull-up node PU1 also begins to decrease under the pull-down action of the first capacitor C1. Based on the above analysis, it can be seen that during the process of the voltage at the first pull-up node PU1 following the voltage at the first drive output terminal OUTPUT1, the voltage at the first drive output terminal OUTPUT1 may not decrease to VGL (the low level voltage provided by the first clock signal input terminal CLK), but the voltage at the first pull-up node PU1 reaches VGL+Vth, thereby causing the fifth transistor M5 to turn off in advance, and at this time the low level voltage VGL provided by the first clock signal input terminal CLK cannot be written to the first drive output terminal OUTPUT1.

[0111] In the reset stage t_3, the first cascade signal input terminal INPUT1 provides a low level signal, the first reset signal input terminal RST1 provides a high level signal, the voltage V3 provided by the third power supply terminal is a low level voltage, the voltage V4 provided by the fourth power supply terminal is a high level voltage, and the first clock signal input terminal CLK provides a low level voltage.

[0112] The first cascade signal input terminal INPUT1 provides a low level signal, and the first reset signal input terminal RST1 provides a high level signal, so the first transistor M1 is maintained in the off state, and the second transistor M2 and the fourth transistor M4 are both in the on state. The low level voltage VGL1 provided by the second power supply terminal is written to the first pull-up node PU1 through the second transistor M2, and the first pull-up node PU1 is in a low level state, and the fifth transistor M5 is in the off state.

[0113] The voltage V3 provided by the third power supply end is a low-level voltage, and the voltage V4 provided by the fourth power supply end is a high-level voltage, so that the eighth transistor M8 is cut off, the twelfth transistor M12 is turned on, and the low-level voltage VGL1 provided by the second power supply end is written to the first pull-down node PD1 through the twelfth transistor M12. The ninth transistor M9, the eleventh transistor M11 and the tenth transistor M10 are all in the cut-off state.

[0114] At this time, since the fourth transistor M4 is turned on, the low-level voltage VGL2 provided by the fifth power supply end is written to the first drive output end OUTPUT1 through the fourth transistor M4, and the first drive output end OUTPUT1 outputs a low-level signal.

[0115] The technical solution of the present disclosure can ensure that the first drive output end OUTPUT1 always outputs a low-level signal at the reset stage t_3 by setting the first output reset circuit 4, thereby effectively avoiding the problem of incorrect charging caused by the fact that the fifth transistor M5 is turned off in advance before the reset stage t_3, and the drive output end outputs a high-level voltage at the reset stage t_3. As can be seen, the technical solution of the present disclosure can effectively improve the output stability of the shift register unit.

[0116] At the noise reduction stage t_4, the first cascade signal input end INPUT1 provides a low-level signal, the first reset signal input end RST1 provides a low-level signal, and the third power supply end and the fourth power supply end alternately provide a high-level voltage.

[0117] Specifically, the noise reduction stage t_4 includes a first sub-stage t_4a and a second sub-stage t_4b alternately performed.

[0118] At the first sub-stage t_4a, the voltage V3 provided by the third power supply end is a high-level voltage, and the voltage V4 provided by the fourth power supply end is a low-level voltage.

[0119] Since the first cascade signal input end INPUT1 provides a low-level signal, and the first reset signal input end RST1 provides a low-level signal, the first transistor M1 and the second transistor M2 are both maintained in the cut-off state. The voltage at the first pull-up node PU1 is maintained in a low-level state, and the fifth transistor M5, the ninth transistor M9 and the eleventh transistor M11 are all cut off.

[0120] Since the voltage V3 provided by the third power supply end is a high-level voltage, the high-level voltage provided by the third power supply end can be written to the first pull-down control node PNC1 through the eighth transistor M8, the first pull-down control node PNC1 is in a high-level state, the tenth transistor M10 is turned on, and the high-level voltage provided by the third power supply end is written to the first pull-down node PD1 through the tenth transistor M10, the first pull-down node PD1 is in a high-level state, and the third transistor M3 and the sixth transistor M6 are both turned on. At this time, the low-level voltage VGL1 provided by the second power supply end is written to the first pull-up node PU1 through the third transistor M3 to perform noise reduction on the first pull-up node PU1. At the same time, the low-level voltage VGL2 provided by the fifth power supply end is written to the first drive output end OUTPUT1 through the sixth transistor M6, and the first drive output end OUTPUT1 maintains output low level.

[0121] In the second sub-stage t_4b, the voltage V3 provided by the third power supply end is a low-level voltage, and the voltage V4 provided by the fourth power supply end is a high-level voltage.

[0122] Since the voltage V4 provided by the fourth power supply end is a high-level voltage, the twelfth transistor M12 is turned on, the low-level voltage VGL1 provided by the second power supply end is written to the first pull-down node PD1 through the twelfth transistor M12, the first pull-down node PD1 is in a low-level state, and the third transistor M3 and the sixth transistor M6 are both maintained in a cut-off state. At this time, the first drive output end OUTPUT1 is in a floating state to maintain the output low level.

[0123] Based on Figure 7 It can be seen that the voltage at the first pull-down node PD1 is in a high-level state in the first sub-stage and in a low-level state in the second sub-stage, that is, the sixth transistor M6 will be turned on in the first sub-stage and turned off in the second sub-stage, that is, the sixth transistor M6 will be switched between the on state and the off state in the noise reduction stage t_4, which can effectively avoid the problem of serious threshold voltage drift caused by the sixth transistor M6 being in a single state for a long time.

[0124] In the related art, the first drive output circuit 3 is not only used to provide a drive signal for the corresponding gate line in the display panel, but also used to provide a cascading signal for other shift registers of the adjacent stage, at this time, the first drive output end OUTPUT1 of the first drive output circuit 3 has a large load, which is easy to cause problems such as signal delay and large noise at the first drive output end OUTPUT1. In order to effectively improve the problem of large load at the first drive output end OUTPUT1 in the related art, the present disclosure provides a corresponding solution.

[0125] Figure 8Another circuit structure diagram of the shift register unit provided by the embodiments of the present disclosure is shown in FIG. 6, which is different from the previous embodiments in that Figure 8 As shown in FIG. 6, the shift register unit includes not only the first driving output circuit 3 but also a first cascaded output circuit 6. Figure 8 As shown in FIG. 6, the shift register unit includes not only the first driving output circuit 3 but also a first cascaded output circuit 6.

[0126] The first cascaded output circuit 6 is connected with the first pull-up node PU1, the first pull-down node PD1, the first clock signal input terminal CLK, the second power supply terminal and the first cascaded output terminal CR1, and is configured to write the signal provided by the first clock signal input terminal CLK to the first cascaded output terminal CR1 in response to the control of the valid level signal at the first pull-up node PU1, and write the voltage provided by the fifth power supply terminal to the first cascaded output terminal CR1 in response to the control of the valid level signal at the first pull-down node PD1.

[0127] In some embodiments, the first cascaded output circuit 6 includes a fifteenth transistor M15 and a sixteenth transistor M16. The control electrode of the fifteenth transistor M15 is connected with the first pull-up node PU1, the first electrode of the fifteenth transistor M15 is connected with the first clock signal input terminal CLK, and the second electrode of the fifteenth transistor M15 is connected with the first cascaded output terminal CR1. The control electrode of the sixteenth transistor M16 is connected with the first pull-down node PD1, the first electrode of the sixteenth transistor M16 is connected with the first cascaded output terminal CR1, and the second electrode of the sixteenth transistor M16 is connected with the second power supply terminal.

[0128] In the embodiments of the present disclosure, the first driving output terminal OUTPUT1 of the first driving output circuit 3 can be used to provide a driving signal to the corresponding gate line in the display panel, and the first cascaded output terminal CR1 of the first cascaded output circuit 6 can be used to provide a cascaded signal to other shift registers of the adjacent stage; in this way, the load at the first driving output terminal OUTPUT1 can be effectively reduced, which is conducive to reducing the signal delay and noise at the first driving output terminal OUTPUT1.

[0129] Figure 9 Another circuit structure diagram of the shift register unit provided by the embodiments of the present disclosure is shown in FIG. 6, which is different from the previous embodiments in that Figure 9 As shown in FIG. 6, the shift register unit includes not only the first driving output circuit 3 but also a first cascaded output circuit 6.

[0130] In some embodiments, the third pull-down control circuit 7 comprises a thirteenth transistor M13, a control electrode of the thirteenth transistor M13 is connected with the first cascade signal input end INPUT1, a first electrode of the thirteenth transistor M13 is connected with the first pull-down node PD1, and a second electrode of the thirteenth transistor M13 is connected with the second power supply end.

[0131] The third pull-down control circuit 7 works in the pre-charge stage (the thirteenth transistor M13 is in the on state in the pre-charge stage) to write the second working voltage VGL1 provided by the second power supply end to the first pull-down node PD1.

[0132] Before the pre-charge stage of the current cycle, the first sub-stage of the noise reduction stage of the previous cycle (the voltage V3 provided by the third power supply end is a high voltage, and the voltage V4 provided by the fourth power supply end is a low voltage), that is, at the initial moment of entering the pre-charge stage of the current cycle, the voltage at the first pull-down node PD1 is high. In order to make the voltage at the first pull-down node PD1 drop to a low state quickly after entering the pre-charge stage (to prevent the fifth transistor M5 and the sixth transistor M6 from being on at the same time), the third pull-down control circuit 7 is added. Under the joint action of the third pull-down control circuit 7 (the thirteenth transistor M13) and the third pull-down sub-circuit (the twelfth transistor M12), the voltage at the first pull-down node PD1 can drop to a low state quickly after entering the pre-charge stage; that is, the sixth transistor M6 will be in the off state quickly after entering the pre-charge stage, so as to avoid the situation that the fifth transistor M5 and the sixth transistor M6 are on at the same time in the pre-charge stage.

[0133] In some embodiments, the shift register unit further comprises a first global reset circuit 8, the first global reset circuit 8 is connected with the global reset signal input end TRST, the second power supply end and the first pull-up node PU1, and the first global reset circuit 8 is configured to write the voltage provided by the second power supply end to the first pull-up node PU1 in response to the control of the effective level signal provided by the global reset signal input end TRST.

[0134] In some embodiments, the first global reset circuit 8 comprises a fourteenth transistor M14, a control electrode of the fourteenth transistor M14 is connected with the global reset signal input end TRST, a first electrode of the fourteenth transistor M14 is connected with the first pull-up node PU1, and a second electrode of the fourteenth transistor M14 is connected with the second power supply end.

[0135] Generally, the first global reset circuit 8 will provide an effective level signal before the end of a frame and the beginning of the next frame, so as to globally reset the pull-up nodes of each shift register unit in the gate drive circuit.

[0136] Figure 9The shift register unit shown in FIG. 1 includes the third pull-down control circuit 7 and the first global reset circuit 8, which is only exemplary and does not limit the technical solutions of the present disclosure.

[0137] Figure 8 and Figure 9 The working timing of the shift register unit shown in FIG. 1 can refer to the working timing shown in FIG. 2, and the specific working process is not described here. Figure 7

[0138] It should be noted that, Figure 5 , Figure 6 , Figure 8 and Figure 9 The shift register unit shown in FIG. 1 includes only one shift register circuit, that is, one shift register unit can only provide a driving signal to a corresponding gate line in the display panel.

[0139] Figure 10 Another circuit structure diagram of the shift register unit provided by the embodiment of the present disclosure is shown in FIG. 3, which is different from the embodiment that one shift register unit includes one shift register circuit in the previous embodiment, Figure 10 Figure 10 The embodiment shown in FIG. 3 includes two shift register circuits GOA1 and GOA2, and the shift register unit can provide driving signals to two corresponding gate lines in the display panel. For convenience of description, the two shift register circuits included in the shift register unit are referred to as the first shift register circuit GOA1 and the second shift register circuit GOA2.

[0140] In some embodiments, the first shift register circuit GOA1 can include the first pre-charge reset circuit 1, the first pull-down control circuit 2, the first driving output circuit 3, and the first output reset circuit 4 in the previous embodiment. Of course, the first shift register circuit GOA1 can also selectively include at least one of the first cascade output circuit 6, the third pull-down control circuit 7, and the first global reset circuit 8 in the previous embodiment. For the specific circuit structure of the first pre-charge reset circuit 1, the first pull-down control circuit 2, the first driving output circuit 3, the first output reset circuit 4, the first cascade output circuit 6, the third pull-down control circuit 7, and the first global reset circuit 8, the structure shown in Figure 5 Figure 6 Figure 8 and Figure 9 of course, other structures can also be used.

[0141] In some embodiments, the second shift register unit includes a second pre-charge reset circuit 11, a second pull-down control circuit 12, a second driving output circuit 13, and a second output reset circuit 14. ​​​​

[0142] The second pre-charge reset circuit 11 is connected with the second cascade signal input end INPUT2, the second reset signal input end RST2, the first power supply end, the second power supply end, and the second pull-up node PU2. The second pre-charge reset circuit 11 is configured to write the voltage provided by the first power supply end to the second pull-up node PU2 in response to the control of the effective level signal provided by the second cascade signal input end INPUT2, and write the voltage provided by the second power supply end to the second pull-up node PU2 in response to the control of the effective level signal provided by the second reset signal input end RST2.

[0143] The second pull-down control circuit 12 is connected with the second pull-up node PU2, the second pull-down node PD2, the second power supply end, the third power supply end, and the fourth power supply end. The second pull-down control circuit 12 is configured to write the effective level signal to the second pull-down node PD2 when the fourth power supply end provides the effective level signal and the voltage at the second pull-up node PU2 is in the non-effective level state, and write the non-effective level signal to the second pull-down node PD2 when the third power supply end provides the effective level signal or when the second pull-up node PU2 is in the effective level state.

[0144] The second drive output circuit 13 is connected with the second pull-up node PU2, the second pull-down node PD2, the second clock signal input end CLKB, the fifth power supply end, and the second drive output end OUTPUT2. The second drive output circuit 13 is configured to write the signal provided by the second clock signal input end CLKB to the second drive output end OUTPUT2 in response to the control of the effective level signal at the second pull-up node PU2, and write the voltage provided by the fifth power supply end to the second drive output end OUTPUT2 in response to the control of the effective level signal at the second pull-down node PD2.

[0145] The second output reset circuit 14 is connected with the second reset signal input end RST2, the fifth power supply end, and the second drive output end OUTPUT2. The second output reset circuit 14 is configured to write the voltage provided by the fifth power supply end to the second drive output end OUTPUT2 in response to the control of the effective level signal provided by the second reset signal input end RST2.

[0146] In the embodiments of the present disclosure, the circuit structure of the second shift register circuit GOA2 is similar to that of the first shift register circuit GOA1, and the working processes of the two are also similar. The function of the second output reset circuit 14 is also similar to that of the first output reset circuit 4, which can be used to write the voltage provided by the fifth power supply end to the second drive output end OUTPUT2 when the second shift register circuit GOA2 works in the reset phase, so as to ensure that the second drive output end OUTPUT2 is in the non-effective level state in the reset phase.

[0147] In some embodiments, the first shift register circuit GOA1 comprises a first cascade output circuit 6, and the second shift register circuit GOA2 further comprises: a second cascade output circuit 16. The second cascade output circuit 16 is connected with the second pull-up node PU2, the second pull-down node PD2, the second clock signal input terminal CLKB, the second power supply terminal and the second cascade output terminal CR2, and is configured to write the signal provided by the second clock signal input terminal CLKB to the second cascade output terminal CR2 in response to the control of the valid level signal at the second pull-up node PU2, and write the voltage provided by the fifth power supply terminal to the first cascade output terminal CR1 in response to the control of the valid level signal at the second pull-down node PD2; the first cascade output terminal CR1 is connected with the second cascade signal input terminal INPUT2, and the second cascade output terminal CR2 is connected with the first reset signal input terminal RST1.

[0148] In the embodiments of the present disclosure, in the shift register unit, the first cascade output terminal CR1 of the first shift register circuit GOA1 provides a cascade signal to the second cascade signal input terminal INPUT2 of the second shift register circuit GOA2, and the second cascade output terminal CR2 of the second shift register circuit GOA2 provides a reset signal to the first reset signal input terminal RST1 of the first shift register circuit GOA1, and the first shift register circuit GOA1 and the second shift register circuit GOA2 constitute a cascade.

[0149] In some embodiments, the second shift register circuit GOA2 further comprises: a second pull-up noise reduction circuit 15; the second pull-up noise reduction circuit 15 is connected with the second pull-up node PU2, the second pull-down node PD2 and the second power supply terminal, and the second pull-up noise reduction circuit 15 is configured to write the voltage provided by the second power supply terminal to the second pull-up node PU2 in response to the control of the valid level signal at the second pull-down node PD2.

[0150] In some embodiments, the second shift register circuit GOA2 further comprises: a fourth pull-down control circuit 17, which is connected with the second cascade signal input terminal INPUT2, the second power supply terminal and the second pull-down node PD2, and the fourth pull-down control circuit 17 is configured to write the voltage provided by the second power supply terminal to the second pull-down node PD2 in response to the control of the valid level signal provided by the second cascade signal input terminal INPUT2.

[0151] In some embodiments, the second shift register circuit GOA2 further comprises a second global reset circuit 18, which is connected with the global reset signal input terminal TRST, the second power supply terminal and the second pull-up node PU2, and the second global reset circuit 18 is configured to write the voltage provided by the second power supply terminal to the second pull-up node PU2 in response to the control of the valid level signal provided by the global reset signal input terminal TRST.

[0152] Figure 11 Another circuit structure diagram of the shift register unit provided by the embodiments of the present disclosure is shown in FIG. 6, Figure 12 For Figure 11 A working timing diagram of the shift register unit shown in FIG. 6 is shown in FIG. 7, Figure 11 and Figure 12 as shown in FIG. 8, Figure 11 The shift register unit shown in FIG. 8 is based on Figure 10 A specific optional implementation of the shift register unit shown in FIG. 8.

[0153] In some embodiments, the first pull-down control circuit 2 is further connected with the second pull-up node PU2, and the first pull-down control circuit 2 comprises a first control sub-circuit 201, a second control sub-circuit 202 and a third control sub-circuit 203.

[0154] The first control sub-circuit 201 is connected with the first pull-up node PU1, the second pull-up node PU2, the first pull-down control node PNC1, the second power supply end and the third power supply end, and the first control sub-circuit 201 is configured to write the voltage provided by the second power supply end to the first pull-down control node PNC1 when at least one of the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 is in an effective level state, and write an effective level signal to the first pull-down control node PNC1 when the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 are both in a non-effective level state and the third power supply end provides an effective level signal.

[0155] The second control sub-circuit 202 is connected with the first pull-down control node PNC1, the first pull-up node PU1, the second pull-up node PU2, the first pull-down node PD1, the second power supply end and the third power supply end, and the second control sub-circuit 202 is configured to write an effective level signal to the first pull-down node PD1 when the voltage at the first pull-down control node PNC1 is in an effective level state, and write the voltage provided by the second power supply end to the first pull-down node PD1 when at least one of the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 is in an effective level state.

[0156] The third control sub-circuit 203 is connected with the first pull-down node PD1, the second power supply end and the fourth power supply end, and the third control sub-circuit 203 is configured to write the voltage provided by the second power supply end to the first pull-down node PD1 when the fourth power supply end provides an effective level signal.

[0157] The second pull-down control circuit 12 is further connected with the first pull-up node PU1, and the second pull-down control circuit 12 comprises a fourth control sub-circuit 1201, a fifth control sub-circuit 1202 and a sixth control sub-circuit 1203.

[0158] The fourth control sub-circuit 1201 is connected with the first pull-up node PU1, the second pull-up node PU2, the second pull-down control node PNC2, the second power supply end and the fourth power supply end. The fourth control sub-circuit 1201 is configured to write the voltage provided by the second power supply end to the second pull-down control node PNC2 when at least one of the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 is at an effective level, and write an effective level signal to the second pull-down control node PNC2 when the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 are both at an ineffective level and the fourth power supply end provides an effective level signal.

[0159] The fifth control sub-circuit 1202 is connected with the second pull-down control node PNC2, the first pull-up node PU1, the second pull-up node PU2, the second pull-down node PD2, the second power supply end and the fourth power supply end. The fifth control sub-circuit 1202 is configured to write an effective level signal to the second pull-down node PD2 when the voltage at the second pull-down control node PNC2 is at an effective level, and write the voltage provided by the second power supply end to the second pull-down node PD2 when at least one of the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 is at an effective level.

[0160] The sixth control sub-circuit 1203 is connected with the second pull-down node PD2, the second power supply end and the third power supply end. The sixth control sub-circuit 1203 is configured to write the voltage provided by the second power supply end to the second pull-down node PD2 when the third power supply end provides an effective level signal.

[0161] In some embodiments, the first drive output circuit 3 is further connected with the second pull-down node PD2. The first drive output circuit 3 is further configured to write the voltage provided by the fifth power supply end to the first drive output end OUTPUT1 in response to the control of the effective level signal at the second pull-down node PD2.

[0162] The second drive output circuit 13 is further connected with the first pull-down node PD1. The second drive output circuit 13 is further configured to write the voltage provided by the fifth power supply end to the second drive output end OUTPUT2 in response to the control of the effective level signal at the first pull-down node PD1.

[0163] The first cascade output circuit 6 is further connected with the second pull-down node PD2. The first cascade output circuit 6 is further configured to write the voltage provided by the fifth power supply end to the first cascade output end CR1 in response to the control of the effective level signal at the second pull-down node PD2.

[0164] The second cascaded output circuit 16 is also connected with the first pull-down node PD1, and the second cascaded output circuit 16 is configured to write the voltage provided by the fifth power supply end to the second cascaded output end CR2 in response to the control of the valid level signal at the first pull-down node PD1.

[0165] In some embodiments, the first pull-up noise reduction circuit 5 is also connected with the second pull-down node PD2, and the first pull-up noise reduction circuit 5 is configured to write the voltage provided by the second power supply end to the first pull-up node PU1 in response to the control of the valid level signal at the second pull-down node PD2.

[0166] The second pull-up noise reduction circuit 15 is also connected with the first pull-down node PD1, and the second pull-up noise reduction circuit 15 is configured to write the voltage provided by the second power supply end to the second pull-up node PU2 in response to the control of the valid level signal at the first pull-down node PD1.

[0167] In the first shift register circuit GOA1, the first pre-charge reset circuit 1 includes a first transistor M1 and a second transistor M2.

[0168] The control electrode of the first transistor M1 is connected with the first cascaded signal input end INPUT1, the first electrode of the first transistor M1 is connected with the first power supply end, and the second electrode of the first transistor M1 is connected with the first pull-up node PU1.

[0169] The control electrode of the second transistor M2 is connected with the first reset signal input end RST1, the first electrode of the second transistor M2 is connected with the first pull-up node PU1, and the second electrode of the second transistor M2 is connected with the second power supply end.

[0170] The first control sub-circuit 201 includes an eighth transistor M8, a ninth transistor M9 and a seventeenth transistor M17, the second control sub-circuit 202 includes a tenth transistor M10, an eleventh transistor M11 and an eighteenth transistor M18, and the third control sub-circuit 203 includes a twelfth transistor M12.

[0171] The control electrode and the first electrode of the eighth transistor M8 are both connected with the third power supply end, and the second electrode of the eighth transistor M8 is connected with the first pull-down control node PNC1.

[0172] The control electrode of the ninth transistor M9 is connected with the first pull-up node PU1, the first electrode of the ninth transistor M9 is connected with the first pull-down control node PNC1, and the second electrode of the ninth transistor M9 is connected with the second power supply end.

[0173] The control electrode of the seventeenth transistor M17 is connected with the second pull-up node PU2, the first electrode of the seventeenth transistor M17 is connected with the first pull-down node PD1, and the second electrode of the seventeenth transistor M17 is connected with the second power supply end.

[0174] The control electrode of the tenth transistor M10 is connected with the first pull-down control node PNC1, the first electrode of the tenth transistor M10 is connected with the third power supply, and the second electrode of the tenth transistor M10 is connected with the first pull-down node PD1.

[0175] The control electrode of the eleventh transistor M11 is connected with the first pull-up node PU1, the first electrode of the eleventh transistor M11 is connected with the first pull-down node PD1, and the second electrode of the eleventh transistor M11 is connected with the second power supply.

[0176] The control electrode of the eighteenth transistor M18 is connected with the second pull-up node PU2, the first electrode of the eighteenth transistor M18 is connected with the first pull-down node PD1, and the second electrode of the eighteenth transistor M18 is connected with the second power supply.

[0177] The control electrode of the twelfth transistor M12 is connected with the fourth power supply, the first electrode of the twelfth transistor M12 is connected with the first pull-down node PD1, and the second electrode of the twelfth transistor M12 is connected with the second power supply.

[0178] The first cascade output circuit 6 comprises a fifteenth transistor M15, a sixteenth transistor M16 and a twentieth transistor M20.

[0179] The control electrode of the fifteenth transistor M15 is connected with the first pull-up node PU1, the first electrode of the fifteenth transistor M15 is connected with the first clock signal input terminal CLK, and the second electrode of the fifteenth transistor M15 is connected with the first cascade output terminal CR1.

[0180] The control electrode of the sixteenth transistor M16 is connected with the first pull-down node PD1, the first electrode of the sixteenth transistor M16 is connected with the first cascade output terminal CR1, and the second electrode of the sixteenth transistor M16 is connected with the second power supply.

[0181] The control electrode of the twentieth transistor M20 is connected with the second pull-down node PD2, the first electrode of the twentieth transistor M20 is connected with the first cascade output terminal CR1, and the second electrode of the twentieth transistor M20 is connected with the second power supply.

[0182] The first drive output circuit 3 comprises a fifth transistor M5, a sixth transistor M6, a nineteenth transistor M19 and a first capacitor C1.

[0183] The control electrode of the fifth transistor M5 is connected with the first pull-up node PU1, the first electrode of the fifth transistor M5 is connected with the first clock signal input terminal CLK, and the second electrode of the fifth transistor M5 is connected with the first drive output terminal OUTPUT1.

[0184] The control electrode of the sixth transistor M6 is connected with the first pull-down node PD1, the first electrode of the sixth transistor M6 is connected with the first drive output end OUTPUT1, and the second electrode of the sixth transistor M6 is connected with the fifth power supply end.

[0185] The control electrode of the nineteenth transistor M19 is connected with the second pull-down node PD2, the first electrode of the nineteenth transistor M19 is connected with the first drive output end OUTPUT1, and the second electrode of the nineteenth transistor M19 is connected with the fifth power supply end.

[0186] The first end of the first capacitor C1 is connected with the first pull-up node PU1, and the second end of the first capacitor C1 is connected with the first drive output end OUTPUT1.

[0187] The first pull-up noise reduction circuit 5 comprises a third transistor M3 and a seventh transistor M7.

[0188] The control electrode of the third transistor M3 is connected with the first pull-down node PD1, the first electrode of the third transistor M3 is connected with the first pull-up node PU1, and the second electrode of the third transistor M3 is connected with the second power supply end.

[0189] The control electrode of the seventh transistor M7 is connected with the second pull-down node PD2, the first electrode of the seventh transistor M7 is connected with the first pull-up node PU1, and the second electrode of the seventh transistor M7 is connected with the second power supply end.

[0190] The third pull-down control circuit 7 comprises a thirteenth transistor M13.

[0191] The control electrode of the thirteenth transistor M13 is connected with the first cascade signal input end INPUT1, the first electrode of the thirteenth transistor M13 is connected with the first pull-down node PD1, and the second electrode of the thirteenth transistor M13 is connected with the second power supply end.

[0192] The first global reset circuit 8 comprises a fourteenth transistor M14.

[0193] The control electrode of the fourteenth transistor M14 is connected with the global reset signal input end TRST, the first electrode of the fourteenth transistor M14 is connected with the first pull-up node PU1, and the second electrode of the fourteenth transistor M14 is connected with the second power supply end.

[0194] The first output reset circuit 4 comprises a fourth transistor M4.

[0195] The control electrode of the fourth transistor M4 is connected with the first reset signal input end RST1, the first electrode of the fourth transistor M4 is connected with the first drive output end OUTPUT1, and the second electrode of the fourth transistor M4 is connected with the fifth power supply end.

[0196] In the second shift register circuit GOA2, the second pre-charge reset circuit 11 includes a twenty-first transistor M21 and a twenty-second transistor M22.

[0197] The control electrode of the twenty-first transistor M21 is connected with the second cascade signal input end INPUT2, the first electrode of the twenty-first transistor M21 is connected with the first power supply end, and the second electrode of the twenty-first transistor M21 is connected with the second pull-up node PU2.

[0198] The control electrode of the twenty-second transistor M22 is connected with the second reset signal input end RST2, the first electrode of the twenty-second transistor M22 is connected with the second pull-up node PU2, and the second electrode of the twenty-second transistor M22 is connected with the second power supply end.

[0199] The fourth control sub-circuit includes a twenty-eighth transistor M28, a twenty-ninth transistor M29 and a thirty-seventh transistor M37, the fifth control sub-circuit includes a thirtieth transistor M30, a thirty-first transistor M31 and a thirty-eighth transistor M38, and the sixth control sub-circuit includes a thirty-second transistor M32.

[0200] The control electrode and the first electrode of the twenty-eighth transistor M28 are both connected with the third power supply end, and the second electrode of the twenty-eighth transistor M28 is connected with the second pull-down control node.

[0201] The control electrode of the twenty-ninth transistor M29 is connected with the second pull-up node PU2, the first electrode of the twenty-ninth transistor M29 is connected with the second pull-down control node, and the second electrode of the twenty-ninth transistor M29 is connected with the second power supply end.

[0202] The control electrode of the thirty-seventh transistor M37 is connected with the first pull-up node PU1, the first electrode of the thirty-seventh transistor M37 is connected with the second pull-down node PD2, and the second electrode of the thirty-seventh transistor M37 is connected with the second power supply end.

[0203] The control electrode of the thirtieth transistor M30 is connected with the second pull-down control node, the first electrode of the thirtieth transistor M30 is connected with the third power supply, and the second electrode of the thirtieth transistor M30 is connected with the second pull-down node PD2.

[0204] The control electrode of the thirty-first transistor M31 is connected with the second pull-up node PU2, the first electrode of the thirty-first transistor M31 is connected with the second pull-down node PD2, and the second electrode of the thirty-first transistor M31 is connected with the second power supply end.

[0205] The control electrode of the thirty-eighth transistor M38 is connected with the first pull-up node PU1, the first electrode of the thirty-eighth transistor M38 is connected with the second pull-down node PD2, and the second electrode of the thirty-eighth transistor M38 is connected with the second power supply end.

[0206] The control electrode of the thirty-second transistor M32 is connected with the fourth power supply end, the first electrode of the thirty-second transistor M32 is connected with the second pull-down node PD2, and the second electrode of the thirty-second transistor M32 is connected with the second power supply end.

[0207] The second cascade output circuit 16 comprises a thirty-fifth transistor M35, a thirty-sixth transistor M36 and a fortieth transistor M40.

[0208] The control electrode of the thirty-fifth transistor M35 is connected with the second pull-up node PU2, the first electrode of the thirty-fifth transistor M35 is connected with the second clock signal input end, and the second electrode of the thirty-fifth transistor M35 is connected with the second cascade output end CR2.

[0209] The control electrode of the thirty-sixth transistor M36 is connected with the second pull-down node PD2, the first electrode of the thirty-sixth transistor M36 is connected with the second cascade output end CR2, and the second electrode of the thirty-sixth transistor M36 is connected with the second power supply end.

[0210] The control electrode of the fortieth transistor M40 is connected with the first pull-down node PD1, the first electrode of the fortieth transistor M40 is connected with the second cascade output end CR2, and the second electrode of the fortieth transistor M40 is connected with the second power supply end.

[0211] The second drive output circuit 13 comprises a twenty-fifth transistor M25, a twenty-sixth transistor M26, a thirty-ninth transistor M39 and a second capacitor C2.

[0212] The control electrode of the twenty-fifth transistor M25 is connected with the second pull-up node PU2, the first electrode of the twenty-fifth transistor M25 is connected with the second clock signal input end, and the second electrode of the twenty-fifth transistor M25 is connected with the second drive output end OUTPUT2.

[0213] The control electrode of the twenty-sixth transistor M26 is connected with the second pull-down node PD2, the first electrode of the twenty-sixth transistor M26 is connected with the second drive output end OUTPUT2, and the second electrode of the twenty-sixth transistor M26 is connected with the fifth power supply end.

[0214] The control electrode of the thirty-ninth transistor M39 is connected with the first pull-down node PD1, the first electrode of the thirty-ninth transistor M39 is connected with the second drive output end OUTPUT2, and the second electrode of the thirty-ninth transistor M39 is connected with the fifth power supply end.

[0215] The first end of the second capacitor C2 is connected with the second pull-up node PU2, and the second end of the second capacitor C2 is connected with the second drive output end OUTPUT2.

[0216] The second pull-up noise reduction circuit 15 comprises a twenty-third transistor M23 and a twenty-seventh transistor M27.

[0217] The control electrode of the twenty-third transistor M23 is connected with the second pull-down node PD2, the first electrode of the twenty-third transistor M23 is connected with the second pull-up node PU2, and the second electrode of the twenty-third transistor M23 is connected with the second power supply end.

[0218] The control electrode of the twenty-seventh transistor M27 is connected with the first pull-down node PD1, the first electrode of the twenty-seventh transistor M27 is connected with the second pull-up node PU2, and the second electrode of the twenty-seventh transistor M27 is connected with the second power supply end.

[0219] The fourth pull-down control circuit 17 comprises a thirty-third transistor M33.

[0220] The control electrode of the thirty-third transistor M33 is connected with the second cascade signal input end INPUT2, the first electrode of the thirty-third transistor M33 is connected with the second pull-down node PD2, and the second electrode of the thirty-third transistor M33 is connected with the second power supply end.

[0221] The second global reset circuit 18 comprises a thirty-fourth transistor M34.

[0222] The control electrode of the thirty-fourth transistor M34 is connected with the global reset signal input end TRST, the first electrode of the thirty-fourth transistor M34 is connected with the second pull-up node PU2, and the second electrode of the thirty-fourth transistor M34 is connected with the second power supply end.

[0223] The second output reset circuit 14 comprises a twenty-fourth transistor M24.

[0224] The control electrode of the twenty-fourth transistor M24 is connected with the second reset signal input end RST2, the first electrode of the twenty-fourth transistor M24 is connected with the second drive output end OUTPUT2, and the second electrode of the twenty-fourth transistor M24 is connected with the fifth power supply end.

[0225] Referring to Figure 12 As shown, the working process of the first gate drive circuit GOA1 in the shift register unit comprises a pre-charge stage t1_1, an output stage t1_2, a reset stage t1_3 and a noise reduction stage t1_4; the working process of the second gate drive circuit GOA2 in the shift register unit comprises a pre-charge stage t2_1, an output stage t2_2, a reset stage t2_3 and a noise reduction stage t2_4. For specific working processes, please refer to the related description of the foregoing Figure 7 .

[0226] Figure 13 A circuit structure schematic diagram of the gate drive circuit provided by the embodiment of the present disclosure is shown inFigure 14 This is a schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of the present disclosure, such as... Figure 13 and Figure 14 As shown, the gate drive circuit includes: a plurality of cascaded shift register units, at least one of which adopts the shift register unit provided in the above embodiment. For a detailed description of the shift register unit, please refer to the preceding content. Figure 13 and Figure 14 The example shows a 4-level shift register unit.

[0227] In some embodiments, each stage of the shift register unit SR_1 to SR_4 in the gate driving circuit adopts the shift register unit in the previous embodiment. The gate driving circuit is configured with a frame start signal input terminal STV and a frame end signal input terminal (not shown). The frame start signal input terminal STV is connected to the first cascade signal input terminal (INPUT1) of the shift register unit SR_1 located in the first stage of the gate driving circuit, and the frame end signal input terminal is connected to the reset signal input terminal of the shift register unit located in the last stage of the gate driving circuit.

[0228] Figure 13 The example shown illustrates a shift register unit that includes only one shift register circuit. Figure 14 The illustration shows a case where a shift register unit includes two shift register circuits and the two shift register units are cascaded. These cases are all within the protection scope of this disclosure.

[0229] The gate drive circuit is equipped with two clock signal supply lines, CK1 and CK2; Figure 13 In the illustrated case, the first clock signal input terminal CLK of the shift register unit located in the odd-numbered stage is connected to the clock signal supply line CK1, and the first clock signal input terminal CLK of the shift register unit located in the even-numbered stage is connected to the clock signal supply line CK2. Figure 13 In the scenario shown, the first clock signal input terminal CLK in each shift register unit is connected to the clock signal supply line CK1, and the second clock signal input terminal CLKB in each shift register unit is connected to the clock signal supply line CK2.

[0230] Based on the same inventive concept, this disclosure also provides a display substrate, which includes a display area and a peripheral area located around the display area. A gate driving circuit is disposed in the peripheral area. The gate driving circuit adopts the gate driving circuit provided in the previous embodiment. For a detailed description of the gate driving circuit, please refer to the content in the previous embodiment, which will not be repeated here.

[0231] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes a display substrate, which can be the display substrate provided by the above embodiments. For the specific description of the display substrate, please refer to the above embodiments, which will not be repeated here.

[0232] The display device provided by the embodiments of the present disclosure can be a display panel, a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device should be understood by those skilled in the art, and will not be repeated here, nor should it be considered as a limitation to the present disclosure.

[0233] Based on the same inventive concept, the embodiments of the present disclosure also provide a gate driving method. Figure 15 A flow chart of the gate driving method provided by the embodiments of the present disclosure is shown in FIG. 8. The gate driving method is based on the shift register unit provided by the above embodiments. For the related description of the shift register unit, please refer to the above embodiments, which will not be repeated here. Figure 15

[0234] The gate driving method includes:

[0235] In step S1, in the pre-charging stage, the first pre-charging reset circuit writes the voltage provided by the first power supply end to the first pull-up node in response to the control of the effective level signal provided by the first cascade signal input end, so as to pre-charge the first pull-up node;

[0236] In step S2, in the output stage, the first driving output circuit writes the signal provided by the first clock signal input end to the first driving output end in response to the control of the effective level signal at the first pull-up node;

[0237] In step S3, in the reset stage, the first pre-charging reset circuit writes the voltage provided by the second power supply end to the first pull-up node in response to the control of the effective level signal provided by the first reset signal input end, so as to reset the first pull-up node, and the first output reset circuit writes the voltage provided by the fifth power supply end to the first driving output end in response to the control of the effective level signal provided by the first reset signal input end, so as to reset the first driving output end;

[0238] In step S4, in the noise reduction stage, the first pull-down control circuit writes the effective level signal to the first pull-down node when the third power supply end provides the effective level signal and the voltage at the first pull-up node is in the non-effective level state, and writes the non-effective level signal to the first pull-down node when the fourth power supply end provides the effective level signal.

[0239] ​For the specific description of the above steps S1-S4, please refer to the relevant description of each stage in the foregoing embodiments, which will not be repeated here.

[0240] In the embodiments of the present disclosure, in the case that the first pull-down control circuit capable of alternately outputting the active level signal and the inactive level signal to the pull-down node is arranged in the shift register unit, by additionally arranging the first output reset circuit, the voltage provided by the fifth power supply end is written to the first driving output end by the first output reset circuit in the reset stage, so as to reset the first driving output end, so that the voltage of the first driving output end can quickly reach VGL2 after entering the reset stage, thereby avoiding the problem of incorrect charging of the shift register unit in the reset stage.

[0241] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present application, but the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A shift register unit characterized by comprising: The first pre-charge reset circuit is connected with the first cascade signal input end, the first reset signal input end, the first power supply end, the second power supply end and the first pull-up node, and is configured to write the voltage provided by the first power supply end to the first pull-up node in response to the control of the valid level signal provided by the first cascade signal input end, and write the voltage provided by the second power supply end to the first pull-up node in response to the control of the valid level signal provided by the first reset signal input end. The first pull-down control circuit is connected with the first pull-up node, the first pull-down node, the second power supply end, the third power supply end and the fourth power supply end, and is configured to write the valid level signal to the first pull-down node when the third power supply end provides the valid level signal and the voltage at the first pull-up node is in the invalid level state, and write the invalid level signal to the first pull-down node when the fourth power supply end provides the valid level signal or when the first pull-up node is in the valid level state. The first drive output circuit is connected with the first pull-up node, the first pull-down node, the first clock signal input end, the fifth power supply end and the first drive output end, and is configured to write the signal provided by the first clock signal input end to the first drive output end in response to the control of the valid level signal at the first pull-up node, and write the voltage provided by the fifth power supply end to the first drive output end in response to the control of the valid level signal at the first pull-down node. The first output reset circuit is connected with the first reset signal input end, the fifth power supply end and the first drive output end, and is configured to write the voltage provided by the fifth power supply end to the first drive output end in response to the control of the valid level signal provided by the first reset signal input end. The second pre-charge reset circuit is connected with the second cascade signal input end, the second reset signal input end, the first power supply end, the second power supply end and the second pull-up node, and is configured to write the voltage provided by the first power supply end to the second pull-up node in response to the control of the valid level signal provided by the second cascade signal input end, and write the voltage provided by the second power supply end to the second pull-up node in response to the control of the valid level signal provided by the second reset signal input end. The second pull-down control circuit is connected with the second pull-up node, the second pull-down node, the second power supply end, the third power supply end and the fourth power supply end, and is configured to write the valid level signal to the second pull-down node when the fourth power supply end provides the valid level signal and the voltage at the second pull-up node is in the invalid level state, and write the invalid level signal to the second pull-down node when the third power supply end provides the valid level signal or when the second pull-up node is in the valid level state. ​ The second driving output circuit is connected with the second pull-up node, the second pull-down node, a second clock signal input end, a fifth power supply end and a second driving output end, and is configured to write a signal provided by the second clock signal input end to the second driving output end in response to a control of a valid level signal at the second pull-up node, and write a voltage provided by the fifth power supply end to the second driving output end in response to a control of a valid level signal at the second pull-down node; The second output reset circuit is connected with the second reset signal input end, the fifth power supply end and the second driving output end, and is configured to write a voltage provided by the fifth power supply end to the second driving output end in response to a control of a valid level signal provided by the second reset signal input end; The first pull-down control circuit is further connected with the second pull-up node, and the first pull-down control circuit comprises: The first control sub-circuit is connected with the first pull-up node, the second pull-up node, a first pull-down control node, a second power supply end and a third power supply end, and is configured to write a voltage provided by the second power supply end to the first pull-down control node when at least one of a voltage at the first pull-up node and a voltage at the second pull-up node is in a valid level state, and write a valid level signal to the first pull-down control node when the voltage at the first pull-up node and the voltage at the second pull-up node are both in an invalid level state and the third power supply end provides a valid level signal; The second control sub-circuit is connected with the first pull-down control node, the first pull-up node, the second pull-up node, the first pull-down node, the second power supply end and the third power supply end, and is configured to write a valid level signal to the first pull-down node when a voltage at the first pull-down control node is in a valid level state, and write a voltage provided by the second power supply end to the first pull-down node when at least one of a voltage at the first pull-up node and a voltage at the second pull-up node is in a valid level state; The third control sub-circuit is connected with the first pull-down node, the second power supply end and a fourth power supply end, and is configured to write a voltage provided by the second power supply end to the first pull-down node when the fourth power supply end provides a valid level signal; The second pull-down control circuit is further connected with the first pull-up node, and the second pull-down control circuit comprises: The fourth control sub-circuit is connected with the first pull-up node, the second pull-up node, a second pull-down control node, a second power supply end and a fourth power supply end, and is configured to write a voltage provided by the second power supply end to the second pull-down control node when at least one of a voltage at the first pull-up node and a voltage at the second pull-up node is in a valid level state, and write a valid level signal to the second pull-down control node when the voltage at the first pull-up node and the voltage at the second pull-up node are both in an invalid level state and the fourth power supply end provides a valid level signal; a fifth control sub-circuit, connected with the second pull-down control node, the first pull-up node, the second pull-up node, the second pull-down node, the second power terminal and the fourth power terminal, configured to write a valid level signal to the second pull-down node when the voltage at the second pull-down control node is at a valid level state, and write the voltage provided by the second power terminal to the second pull-down node when at least one of the voltage at the first pull-up node and the voltage at the second pull-up node is at a valid level state; a sixth control sub-circuit, connected with the second pull-down node, the second power terminal and the third power terminal, configured to write the voltage provided by the second power terminal to the second pull-down node when the third power terminal provides a valid level signal.

2. The shift register cell of claim 1, wherein, Further comprising: a first cascade output circuit, connected with the first pull-up node, the first pull-down node, the first clock signal input terminal, the second power terminal and the first cascade output terminal, configured to write the signal provided by the first clock signal input terminal to the first cascade output terminal in response to the control of the valid level signal at the first pull-up node, and write the voltage provided by the fifth power terminal to the first cascade output terminal in response to the control of the valid level signal at the first pull-down node.

3. The shift register cell of claim 1, wherein, The second power terminal is insulated from the fifth power terminal; The voltage provided by the second power terminal is greater than the voltage provided by the fifth power terminal.

4. The shift register cell of claim 1, wherein, Further comprising: a first cascade output circuit, connected with the first pull-up node, the first pull-down node, the first clock signal input terminal, the second power terminal and the first cascade output terminal, configured to write the signal provided by the first clock signal input terminal to the first cascade output terminal in response to the control of the valid level signal at the first pull-up node, and write the voltage provided by the fifth power terminal to the first cascade output terminal in response to the control of the valid level signal at the first pull-down node; a second cascade output circuit, connected with the second pull-up node, the second pull-down node, the second clock signal input terminal, the second power terminal and the second cascade output terminal, configured to write the signal provided by the second clock signal input terminal to the second cascade output terminal in response to the control of the valid level signal at the second pull-up node, and write the voltage provided by the fifth power terminal to the first cascade output terminal in response to the control of the valid level signal at the second pull-down node; The first cascade output terminal is connected with the second cascade signal input terminal, and the second cascade output terminal is connected with the first reset signal input terminal.

5. The shift register cell of claim 1, wherein, The first drive output circuit is further connected with the second pull-down node, and the first drive output circuit is further configured to write the voltage provided by the fifth power terminal to the first drive output terminal in response to the control of the valid level signal at the second pull-down node; The second driving output circuit is also connected with the first pull-down node, and the second driving output circuit is configured to write the voltage provided by the fifth power terminal to the second driving output terminal in response to the control of the valid level signal at the first pull-down node.

6. The shift register unit of any one of claims 1 to 5, wherein, The first output reset circuit comprises a fourth transistor. The control electrode of the fourth transistor is connected with the first reset signal input terminal, the first electrode of the fourth transistor is connected with the first driving output terminal, and the second electrode of the fourth transistor is connected with the fifth power terminal.

7. A gate drive method characterized by, The gate driving method is based on a shift register unit, the shift register unit adopts any one of the shift register units in claims 1-6, and the gate driving method comprises: In the pre-charging stage, the first pre-charging reset circuit writes the voltage provided by the first power terminal to the first pull-up node in response to the control of the valid level signal provided by the first cascade signal input terminal, so as to pre-charge the first pull-up node; In the output stage, the first driving output circuit writes the signal provided by the first clock signal input terminal to the first driving output terminal in response to the control of the valid level signal at the first pull-up node; In the reset stage, the first pre-charging reset circuit writes the voltage provided by the second power terminal to the first pull-up node in response to the control of the valid level signal provided by the first reset signal input terminal, so as to reset the first pull-up node, and the first output reset circuit writes the voltage provided by the fifth power terminal to the first driving output terminal in response to the control of the valid level signal provided by the first reset signal input terminal, so as to reset the first driving output terminal; In the noise reduction stage, the first pull-down control circuit writes the valid level signal to the first pull-down node when the third power terminal provides the valid level signal and the voltage at the first pull-up node is in the non-valid level state, and writes the non-valid level signal to the first pull-down node when the fourth power terminal provides the valid level signal.

8. A gate drive circuit, characterized by The gate driving circuit comprises: A plurality of cascaded shift register units, at least one of the shift register units adopts any one of the shift register units in claims 1-6.

9. A display substrate, characterized in that, The gate driving circuit comprises: The display substrate comprises:

10. A display device, characterized by comprising: The display substrate comprises: ​

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