Pixel circuit, driving method thereof and display panel

Abstract

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving module, a first voltage writing module, a second voltage writing module, a coupling module and a light-emitting module. The second voltage writing module is connected with the first end of the coupling module. The second end of the coupling module is connected with the control end of the driving module. The first reference voltage is transmitted to the first end of the coupling module in the data writing stage, and the second reference voltage is transmitted to the first end of the coupling module in the voltage adjusting stage. The coupling module is used for adjusting the voltage of the control end of the driving module according to the first reference voltage and the second reference voltage. The driving module is used for driving the light-emitting module to emit light in the light-emitting stage. In a display period, the voltage adjusting stage is located after the data writing stage. The scheme can adjust the data voltage, and is beneficial to reducing the power consumption of the display driving chip.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have become a research hotspot in the field due to their low power consumption, low production cost, and self-emissive characteristics.

[0003] Display panels typically include pixel circuits, which consist of driving transistors and light-emitting elements. Data voltage manages the current of the driving transistors, thus influencing the current flowing through the light-emitting elements and controlling the brightness. However, the existing pixel circuit architecture tends to increase the power consumption of the display driver integration chip (DDIC), failing to meet market demands. Summary of the Invention

[0004] This invention provides a pixel circuit and its driving method, as well as a display panel, to reduce the power consumption of the display driver chip.

[0005] According to one aspect of the present invention, a pixel circuit is provided, comprising: a driving module, a first voltage writing module, a second voltage writing module, a coupling module, and a light-emitting module;

[0006] The first voltage writing module is used to write the data voltage to the control terminal of the drive module during the data writing stage;

[0007] The second voltage writing module is connected to the first end of the coupling module, and the second end of the coupling module is connected to the control end of the drive module. The second voltage writing module is used to transmit the first reference voltage to the first end of the coupling module at least during the data writing phase, and to transmit the second reference voltage to the first end of the coupling module during the voltage adjustment phase. The coupling module is used to adjust the voltage of the control end of the drive module according to the first reference voltage and the second reference voltage.

[0008] The driving module and the light-emitting module are connected between the first power line and the second power line. The driving module is used to drive the light-emitting module to emit light during the light-emitting phase. In one display cycle, the voltage adjustment phase is located after the data writing phase.

[0009] Optionally, the first reference voltage satisfies: 0 ≤ VREFP1 < VREFP2; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage;

[0010] Optionally, the second reference voltage is the same as the first power supply voltage transmitted on the first power supply line.

[0011] Optionally, the first reference voltage satisfies: VREFP2 < VREFP1; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage;

[0012] Optionally, the second reference voltage is the same as the first power supply voltage transmitted on the first power supply line.

[0013] Optionally, the second voltage writing module includes a first switching unit and a second switching unit;

[0014] The control terminal of the first switching unit and the control terminal of the first voltage writing module are both connected to the first scan signal line. The first terminal of the first switching unit is connected to the first reference voltage signal line to access the first reference voltage. The second terminal of the first switching unit is connected to the first terminal of the coupling module.

[0015] The control terminal of the second switching unit is connected to the second scanning signal line, the first terminal of the second switching unit is connected to the second reference voltage signal line to access the second reference voltage, and the second terminal of the second switching unit is connected to the first terminal of the coupling module.

[0016] Optionally, the first switching unit includes a first transistor, and the second switching unit includes a second transistor; the gate of the first transistor is the control terminal of the first switching unit, the first electrode of the first transistor is the first terminal of the first switching unit, the second electrode of the first transistor is the second terminal of the first switching unit, the gate of the second transistor is the control terminal of the second switching unit, the first electrode of the second transistor is the first terminal of the second switching unit, and the second electrode of the second transistor is the second terminal of the second switching unit.

[0017] Optionally, it also includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is connected between the first power line and the first end of the drive module, and the second light-emitting control unit is connected between the second end of the drive module and the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line, and the control terminals of the first and second light-emitting control units are both connected to the light-emitting control signal line.

[0018] Optionally, the light emission control signal line is multiplexed as a second scan signal line;

[0019] Optionally, the first light-emitting control unit includes a third transistor, and the second light-emitting control unit includes a fourth transistor. The gates of the third transistor and the fourth transistor are both connected to the light-emitting control signal line. The first electrode of the third transistor is connected to the first power supply line, and the second electrode of the third transistor is connected to the first end of the driving module. The first electrode of the fourth transistor is connected to the second end of the driving module, and the second electrode of the fourth transistor is connected to the first end of the light-emitting module.

[0020] Optionally, the pixel circuit further includes: a storage module, which is connected to the control terminal of the driving module and is used to store the voltage of the control terminal of the driving module;

[0021] The pixel circuit also includes a compensation module; the first voltage writing module is connected between the data line and the first end of the driving module, and the compensation module is connected between the second end of the driving module and the control end. The compensation module is used to perform threshold compensation on the driving module during the data writing stage.

[0022] Optionally, the driving module includes a fifth transistor, the first voltage writing module includes a sixth transistor, and the compensation module includes a seventh transistor. The first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the first terminal of the fifth transistor, the gate of the sixth transistor is connected to the first scan signal line, the gate of the seventh transistor is connected to the first scan signal line, the first terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and the second terminal of the seventh transistor is connected to the gate of the fifth transistor. The first terminal of the fifth transistor is the first terminal of the driving module, the second terminal of the fifth transistor is the second terminal of the driving module, and the gate of the fifth transistor is the control terminal of the driving module.

[0023] Optionally, the storage module includes a first capacitor, the coupling module includes a second capacitor, the first terminal of the first capacitor is connected to a first power line, the second terminal of the first capacitor is connected to the control terminal of the drive module, the first terminal of the second capacitor is connected to the output terminal of the second voltage writing module, and the second terminal of the second capacitor is connected to the control terminal of the drive module.

[0024] Optionally, the pixel circuit further includes a first initialization module and a second initialization module. The first terminal of the first initialization module is connected to the first initialization signal line, the second terminal of the first initialization module is connected to the control terminal of the driving module, and the control terminal of the first initialization module is connected to the third scan signal line. The first terminal of the second initialization module is connected to the second initialization signal line, the second terminal of the second initialization module is connected to the first terminal of the light-emitting module, the second terminal of the light-emitting module is connected to the second power supply line, and the control terminal of the second initialization module is connected to the fourth scan signal line.

[0025] Optionally, the third scan signal line is multiplexed as the fourth scan signal line;

[0026] Optionally, the first initialization signal line is multiplexed as the second initialization signal line;

[0027] Optionally, the first initialization module includes an eighth transistor, and the second initialization module includes a ninth transistor. The gate of the eighth transistor is the control terminal of the first initialization module, the first electrode of the eighth transistor is the first terminal of the first initialization module, and the second electrode of the eighth transistor is the second terminal of the first initialization module. The gate of the ninth transistor is the control terminal of the second initialization module, the first electrode of the ninth transistor is the first terminal of the second initialization module, and the second electrode of the ninth transistor is the second terminal of the second initialization module.

[0028] According to another aspect of the present invention, a driving method for a pixel circuit is provided. The pixel circuit includes a driving module, a first voltage writing module, a second voltage writing module, a coupling module, a storage module, and a light-emitting module. The second voltage writing module is connected to a first end of the coupling module, the second end of the coupling module is connected to a control end of the driving module, the storage module is connected to the control end of the driving module, and the driving module and the light-emitting module are connected between a first power line and a second power line.

[0029] The driving methods include:

[0030] During the voltage writing phase, the first voltage writing module is controlled to write the data voltage to the control terminal of the drive module and the storage module, and the second voltage writing module is controlled to transmit the first reference voltage to the first terminal of the coupling module.

[0031] During the voltage regulation phase, the control second voltage writing module transmits the second reference voltage to the first terminal of the coupling module, so that the coupling module adjusts the voltage of the control terminal of the drive module according to the first reference voltage and the second reference voltage.

[0032] During the light-emitting stage, the control and driving module drives the light-emitting module to emit light.

[0033] Optionally, during the voltage regulation phase, the step of controlling the second voltage writing module to transmit the second reference voltage to the first terminal of the coupling module, so that the coupling module adjusts the voltage at the control terminal of the driving module according to the first reference voltage and the second reference voltage, includes:

[0034] During the voltage regulation phase, the control second voltage writing module transmits the second reference voltage to the first terminal of the coupling module. The coupling module increases the voltage at the control terminal of the drive module according to the difference between the second reference voltage and the first reference voltage. The first reference voltage satisfies: 0≤VREFP1<VREFP2; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage.

[0035] Alternatively, during the voltage regulation phase, the control second voltage writing module transmits the second reference voltage to the first terminal of the coupling module, and the voltage at the control terminal of the drive module is reduced by the difference between the second reference voltage and the first reference voltage of the coupling module; the first reference voltage satisfies: VREFP2 < VREFP1; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage;

[0036] Optionally, the voltage regulation stage and the light emission stage can be performed simultaneously.

[0037] According to another aspect of the present invention, a display panel is provided, including the pixel circuit provided in any embodiment of the present invention.

[0038] The technical solution provided by this invention involves setting a coupling module at the control terminal of the driving module. During the data writing phase, a first voltage writing module writes a data voltage to the control terminal of the driving module and the second terminal of the coupling module, and a second voltage writing module writes a first reference voltage to the first terminal of the coupling module. Then, during the voltage adjustment phase, the second voltage writing module writes a second reference voltage to the first terminal of the coupling module to change the potential of the first terminal of the coupling module, thereby coupling and changing the potential of the control terminal of the driving module. The voltage change at the control terminal of the driving module is determined by the difference between the first reference voltage and the second reference voltage. Therefore, during the data writing process, the voltage value of the data transmitted on the data line can be reduced, so that when achieving low grayscale display, the data voltage output by the display driver chip is far from its output upper limit, effectively reducing the maximum value of the output data voltage, thereby helping to reduce the power consumption of the display driver chip.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0043] Figure 3This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0048] Figure 8 A driving timing waveform diagram provided in an embodiment of the present invention;

[0049] Figure 9 Another driving timing waveform diagram provided in an embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0051] Figure 11 Another driving timing waveform diagram provided in an embodiment of the present invention;

[0052] Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0053] Figure 13 Another driving timing waveform diagram provided in an embodiment of the present invention;

[0054] Figure 14 Another driving timing waveform diagram provided in an embodiment of the present invention;

[0055] Figure 15 A flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention;

[0056] Figure 16 A flowchart of another pixel circuit driving method provided in an embodiment of the present invention;

[0057] Figure 17 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0058] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] As described in the background section, existing pixel circuit architectures typically manage the current flowing through the light-emitting element using data voltage, thereby controlling the brightness. This data voltage is provided by the display driver chip. With advancements in display technology, to achieve higher brightness, the luminous efficiency of the light-emitting element has increased, enabling it to emit brighter light with lower current. However, this has led to a corresponding increase in the data voltage required for the pixel circuit to support zero grayscale. Consequently, the maximum data voltage (VGMP) in the pixel circuit approaches the output limit of the display driver chip, increasing the chip's power consumption and failing to meet the low-power requirements of the product.

[0061] To address the aforementioned problems, this invention provides a pixel circuit to optimize the data voltage in the pixel circuit and improve the power consumption of the display driver chip. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1 The pixel circuit provided in this embodiment of the invention includes: a driving module 110, a first voltage writing module 120, a second voltage writing module 130, a coupling module 140, and a light-emitting module 160.

[0062] The first voltage writing module 120 is used to write the data voltage Vdata to the control terminal G of the drive module 110 during the data writing stage;

[0063] The second voltage writing module 130 is connected to the first end of the coupling module 140, and the second end of the coupling module 140 is connected to the control terminal G of the drive module 110. The second voltage writing module 130 is used to transmit the first reference voltage VREFP1 to the first end of the coupling module 140 during the data writing stage, and to transmit the second reference voltage VREFP2 to the first end of the coupling module 140 during the voltage adjustment stage. The coupling module 140 is used to adjust the voltage of the control terminal G of the drive module 110 according to the first reference voltage VREFP1 and the second reference voltage VREFP2.

[0064] The driving module 110 and the light-emitting module 160 are connected between the first power line L1 and the second power line L2. The driving module 110 is used to drive the light-emitting module 160 to emit light during the light-emitting stage.

[0065] Specifically, the first power line L1 is used to transmit the first power supply voltage VDD, which can be a high voltage. The second power line L2 is used to transmit the second power supply voltage VSS, which can be a low voltage. The driving module 110 and the light-emitting module 160 are connected between the first power line L1 and the second power line L2. When the connection path between the first power line L1 and the second power line L2 is open, the driving module 110 drives the light-emitting module 160 to emit light during the light-emitting phase of the display cycle according to the voltage of its control terminal G and the first terminal. A light-emitting control module 170 can be provided on this connection path to ensure the reliability of the light emission.

[0066] The pixel circuit provided in this embodiment includes at least a data writing stage, a voltage adjustment stage, and a light emission stage. Within a display cycle, the voltage adjustment stage follows the data writing stage. Here, "the voltage adjustment stage follows the data writing stage" means that the voltage adjustment stage can be between the data writing stage and the light emission stage, or it can be performed simultaneously with the light emission stage.

[0067] by Figure 1 Taking the pixel circuit shown as an example, during the data writing stage, the first voltage writing module 120 and the second voltage writing module 130 are turned on. The data voltage Vdata is written to the control terminal G of the driving module 110 and the second terminal of the coupling module 140 via the first voltage writing module 120. At the same time, the second voltage writing module 130 transmits the first reference voltage VREFP1 to the first terminal of the coupling module 140, and the voltage difference across the coupling module 140 is VREFP1 - Vdata.

[0068] During the voltage regulation phase, the second voltage writing module 130 is turned on, and the second reference voltage VREFP2 is transmitted to the first terminal of the coupling module 140 through the second voltage writing module 130. The voltage at the first terminal of the coupling module 140 jumps from the first reference voltage VREFP1 to the second reference voltage VREFP2. Under the coupling effect of the coupling module 140, the voltage change at its first terminal is coupled to the control terminal G of the drive module 110, thereby regulating the voltage at the control terminal G of the drive module 110. For example, the absolute value of the voltage change at the control terminal G of the drive module 110 compared to the voltage during the data writing phase can be equal to the absolute value of the difference between VREFP1 and VREFP2.

[0069] During the light-emitting stage, the driving module 110 generates a driving current based on the voltage of its control terminal G and the first terminal. The driving current flows through the light-emitting module 160 to drive the light-emitting module 160 to emit light.

[0070] In this embodiment, through the coupling function of the coupling module 140, after the data voltage Vdata is written to the control terminal G of the driving module 110, the voltage of the control terminal G of the driving module 110 is coupled to change the voltage of the control terminal G of the driving module 110, thereby compensating for the insufficient data voltage Vdata written to the control terminal G of the driving module 110 during the data writing stage. Therefore, during the data writing stage, a smaller data voltage Vdata can be written to the control terminal G of the driving module 110, and the voltage of the control terminal G of the driving module 110 can be adjusted by the coupling module 140, thereby changing the driving current to achieve 0 grayscale display.

[0071] The technical solution provided by this invention involves setting a coupling module at the control terminal of the driving module. During the data writing phase, a first voltage writing module writes a data voltage to the control terminal of the driving module and the second terminal of the coupling module, and a second voltage writing module writes a first reference voltage to the first terminal of the coupling module. Then, during the voltage adjustment phase, the second voltage writing module writes a second reference voltage to the first terminal of the coupling module to change the potential of the first terminal of the coupling module, thereby coupling and changing the potential of the control terminal of the driving module. The voltage change at the control terminal of the driving module is determined by the difference between the first reference voltage and the second reference voltage. Therefore, during the data writing process, the voltage value of the data transmitted on the data line can be reduced, so that when achieving low grayscale display, the data voltage output by the display driver chip is far from its output upper limit, effectively reducing the maximum value of the output data voltage, thereby helping to reduce the power consumption of the display driver chip.

[0072] In this embodiment, the luminous intensity of the light-emitting module 160 is related to the voltage of the control terminal G of the driving module 110. Taking the transistors included in the driving module 110 as P-type transistors as an example, when the voltage at the first terminal of the driving module 110 is fixed, the higher the voltage of the control terminal G of the driving module 110, the lower the driving current, and the lower the luminous intensity of the light-emitting module 160. In order to achieve low grayscale display while reducing the maximum value VGMP of the data voltage Vdata, the first reference voltage VREFP1 and the second reference voltage VREFP2 satisfy: 0 ≤ VREFP1 < VREFP2, so that the voltage of the control terminal G of the driving module 110 is coupled and increased during the voltage adjustment phase to compensate for the deficiency of insufficient charging of the control terminal G of the driving module 110 due to the small data voltage Vdata.

[0073] Optionally, the second reference voltage VREFP2 is the same as the first power supply voltage VDD transmitted on the first power supply line L1, which helps to save the number of voltage signal lines. The second voltage writing module 130 can be electrically connected to the first power supply line L1 to use the voltage of the first power supply line L1 as the second reference voltage VREFP2 of the second voltage writing module 130.

[0074] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 2 Based on the above technical solutions, optionally, in Figure 1 Based on the pixel circuit shown, the pixel circuit also includes a storage module 150, which is connected to the control terminal G of the driving module 110 and is used to store the voltage of the control terminal G of the driving module 110.

[0075] Continue to refer to Figure 2 Optionally, the second voltage writing module 130 includes a first switching unit 1301 and a second switching unit 1302.

[0076] The control terminal of the first switching unit 1301 is connected to the first scan signal line. Optionally, both the control terminal of the first switching unit 1301 and the control terminal of the first voltage writing module 120 are connected to the first scan signal line. The first terminal of the first switching unit 1301 is connected to the first reference voltage signal line R1 to access the first reference voltage VREFP1, and the second terminal of the first switching unit 1301 is connected to the first terminal of the coupling module 140; the control terminal of the second switching unit 1302 is connected to the second scan signal line, the first terminal of the second switching unit 1302 is connected to the second reference voltage signal line R2 to access the second reference voltage REFP2, and the second terminal of the second switching unit 1302 is connected to the first terminal of the coupling module 140.

[0077] The first scan signal line is used to transmit the first scan signal S1, and the second scan signal line is used to transmit the second scan signal S2. The first switching unit 1301 is used to conduct in response to the first scan signal S1 during the data writing phase, transmitting the first reference voltage VREFP1 to the first terminal of the coupling module 140. The second switching unit 1302 is used to conduct in response to the second scan signal S2 during the voltage adjustment phase, transmitting the second reference voltage VREFP2 to the first terminal of the coupling module 140. Here, the second reference voltage VREFP2 is greater than the first reference voltage VREFP1, and the second reference voltage VREFP2 can be the first power supply voltage VDD. The first power supply line L1 can be reused as the second reference voltage signal line R2, and the first terminal of the second switching unit 1302 is connected to the first power supply line L1.

[0078] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, specifically... Figure 2 The second switch module 130 in the pixel circuit shown is illustrated in a detailed schematic diagram of its device structure. (Reference) Figure 3 The first switching unit 1301 includes a first transistor M1, and the second switching unit 1302 includes a second transistor M2. The gate of the first transistor M1 is the control terminal of the first switching unit 1301, the first electrode of the first transistor M1 is the first terminal of the first switching unit 1301, and the second electrode of the first transistor M1 is the second terminal of the first switching unit 1301. The gate of the second transistor M2 is the control terminal of the second switching unit 1302, the first electrode of the second transistor M2 is the first terminal of the second switching unit 1302, and the second electrode of the second transistor M2 is the second terminal of the second switching unit 1302.

[0079] Here, both the first transistor M1 and the second transistor M2 are P-type transistors. Of course, in other embodiments, the first transistor M1 and the second transistor M2 can also be N-type transistors, or one can be a P-type transistor and the other an N-type transistor. This embodiment is only schematically illustrating the structure of a pixel circuit.

[0080] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 4Based on the above technical solutions, optionally, the light-emitting control module 170 includes a first light-emitting control unit 1701 and a second light-emitting control unit 1702. The first light-emitting control unit 1701 is connected between the first power line L1 and the first end of the drive module 110, and the second light-emitting control unit 1702 is connected between the second end of the drive module 110 and the first end of the light-emitting module 160. The second end of the light-emitting module 160 is connected to the second power line L2. The control terminals of both the first light-emitting control unit 1701 and the second light-emitting control unit 1702 are connected to the light-emitting control signal line. The light-emitting control signal line is used to transmit the light-emitting control signal EM.

[0081] The first light-emitting control unit 1701 and the second light-emitting control unit 1702 are used to turn on during the light-emitting stage so that the driving module 110 generates a driving current and transmits the driving current to the light-emitting module 160 to drive the light-emitting module 160 to emit light.

[0082] In other embodiments, the first light-emitting control unit 1701 and the second light-emitting control unit 1702 can be connected to different light-emitting control signal lines for separate control.

[0083] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5 The light emission control signal line can be reused as the second scanning signal line. That is, the control terminal of the second switching unit 1302 and the control terminal of the first light emission control unit 1701 are both connected to the light emission control signal line. The second switching unit 1302 and the first light emission control unit 1701 are turned on at the same time during the light emission stage. The voltage regulation stage coincides with the light emission stage, that is, the voltage regulation stage and the light emission stage are performed simultaneously.

[0084] Continue to refer to Figure 5 The first light-emitting control unit 1701 includes a third transistor M3, and the second light-emitting control unit 1702 includes a fourth transistor M4. The gates of the third transistor M3 and the fourth transistor M4 are both connected to the light-emitting control signal line. The first terminal of the third transistor M3 is connected to the first power supply line L1, the second terminal of the third transistor M3 is connected to the first end of the driving module 110, the first terminal of the fourth transistor M4 is connected to the second end of the driving module 110, and the second terminal of the fourth transistor M4 is connected to the first end of the light-emitting module 160.

[0085] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 6Based on the above technical solutions, the pixel circuit may optionally include a compensation module 180. The first voltage writing module 120 is connected between the data line and the first end of the driving module 110, and the compensation module 180 is connected between the second end of the driving module 110 and the control terminal G. The compensation module 180 is used to perform threshold compensation on the driving module 110 during the data writing stage.

[0086] Optionally, the pixel circuit further includes a first initialization module 191, and / or, the pixel circuit further includes a second initialization module 192. The first terminal of the first initialization module 191 is connected to a first initialization signal line, the second terminal of the first initialization module 192 is connected to the control terminal G of the drive module 110, and the control terminal of the first initialization module 191 is connected to a third scan signal line; the first terminal of the second initialization module 192 is connected to a second initialization signal line, the second terminal of the second initialization module 192 is connected to a first terminal of the light-emitting module 160, the second terminal of the light-emitting module 160 is connected to a second power supply line L2, and the control terminal of the second initialization module 192 is connected to a fourth scan signal line. The third scan signal line is used to transmit a third scan signal S3, and the fourth scan signal line is used to transmit a fourth scan signal S4.

[0087] In this embodiment, the third scan signal S3 and the fourth scan signal S4 can be the same or different; the first initialization voltage VREFN1 transmitted by the first initialization signal line and the second initialization voltage VREFN2 transmitted by the second initialization signal line can also be the same or different. The first initialization signal line and the second initialization signal line can be the same signal line. That is, the first initialization module 191 and the second initialization module 192 can be turned on simultaneously or not simultaneously, or be turned on in a time-division manner. The first initialization module 191 is used to initialize the potential of the control terminal G of the driving module 110 to the first initialization voltage VREFN1, and the second initialization module 192 is used to initialize the potential of the first terminal of the light-emitting module 160 to the second initialization voltage VREFN2.

[0088] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, specifically... Figure 6 The pixel shown is a structural schematic diagram of the device, for reference. Figure 7 The driving module 110 includes a fifth transistor M5. The first electrode of the fifth transistor M5 is the first terminal of the driving module 110, the second electrode of the fifth transistor M5 is the second terminal of the driving module 110, and the gate of the fifth transistor M5 is the control terminal of the driving module 110.

[0089] Optionally, the first voltage writing module 120 includes a sixth transistor M6, the first terminal of the sixth transistor M6 is connected to the data line, the second terminal of the sixth transistor M6 is connected to the first terminal of the driving module 110, and the gate of the sixth transistor M6 is connected to the first scan signal line.

[0090] Optionally, the compensation module 180 includes a seventh transistor M7, the gate of which is connected to the first scan signal line, the first terminal of which is connected to the second terminal of the drive module 110, and the second terminal of which is connected to the control terminal of the drive module 110.

[0091] Optionally, the storage module 150 includes a first capacitor C1, the first terminal of the first capacitor C1 is connected to the first power line L1, and the second terminal of the first capacitor C1 is connected to the control terminal of the drive module 110.

[0092] Optionally, the coupling module 140 includes a second capacitor C2. The first terminal of the second capacitor C2 is connected to the output terminal of the second voltage writing module 130, and the second terminal of the second capacitor C2 is connected to the control terminal of the driving module 110. The second terminal of the first switching unit 1301 and the second terminal of the second switching unit 1302 are connected together as the output terminal of the second voltage writing module 130. The first terminal of the first switching unit 1301 serves as the first input terminal of the second voltage writing module 130, and the first terminal of the second switching unit 1302 serves as the second input terminal of the second voltage writing module 130.

[0093] Optionally, the first initialization module 191 includes an eighth transistor M8. The gate of the eighth transistor M8 is the control terminal of the first initialization module 191, the first electrode of the eighth transistor M8 is the first terminal of the first initialization module 191, and the second electrode of the eighth transistor M8 is the second terminal of the first initialization module 191.

[0094] Optionally, the second initialization module 192 includes a ninth transistor M9. The gate of the ninth transistor M9 is the control terminal of the second initialization module 192, the first electrode of the ninth transistor M9 is the first terminal of the second initialization module 192, and the second electrode of the ninth transistor M9 is the second terminal of the second initialization module 192.

[0095] Optionally, the second end of the light-emitting module 160 can be electrically connected to the second power line L2. In this embodiment, the light-emitting module 160 may include a light-emitting diode D1, such as an LED, OLED, or micro-LED. The first end of the light-emitting module 160 can be the anode. The second end of the light-emitting module 160 can be the cathode.

[0096] Optionally, the first transistor M1 to the ninth transistor M9 may be P-type transistors. Optionally, the first transistor M1 to the ninth transistor M9 may be N-type transistors. Optionally, one or more of the first transistor M1 to the ninth transistor M9 may be P-type transistors, and the rest may be N-type transistors.

[0097] Taking a scenario where all transistors are P-type transistors, Figure 8 A driving timing waveform diagram provided in this embodiment of the invention can be used for driving. Figure 7 The pixel circuit shown is a reference. Figure 7 and Figure 8 The working process of the pixel circuit provided in this embodiment of the invention includes a first initialization stage T1, a data writing stage T2, a second initialization stage T3, a voltage adjustment stage T4, and a light emission stage T5.

[0098] In the first initialization phase T1, the first scan signal S1 is at an off level (e.g., high level), the second scan signal S2 is at an off level (e.g., high level), the third scan signal S3 is at an on level (e.g., low level), the fourth scan signal S4 is at an off level (e.g., high level), and the light emission control signal EM is at an off level (e.g., high level). Therefore, the eighth transistor M8 is turned on. The first initialization voltage VREFN1 is transmitted to the gate of the fifth transistor M5 through the eighth transistor M8, thereby initializing the control terminal G of the drive module 110.

[0099] During the data writing phase T2, the first scan signal S1 is at an on level (e.g., low), the second scan signal S2 is at an off level (e.g., high), the third scan signal S3 is at an off level (e.g., high), the fourth scan signal S4 is at an off level (e.g., high), and the light emission control signal EM is at an off level (e.g., high). Therefore, the first transistor M1, the sixth transistor M6, and the seventh transistor M7 are turned on. The data voltage Vdata transmitted on the data line is written to the gate of the fifth transistor M5 via the sixth transistor M6, the fifth transistor M5, and the seventh transistor M7, realizing data writing and threshold compensation for the fifth transistor M5. The gate voltage of the fifth transistor M5 is Vdata + Vth5, where Vth5 is the threshold voltage of the fifth transistor M5, and the first capacitor C1 stores this gate voltage. Simultaneously, the first reference voltage VREFP1 is written to the first terminal (upper plate) of the second capacitor C2 through the first transistor M1, and the voltage at the second terminal of the second capacitor C2 is Vdata + Vth5.

[0100] In the second initialization phase T3, the first scan signal S1 is at an off level (e.g., high level), the second scan signal S2 is at an off level (e.g., high level), the third scan signal S3 is at an off level (e.g., high level), the fourth scan signal S4 is at an on level (e.g., low level), and the light emission control signal EM is at an off level (e.g., high level). Therefore, the ninth transistor M9 is turned on. The second initialization voltage VREFN2 is written to the first electrode (anode) of the light-emitting diode D1 via the ninth transistor M9, thus initializing the potential of the first electrode of the light-emitting diode D1.

[0101] During the voltage regulation phase T4, the first scan signal S1 is at an off level (e.g., high level), the second scan signal S2 is at an on level (e.g., low level), the third scan signal S3 is at an off level (e.g., high level), the fourth scan signal S4 is at an off level (e.g., high level), and the light emission control signal EM is at an off level (e.g., high level). Therefore, the second transistor M2 is turned on. The second reference voltage VREFP2 is transmitted to the first terminal of the second capacitor C2 via the second transistor M2. The voltage at the first terminal of the second capacitor C2 jumps from the first reference voltage VREFP1 to the second reference voltage VREFP2. Under the coupling effect of the second capacitor C2, the voltage at the second terminal of the second capacitor C2, i.e., the gate voltage of the fifth transistor M5, becomes... Where c1 is the capacitance of the first capacitor C1 and c2 is the capacitance of the second capacitor C2. Here, 0 ≤ VREFP1 < VREFP2, therefore, the gate voltage of the fifth transistor M5 increases.

[0102] During the voltage regulation phase T4, the gate voltage of the fifth transistor M5 is increased by coupling it through the second capacitor C2. Therefore, during the data writing phase T2, the maximum value VGMP of the data voltage Vdata transmitted on the data line can be appropriately reduced. Through the voltage regulation process in phase T4, the gate voltage of the fifth transistor M5 can reach the target voltage, meeting the grayscale display requirements. This solution helps reduce the power consumption of the display driver chip used to output the data voltage Vdata.

[0103] Optionally, in this embodiment, the capacitance value of the second capacitor C2 can be less than the capacitance value of the first capacitor C1 to prevent the coupling difference of the second capacitor C2 under different coupling voltages from adversely affecting the storage of the first capacitor C1. Optionally, the capacitance value of the second capacitor C2 can be greater than or equal to the capacitance value of the first capacitor C1, and can be set as needed.

[0104] During the light-emitting stage T5, the first scan signal S1 is at a shutdown level (e.g., high level), the second scan signal S2 is at a shutdown level (e.g., high level), the third scan signal S3 is at a shutdown level (e.g., high level), the fourth scan signal S4 is at a shutdown level (e.g., high level), and the light-emitting control signal EM is at a conduction level (e.g., low level). Therefore, the third transistor M3 and the fourth transistor M4 are turned on, and the first power supply voltage VDD is transmitted to the first terminal of the fifth transistor M5. The fifth transistor M5 generates a driving current I based on the voltage between its gate and its first terminal, driving the light-emitting diode D1 to emit light. The driving current I can be expressed as:

[0105]

[0106] Where μ is the electron mobility of the fifth transistor M5, Cox is the channel capacitance per unit area of ​​the fifth transistor M5, and W / L is the aspect ratio of the fifth transistor M5.

[0107] Figure 9 Another driving timing waveform diagram provided in this embodiment of the invention can be used for driving. Figure 7 The pixel circuit shown is, and Figure 8 The driving timing shown is different, Figure 9 In the driving timing shown, the voltage regulation stage T4 is located between the data writing stage T2 and the second initialization stage T3. Its specific working process is similar to... Figure 8 The working process shown is the same, so it will not be described again.

[0108] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 10 The gates of the second transistor M2 and the third transistor M3 are connected to the same light-emitting control signal line, and the gates of the eighth transistor M8 and the ninth transistor M9 are connected to the third scan signal line. Figure 11 Another driving timing waveform diagram provided in this embodiment of the invention is applicable to Figure 10 The pixel circuit shown. (Reference) Figure 10 and Figure 11 The working process of the pixel circuit provided in this embodiment includes: a first initialization stage T1, a data writing stage T2, and a light emission stage T5.

[0109] In the first initialization phase T1, the first scan signal S1 is at an off level (e.g., high level), the third scan signal S3 is at an on level (e.g., low level), and the light emission control signal EM is at an off level (e.g., high level). Therefore, the eighth transistor M8 and the ninth transistor M9 are turned on. The first initialization voltage VREFN1 is transmitted through the eighth transistor M8 to the gate of the fifth transistor M5, and through the ninth transistor M9 to the first terminal of the light-emitting diode D1, thus achieving simultaneous initialization of the gate of the fifth transistor M5 and the first terminal of the light-emitting diode D1.

[0110] During the data writing phase T2, the first scan signal S1 is at an on level (e.g., low), the third scan signal S3 is at an off level (e.g., high), and the light emission control signal EM is at an off level (e.g., high). Therefore, the first transistor M1, the sixth transistor M6, and the seventh transistor M7 are turned on. The data voltage Vdata transmitted on the data line is written to the gate of the fifth transistor M5 via the sixth transistor M6, the fifth transistor M5, and the seventh transistor M7, realizing data writing and threshold compensation for the fifth transistor M5. The gate voltage of the fifth transistor M5 is Vdata + Vth5, where Vth5 is the threshold voltage of the fifth transistor M5, and the first capacitor C1 stores this gate voltage. Simultaneously, the first reference voltage VREFP1 is written to the first terminal (upper plate) of the second capacitor C2 through the first transistor M1, and the voltage at the second terminal of the second capacitor C2 is Vdata + Vth5.

[0111] During the light-emitting stage T5, the first scan signal S1 is at a shutdown level (e.g., high level), the third scan signal S3 is at a shutdown level (e.g., high level), and the light-emitting control signal EM is at a conduction level (e.g., low level). Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on. The second reference voltage VREFP2 is transmitted to the first terminal of the second capacitor C2 via the second transistor M2. The voltage at the first terminal of the second capacitor C2 jumps from the first reference voltage VREFP1 to the second reference voltage VREFP2. Under the coupling effect of the second capacitor C2, the voltage at the second terminal of the second capacitor C2, i.e., the gate voltage of the fifth transistor M5, becomes... Simultaneously, the first power supply voltage VDD is transmitted to the first terminal of the fifth transistor M5. The fifth transistor M5 generates a drive current based on the voltage between its gate and the first terminal, driving the light-emitting diode D1 to emit light.

[0112] It should be noted that the fifth transistor M5 is a driving transistor. This solution is also applicable when the characteristics of the fifth transistor M5 change due to its own or external factors, resulting in an increase in the black-state voltage.

[0113] In another optional embodiment provided by the present invention, the first reference voltage VREFP1 and the second reference voltage VREFP2 can also satisfy: VREFP2 < VREFP1. Specifically, in the voltage adjustment stage T4, the second reference voltage VREFP2 is transmitted to the first terminal of the second capacitor C2 via the second transistor M2, and the voltage at the first terminal of the second capacitor C2 jumps from the first reference voltage VREFP1 to the second reference voltage VREFP2. Since the first reference voltage VREFP1 is greater than the second reference voltage VREFP2, the gate voltage of the fifth transistor M5 decreases under the coupling effect of the second capacitor C2, thereby increasing the luminous brightness of the light-emitting diode D1. For example, in high grayscale display, the data voltage Vdata needs to be 0V, but the lower limit of the data voltage Vdata output by the display driver chip is 0.2V, which cannot meet the requirement. Therefore, by setting the first reference voltage VREFP1 to be greater than the second reference voltage VREFP2, the gate voltage of the fifth transistor M5 can be coupled down, so that the gate voltage of the fifth transistor M5 reaches 0V. Here, the condition that the first reference voltage VREFP1 is greater than the second reference voltage VREFP2 also applies to the technical solutions provided in any of the above embodiments.

[0114] The technical solution provided by the embodiments of the present invention can effectively manage the voltage range (expand or shrink) of the data voltage Vdata by setting the magnitude relationship between the first reference voltage VREFP1 and the second reference voltage VREFP2, and can adapt to a wider range of driving transistor characteristics.

[0115] Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, and... Figure 10 The difference in the pixel circuits shown is that... Figure 12 The pixel circuit shown has no storage module. Optionally, the second voltage writing module 130 is used to transmit the first reference voltage VREFP1 to the first terminal of the coupling module 140 during the first initialization phase and the data writing phase, and to transmit the second reference voltage VREFP2 to the first terminal of the coupling module 140 during the voltage adjustment phase. The first initialization module 191 is used to initialize the potential of the control terminal G of the drive module 110 to the first initialization voltage VREFN1 during the first initialization phase.

[0116] exist Figure 12 In the middle, the control terminal of the first switching unit 1301 is connected to the fourth scan line to respond to the fourth scan signal S4 transmitted on the fourth scan line. Figure 13 Another driving timing waveform diagram provided in this embodiment of the invention is applicable to Figure 12 The pixel circuit shown. (Reference) Figure 12 and Figure 13The working process of the pixel circuit provided in this embodiment includes: a first initialization stage T1, a data writing stage T2, and a light emission stage T5.

[0117] In the first initialization phase T1, the first scan signal S1 is at an off level (e.g., high level), the third scan signal S3 is at an on level (e.g., low level), the light emission control signal EM is at an off level (e.g., high level), and the fourth scan signal S4 is at an on level (e.g., low level). Therefore, the first transistor M1, the eighth transistor M8, and the ninth transistor M9 are turned on. The first initialization voltage VREFN1 is transmitted through the eighth transistor M8 to the gate of the fifth transistor M5, and through the ninth transistor M9 to the first terminal of the light-emitting diode D1, achieving simultaneous initialization of the gate of the fifth transistor M5 and the first terminal of the light-emitting diode D1. Simultaneously, the first reference voltage VREFP1 is transmitted through the first transistor M1 to the first terminal of the second capacitor C2, maintaining a fixed voltage difference across the second capacitor C2.

[0118] During the data writing phase T2, the first scan signal S1 is at an on level (e.g., low), the third scan signal S3 is at an off level (e.g., high), the light emission control signal EM is at an off level (e.g., high), and the fourth scan signal S4 is at an on level (e.g., low). Therefore, the first transistor M1, the sixth transistor M6, and the seventh transistor M7 are turned on. The data voltage Vdata transmitted on the data line is written to the gate of the fifth transistor M5 via the sixth transistor M6, the fifth transistor M5, and the seventh transistor M7, thus realizing data writing and threshold compensation for the fifth transistor M5. The gate voltage of the fifth transistor M5 is Vdata + Vth5, where Vth5 is the threshold voltage of the fifth transistor M5, and the second capacitor C2 stores this gate voltage.

[0119] During the light-emitting stage T5, the first scan signal S1 is at a turn-off level (e.g., high level), the third scan signal S3 is at a turn-off level (e.g., high level), the light-emitting control signal EM is at a turn-on level (e.g., low level), and the fourth scan signal S4 is at a turn-off level (e.g., high level). Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on. The second reference voltage VREFP2 is transmitted to the first terminal of the second capacitor C2 via the second transistor M2. The voltage at the first terminal of the second capacitor C2 jumps from the first reference voltage VREFP1 to the second reference voltage VREFP2. Under the coupling effect of the second capacitor C2, the voltage at the second terminal of the second capacitor C2, i.e., the gate voltage of the fifth transistor M5, becomes... Simultaneously, the first power supply voltage VDD is transmitted to the first terminal of the fifth transistor M5. The fifth transistor M5 generates a drive current based on the voltage between its gate and its first terminal, driving the light-emitting diode D1 to emit light. The drive current I can be expressed as:

[0120]

[0121] Figure 14 Another driving timing waveform diagram provided in this embodiment of the invention is also applicable to... Figure 12 The pixel circuit shown can be referenced for its specific working process. Figure 13 The working process of the timing sequence shown will not be described in detail here.

[0122] Optionally, embodiments of the present invention also provide a method for driving a pixel circuit. Figure 15 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, combined with... Figure 1 and Figure 15 The driving method includes:

[0123] S110. During the voltage writing stage, the first voltage writing module is controlled to write the data voltage to the control terminal of the drive module, and the second voltage writing module is controlled to transmit the first reference voltage to the first terminal of the coupling module.

[0124] S120. During the voltage regulation phase, the control second voltage writing module transmits the second reference voltage to the first end of the coupling module, so that the coupling module adjusts the voltage of the control end of the drive module according to the first reference voltage and the second reference voltage.

[0125] S130. During the light-emitting stage, the control drive module drives the light-emitting module to emit light.

[0126] The technical solution provided by this invention involves setting a coupling module at the control terminal of the driving module. During the data writing phase, a first voltage writing module writes a data voltage to the control terminal of the driving module and the second terminal of the coupling module, and a second voltage writing module writes a first reference voltage to the first terminal of the coupling module. Then, during the voltage adjustment phase, the second voltage writing module writes a second reference voltage to the first terminal of the coupling module to change the potential of the first terminal of the coupling module, thereby coupling and changing the potential of the control terminal of the driving module. The voltage change at the control terminal of the driving module is determined by the difference between the first reference voltage and the second reference voltage. Therefore, during the data writing process, the voltage value of the data transmitted on the data line can be reduced, so that when achieving low grayscale display, the data voltage output by the display driver chip is far from its output upper limit, effectively reducing the maximum value of the output data voltage, thereby helping to reduce the power consumption of the display driver chip.

[0127] Figure 16 A flowchart of another pixel circuit driving method provided in an embodiment of the present invention is shown below. Figure 16 Based on the above technical solution, step S120 may optionally include:

[0128] S1201. During the voltage regulation phase, the control second voltage writing module transmits the second reference voltage to the first terminal of the coupling module. The coupling module then increases the voltage at the control terminal of the drive module based on the difference between the second reference voltage and the first reference voltage. The first reference voltage satisfies: 0 ≤ VREFP1 < VREFP2; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage.

[0129] Alternatively, step S120 specifically includes:

[0130] S1202. During the voltage regulation phase, the control second voltage writing module transmits the second reference voltage to the first terminal of the coupling module, and reduces the voltage at the control terminal of the drive module by the difference between the second reference voltage and the first reference voltage of the coupling module. The first reference voltage satisfies: VREFP2 < VREFP1; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage.

[0131] Optionally, in this embodiment, the voltage regulation stage and the light emission stage are performed simultaneously.

[0132] Optionally, before the data writing stage, the method further includes: in the first initialization stage, the first initialization module 191 initializes the potential of the control terminal G of the drive module 110 to the first initialization voltage VREFN1.

[0133] Optionally, during the first initialization phase, the second voltage writing module 130 transmits the first reference voltage VREFP1 to the first terminal of the coupling module 140.

[0134] The specific working principle of the pixel circuit driving method provided in this embodiment can be found in the relevant description of the pixel circuit in the above embodiments. It also has the beneficial effects described in any of the above embodiments, and will not be repeated here.

[0135] Optionally, embodiments of the present invention also provide a display panel including the pixel circuit provided in the above embodiments, and therefore the display panel also has the beneficial effects described in any of the above embodiments. Figure 17 This is a schematic diagram of a display panel provided in an embodiment of the present invention. In this embodiment, the display panel can be applied to, for example... Figure 17 The mobile phone panel shown can also be applied to any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not make any special limitations on this.

[0136] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0137] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: The module includes a driver module, a first voltage writing module, a second voltage writing module, a compensation module, a coupling module, and a light-emitting module. The first voltage writing module is used to write the data voltage to the control terminal of the driving module during the data writing stage; the first voltage writing module is connected between the data line and the first terminal of the driving module, and the compensation module is connected between the second terminal of the driving module and the control terminal. The compensation module is used to perform threshold compensation on the driving module during the data writing stage. The second voltage writing module is connected to the first end of the coupling module, and the second end of the coupling module is connected to the control end of the driving module. The second voltage writing module is used to transmit a first reference voltage to the first end of the coupling module during the data writing stage, and to transmit a second reference voltage to the first end of the coupling module during the voltage adjustment stage. The coupling module is used to adjust the voltage of the control end of the driving module according to the first reference voltage and the second reference voltage. The driving module and the light-emitting module are connected between the first power line and the second power line. The driving module is used to drive the light-emitting module to emit light during the light-emitting phase. Within a display cycle, the operation of the pixel circuit further includes a second initialization phase. The voltage adjustment phase is located after the data writing phase, and the second initialization phase is located between the data writing phase and the voltage adjustment phase. In the case of low grayscale display, the voltage value of the data voltage transmitted on the data line is reduced during the data writing process so that the data voltage output by the display driver chip is far away from the output upper limit of the display driver chip. And / or, in the case of high grayscale display, the data voltage output by the display driver chip is the lower limit of the output of the display driver chip.

2. The pixel circuit according to claim 1, characterized in that, In the case of low grayscale display, the first reference voltage satisfies: 0≤VREFP1<VREFP2; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage; The driving module includes a fifth transistor, which is a P-type transistor.

3. The pixel circuit according to claim 2, characterized in that, The second reference voltage is the same as the first power supply voltage transmitted on the first power supply line.

4. The pixel circuit according to claim 1, characterized in that, In the case of high grayscale display, the first reference voltage satisfies: VREFP2 < VREFP1; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage; The driving module includes a fifth transistor, which is a P-type transistor.

5. The pixel circuit according to claim 4, characterized in that, The second reference voltage is the same as the first power supply voltage transmitted on the first power supply line.

6. The pixel circuit according to claim 1, characterized in that, The second voltage writing module includes a first switching unit and a second switching unit; The control terminal of the first switching unit and the control terminal of the first voltage writing module are both connected to the first scan signal line. The first terminal of the first switching unit is connected to the first reference voltage signal line to access the first reference voltage. The second terminal of the first switching unit is connected to the first terminal of the coupling module. The control terminal of the second switching unit is connected to the second scanning signal line, the first terminal of the second switching unit is connected to the second reference voltage signal line to access the second reference voltage, and the second terminal of the second switching unit is connected to the first terminal of the coupling module.

7. The pixel circuit according to claim 6, characterized in that, The first switching unit includes a first transistor, and the second switching unit includes a second transistor; the gate of the first transistor is the control terminal of the first switching unit, the first electrode of the first transistor is the first terminal of the first switching unit, the second electrode of the first transistor is the second terminal of the first switching unit, the gate of the second transistor is the control terminal of the second switching unit, the first electrode of the second transistor is the first terminal of the second switching unit, and the second electrode of the second transistor is the second terminal of the second switching unit.

8. The pixel circuit according to claim 7, characterized in that, It also includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is connected between the first power line and the first end of the driving module. The second light-emitting control unit is connected between the second end of the driving module and the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line. The control terminals of the first light-emitting control unit and the second light-emitting control unit are both connected to the light-emitting control signal line.

9. The pixel circuit according to claim 8, characterized in that, The light emission control signal line is multiplexed as the second scanning signal line.

10. The pixel circuit according to claim 8, characterized in that, The first light-emitting control unit includes a third transistor, and the second light-emitting control unit includes a fourth transistor. The gates of the third transistor and the fourth transistor are both connected to the light-emitting control signal line. The first terminal of the third transistor is connected to the first power supply line, and the second terminal of the third transistor is connected to the first end of the driving module. The first terminal of the fourth transistor is connected to the second end of the driving module, and the second terminal of the fourth transistor is connected to the first end of the light-emitting module.

11. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a storage module, which is connected to the control terminal of the driving module and is used to store the voltage of the control terminal of the driving module.

12. The pixel circuit according to claim 11, characterized in that, The driving module includes a fifth transistor, the first voltage writing module includes a sixth transistor, and the compensation module includes a seventh transistor. The first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the first terminal of the fifth transistor, the gate of the sixth transistor is connected to the first scan signal line, the gate of the seventh transistor is connected to the first scan signal line, the first terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and the second terminal of the seventh transistor is connected to the gate of the fifth transistor. The first terminal of the fifth transistor is the first terminal of the driving module, the second terminal of the fifth transistor is the second terminal of the driving module, and the gate of the fifth transistor is the control terminal of the driving module.

13. The pixel circuit according to claim 12, characterized in that, The storage module includes a first capacitor, and the coupling module includes a second capacitor. The first terminal of the first capacitor is connected to the first power line, and the second terminal of the first capacitor is connected to the control terminal of the driving module. The first terminal of the second capacitor is connected to the output terminal of the second voltage writing module, and the second terminal of the second capacitor is connected to the control terminal of the driving module.

14. The pixel circuit according to claim 13, characterized in that, The driving current I generated by the fifth transistor during the light-emitting phase is: ； Wherein, μ is the electron mobility of the fifth transistor, Cox is the channel capacitance per unit area of ​​the fifth transistor, W / L is the aspect ratio of the fifth transistor, Vdata is the data voltage, VDD is the first power supply voltage transmitted by the first power line, c1 is the capacitance of the first capacitor, c2 is the capacitance of the second capacitor, VREFP1 is the first reference voltage, and VREFP2 is the second reference voltage.

15. The pixel circuit according to claim 1, characterized in that, It also includes a first initialization module and a second initialization module. The first end of the first initialization module is connected to the first initialization signal line, the second end of the first initialization module is connected to the control end of the driving module, and the control end of the first initialization module is connected to the third scan signal line. The first end of the second initialization module is connected to the second initialization signal line, the second end of the second initialization module is connected to the first end of the light-emitting module, the second end of the light-emitting module is connected to the second power line, and the control end of the second initialization module is connected to the fourth scan signal line.

16. The pixel circuit according to claim 15, characterized in that, The third scan signal line is multiplexed as the fourth scan signal line.

17. The pixel circuit according to claim 15, characterized in that, The first initialization signal line is multiplexed as the second initialization signal line.

18. The pixel circuit according to claim 15, characterized in that, The first initialization module includes an eighth transistor, and the second initialization module includes a ninth transistor. The gate of the eighth transistor is the control terminal of the first initialization module, the first electrode of the eighth transistor is the first terminal of the first initialization module, and the second electrode of the eighth transistor is the second terminal of the first initialization module. The gate of the ninth transistor is the control terminal of the second initialization module, the first electrode of the ninth transistor is the first terminal of the second initialization module, and the second electrode of the ninth transistor is the second terminal of the second initialization module.

19. The pixel circuit according to claim 1, characterized in that, During the light-emitting stage, the driving module generates a driving current based on the voltage of its control terminal and the first terminal. The driving current flows through the light-emitting module to drive the light-emitting module to emit light. The voltage at the control terminal of the drive module is adjusted by the coupling module, thereby changing the drive current.

20. The pixel circuit according to claim 1, characterized in that, The coupling module includes a second capacitor, the first terminal of which is connected to the output terminal of the second voltage writing module, and the second terminal of which is connected to the control terminal of the driving module. The driving module includes a fifth transistor, the first voltage writing module includes a sixth transistor, and the compensation module includes a seventh transistor. The first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the first terminal of the fifth transistor, the gate of the sixth transistor is connected to the first scan signal line, the gate of the seventh transistor is connected to the first scan signal line, the first terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and the second terminal of the seventh transistor is connected to the gate of the fifth transistor. The first terminal of the fifth transistor is the first terminal of the driving module, the second terminal of the fifth transistor is the second terminal of the driving module, and the gate of the fifth transistor is the control terminal of the driving module. The driving current I generated by the fifth transistor during the light-emitting phase is: ； Where μ is the electron mobility of the fifth transistor, Cox is the channel capacitance per unit area of ​​the fifth transistor, W / L is the aspect ratio of the fifth transistor, Vdata is the data voltage, VDD is the first power supply voltage transmitted by the first power line, VREFP1 is the first reference voltage, and VREFP2 is the second reference voltage.

21. A pixel circuit, characterized in that, include: The module includes a driver module, a first voltage writing module, a second voltage writing module, a compensation module, a coupling module, and a light-emitting module. The first voltage writing module is used to write the data voltage to the control terminal of the driver module during the data writing phase; the first voltage writing module is connected between the data line and the first terminal of the driver module, and the compensation module is connected between the second terminal of the driver module and the control terminal. The second voltage writing module is connected to the first end of the coupling module, and the second end of the coupling module is connected to the control end of the driving module. The second voltage writing module is used to transmit a first reference voltage to the first end of the coupling module during the data writing stage, and to transmit a second reference voltage to the first end of the coupling module during the voltage adjustment stage. The coupling module is used to adjust the voltage of the control end of the driving module according to the first reference voltage and the second reference voltage. The driving module and the light-emitting module are connected between the first power line and the second power line. The driving module is used to drive the light-emitting module to emit light during the light-emitting phase. The driving module includes a fifth transistor, the first voltage writing module includes a sixth transistor, and the compensation module includes a seventh transistor. The first terminal of the sixth transistor is connected to the data line, the second terminal of the sixth transistor is connected to the first terminal of the fifth transistor, the gate of the sixth transistor is connected to the first scan signal line, the gate of the seventh transistor is connected to the first scan signal line, the first terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and the second terminal of the seventh transistor is connected to the gate of the fifth transistor. The first terminal of the fifth transistor is the first terminal of the driving module, the second terminal of the fifth transistor is the second terminal of the driving module, and the gate of the fifth transistor is the control terminal of the driving module. During the data writing phase, the sixth and seventh transistors are turned on. In one display cycle, the operation of the pixel circuit further includes a second initialization stage. The voltage adjustment stage is located after the data writing stage, and the second initialization stage is located between the data writing stage and the voltage adjustment stage. In the case of low grayscale display, the voltage value of the data voltage transmitted on the data line is reduced during the data writing process so that the data voltage output by the display driver chip is far away from the output upper limit of the display driver chip. And / or, in the case of high grayscale display, the data voltage output by the display driver chip is the lower limit of the output of the display driver chip.

22. A driving method for a pixel circuit, characterized in that, The pixel circuit includes a driving module, a first voltage writing module, a second voltage writing module, a compensation module, a coupling module, and a light-emitting module. The second voltage writing module is connected to the first end of the coupling module, and the second end of the coupling module is connected to the control end of the driving module. The driving module and the light-emitting module are connected between the first power line and the second power line. The driving method includes: During the data writing phase, the first voltage writing module is controlled to write the data voltage to the control terminal of the driving module via the compensation module, and the second voltage writing module is controlled to transmit the first reference voltage to the first terminal of the coupling module. During the voltage regulation phase, the second voltage writing module is controlled to transmit the second reference voltage to the first terminal of the coupling module, so that the coupling module adjusts the voltage of the control terminal of the driving module according to the first reference voltage and the second reference voltage. During the light-emitting phase, the driving module is controlled to drive the light-emitting module to emit light; The driving method further includes a second initialization phase, wherein within a display cycle, the voltage adjustment phase is located after the data writing phase, and the second initialization phase is located between the data writing phase and the voltage adjustment phase; In the case of low grayscale display, the voltage value of the data voltage transmitted on the data line is reduced during the data writing process so that the data voltage output by the display driver chip is far away from the upper limit of the display driver chip's output; and / or, in the case of high grayscale display, the data voltage output by the display driver chip is the lower limit of the display driver chip's output.

23. The driving method for the pixel circuit according to claim 22, characterized in that, During the voltage regulation phase, the step of controlling the second voltage writing module to transmit the second reference voltage to the first terminal of the coupling module, so that the coupling module adjusts the voltage at the control terminal of the driving module according to the first reference voltage and the second reference voltage, includes: In the case of low grayscale display, during the voltage adjustment stage, the second voltage writing module is controlled to transmit the second reference voltage to the first terminal of the coupling module. The coupling module increases the voltage of the control terminal of the drive module according to the difference between the second reference voltage and the first reference voltage. The first reference voltage satisfies: 0≤VREFP1<VREFP2; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage. or, In the case of high grayscale display, during the voltage adjustment stage, the second voltage writing module is controlled to transmit the second reference voltage to the first terminal of the coupling module. The voltage at the control terminal of the driving module is reduced by the difference between the second reference voltage and the first reference voltage of the coupling module. The first reference voltage satisfies: VREFP2 < VREFP1; where VREFP1 is the first reference voltage and VREFP2 is the second reference voltage.

24. The driving method for the pixel circuit according to claim 23, characterized in that, The voltage regulation phase and the light emission phase are performed simultaneously.

25. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-21.

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