Shift register, gate driving circuit, and display substrate

Abstract

The present disclosure provides a shift register, comprising: a voltage control circuit coupled to an output control node; at least one driving output circuit, the driving output circuit comprising: an output transistor and a capacitive structure, the output transistor and the capacitive structure are arranged along a first direction, the output transistor and the capacitive structure are coupled by a first conductive wire extending along a second direction, and the first conductive wire is coupled to a signal output line configured by the driving output circuit; the output transistor comprises a gate, a first pole and at least two second poles, the gate of the output transistor is coupled to the output control node and a first voltage writing pole of the capacitive structure, the first pole of the output transistor is coupled to a clock signal line configured by the driving output circuit, and the second pole of the output transistor is coupled to the first conductive wire; a second conductive wire is arranged between the first conductive wire and the capacitive structure, and the first conductive wire is coupled to a second voltage writing pole of the capacitive structure through the second conductive wire.

Description

[0001] This invention is a divisional application of a Chinese invention patent application with the application number 202111435505.7. Technical Field

[0002] This invention relates to the display field, and particularly to a shift register, a gate driving circuit, and a display substrate. Background Art

[0003] In the display field, the GOA (Gate Drive On Array) circuit design can achieve low cost and narrow borders and has been widely applied. In the GOA circuit design, a capacitor structure design is required. The capacitor structure generally occupies a large area and often causes a capacitor short circuit due to a small foreign particle (Particle), thereby making the GOA circuit work abnormally. Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register, including:

[0005] A voltage control circuit, coupled to an output control node, configured to control the voltage at the output control node;

[0006] At least one driving output circuit, the driving output circuit including: an output transistor and a capacitor structure, the output transistor and the capacitor structure are arranged along a first direction, the output transistor and the capacitor structure are coupled through a first wire extending along a second direction, and the first wire is coupled to a signal output line configured by the driving output circuit;

[0007] The output transistor includes a gate, a first pole, and at least two second poles. The first pole and the second poles of the output transistor are alternately arranged in the second direction. The gate of the output transistor is coupled to the output control node and a first voltage writing pole of the capacitor structure. The first pole of the output transistor is coupled to a clock signal line configured by the driving output circuit, and the second pole of the output transistor is coupled to the first wire;

[0008] A second wire is provided between the first wire and the capacitor structure, and the first wire is coupled to a second voltage writing pole of the capacitor structure through the second wire.

[0009] In some embodiments, the first wire is located between at least a part of the structure of the output transistor and the capacitor structure.

[0010] In some embodiments, the extending direction of the second wire is different from the extending direction of the first wire.

[0011] In some embodiments, the first conductive line is disposed on the same layer as the second pole of the output transistor.

[0012] In some embodiments, the second conductive line is disposed on the same layer as the first conductive line.

[0013] In some embodiments, the capacitive structure includes at least two capacitive units connected in parallel. The first voltage writing pole of the capacitive unit is coupled to the gate of the output transistor, and the second voltage writing pole of the capacitive unit is coupled to the signal output line configured by the driving output circuit.

[0014] In some embodiments, within the capacitive structure, all the capacitive units are divided into at least two capacitive unit groups arranged along the second direction, and each capacitive unit group includes at least one capacitive unit;

[0015] Each capacitive unit group is configured with a corresponding second conductive line, and the second conductive lines corresponding to different capacitive unit groups are different;

[0016] Within the capacitive unit group, the second voltage writing pole of the capacitive unit closest to the first conductive line is coupled to the first conductive line through the second conductive line corresponding to the capacitive unit group.

[0017] In some embodiments, at least two third conductive lines corresponding one-to-one to the capacitive unit groups are further disposed between the output transistor and the capacitive structure;

[0018] Within the capacitive unit group, the first voltage writing pole of the capacitive unit closest to the first conductive line is coupled to the gate of the output transistor through the third conductive line corresponding to the capacitive unit group.

[0019] In some embodiments, the third conductive line is disposed on the same layer as the gate of the output transistor.

[0020] In some embodiments, the extending direction of the third conductive line is the same as the extending direction of the second conductive line.

[0021] In some embodiments, the capacitive units within the capacitive structure are arranged in an array along the first direction and the second direction;

[0022] The first voltage writing poles of any two adjacent capacitive units in the first direction or in the second direction are coupled through a fourth conductive line located between the two adjacent capacitive units;

[0023] The second voltage writing poles of any two adjacent capacitive units in the first direction or in the second direction are coupled through a fifth conductive line located between the two adjacent capacitive units.

[0024] In some embodiments, the fourth conductive line is disposed on the same layer as the gate of the output transistor;

[0025] The fifth conductive line is disposed on the same layer as the second pole of the output transistor.

[0026] In some embodiments, the shift register includes at least two of the driving output circuits, and the at least two driving output circuits include a first driving output circuit and a second driving output circuit;

[0027] The output transistor in the first driving output circuit, the capacitive structure in the first driving output circuit, the capacitive structure in the second driving output circuit, and the output transistor in the second driving output circuit are arranged in sequence along the second direction;

[0028] The first voltage writing pole of the capacitive structure in the first driving output circuit and the first voltage writing pole of the capacitive structure in the second driving output circuit are coupled through a conductive structure located between the capacitive structure in the first driving output circuit and the capacitive structure in the second driving output circuit.

[0029] In some embodiments, the clock signal line configured by the driving output circuit includes a portion extending along the second direction, and the portion of the clock signal line extending along the second direction is located on a side of the output transistor in the corresponding driving output circuit away from the capacitive structure.

[0030] In some embodiments, the first pole in the output transistor extends along the first direction;

[0031] One end of the first pole away from the capacitive structure is connected to the portion of the clock signal line extending along the second direction.

[0032] In some embodiments, the gate of the output transistor includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion is coupled to the second portion, and the second portion is located on a side of the first portion away from the capacitive structure.

[0033] In some embodiments, the first voltage writing pole is a single-layer structure, and the first voltage writing pole is disposed on the same layer as the gate of the output transistor;

[0034] The second voltage writing pole is a single-layer structure, and the second voltage writing pole is disposed on the same layer as the second pole of the output transistor;

[0035] A light-shielding pattern is provided on one side of the output transistor, and the projection of the light-shielding pattern on the substrate at least covers the projection of the channel region of the active layer of the output transistor on the substrate.

[0036] In a second aspect, an embodiment of the present disclosure further provides a gate driving circuit, including: a plurality of cascaded shift registers, wherein at least one of the shift registers adopts the shift register provided in the first aspect as described above.

[0037] In a third aspect, an embodiment of the present disclosure further provides a display substrate, characterized by including: the gate driving circuit provided in the second aspect as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic circuit diagram of a shift register related to the present disclosure;

[0039] Figure 2 It is a layout schematic diagram of a driving output circuit in the related art;

[0040] Figure 3 It is another layout schematic diagram of a driving output circuit in the related art;

[0041] Figure 4 In the related art for Figure 2 It is a schematic diagram during the repair process of the shown driving output circuit;

[0042] Figure 5 In the related art for Figure 3 It is a schematic diagram during the repair process of the shown driving output circuit;

[0043] Figure 6A And Figure 6B They are respectively two different layout schematic diagrams of a driving output circuit in an embodiment of the present disclosure;

[0044] Figure 7 It is another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure;

[0045] Figure 8 For Figure 6A It is a schematic diagram during the repair process of the shown driving output circuit;

[0046] Figure 9 For Figure 7 It is a schematic diagram during the repair process of the shown driving output circuit;

[0047] Figure 10 For Figure 6A It is a cross-sectional schematic diagram taken along the A-A' direction in

[0048] Figure 11 is Figure 6B a schematic cross-sectional view in the B-B' direction in

[0049] Figure 12 another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure;

[0050] Figure 13 is for Figure 12 a schematic diagram during the repair process of the shown driving output circuit;

[0051] Figure 14 another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure;

[0052] Figure 15 is for Figure 14 a schematic diagram during the repair process of the shown driving output circuit;

[0053] Figure 16 another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure;

[0054] Figure 17 is for Figure 16 a schematic diagram during the repair process of the shown driving output circuit;

[0055] Figure 18 is for Figure 16 another schematic diagram during the repair process of the shown driving output circuit;

[0056] Figure 19 another circuit structure schematic diagram of the shift register involved in the present disclosure;

[0057] Figure 20A a layout schematic diagram of the first driving output circuit and the second driving output circuit in an embodiment of the present disclosure;

[0058] Figures 20B to 20G is Figure 20A a layout schematic diagram of each layer structure in

[0059] Figure 21 is for Figure 20A a layout schematic diagram during the repair process of the second driving output circuit in

[0060] Figure 22 a layout schematic diagram of the first driving output circuit and the second driving output circuit in an embodiment of the present disclosure;

[0061] Figure 23 is for Figure 22 a schematic diagram during the repair process of the shown second driving output circuit;

[0062] Figure 24 For Figure 22 a schematic diagram when performing repair processing on the second drive output circuit shown in

[0063] Figure 25 For Figure 22 a schematic diagram when performing repair processing on the second drive output circuit shown in

[0064] Figure 26 For Figure 22 a schematic diagram when performing repair processing on the second drive output circuit shown in

[0065] Figure 27 a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0066] Figure 28 a schematic circuit diagram of a pixel unit in an embodiment of the present disclosure;

[0067] Figure 29 a schematic circuit diagram of a shift register involved in an embodiment of the present disclosure;

[0068] Figure 30 For Figure 29 a working timing diagram of the shown shift register. Detailed implementation manners

[0069] To enable those skilled in the art to better understand the technical solutions of the present invention, the following provides a detailed description of a shift register, a gate driving circuit, and a display substrate provided by the present invention with reference to the accompanying drawings.

[0070] In the embodiments of the present disclosure, the transistors involved may be thin film transistors, field effect transistors, or other devices with the same or similar characteristics; since the source and drain of the transistors used are symmetric, there is no difference between the source and drain. In the embodiments of the present invention, to distinguish between the source and drain of the transistors, one of the poles is referred to as the first pole, and the other pole is referred to as the second pole.

[0071] Figure 1 a schematic circuit diagram of the shift register involved in the present disclosure, as Figure 1As shown, the shift register includes a voltage control circuit 11 and at least one driving output circuit 12. The voltage control circuit 11 is coupled to the output control node PU and is configured to control the voltage at the output control node PU; the driving output circuit 12 is coupled to the output control node PU, the corresponding clock signal line CLKD, and the corresponding signal output line OUT, and is configured to write the clock signal (as a driving signal) provided in the corresponding clock signal line CLKD to the corresponding signal output line OUT in response to the control of the voltage at the output control node PU. The driving output circuit 12 includes an output transistor Mt and a capacitive structure C1. Two voltage writing poles of the capacitive structure C1 are respectively coupled to the output control node PU and the corresponding signal output line OUT.

[0072] Among them, the output transistor Mt outputs a driving signal to the corresponding signal output line OUT through the second pole to drive the pixel unit located in the display area. Therefore, there are relatively high requirements for the driving ability of the output transistor Mt. Therefore, when designing the output transistor Mt, the output transistor Mt is often designed as a double-channel or multi-channel transistor. Correspondingly, at least two second poles for outputting a driving signal to the corresponding signal output line OUT are arranged on the output transistor Mt.

[0073] It should be noted that Figure 1 only an exemplary case where the shift register includes one driving output circuit 12 is drawn. This case only serves as an example and will not limit the technical solution of the present disclosure.

[0074] Figure 2 is a layout schematic diagram of a driving output circuit in the related art. Figure 3 is another layout schematic diagram of a driving output circuit in the related art. As Figure 2 and Figure 3 shown, in the related art, each second pole d of the output transistor Mt directly extends to be directly connected to the second voltage writing pole p2 in the capacitive structure C1; the signal output line OUT configured by the driving output circuit is directly connected to a second pole d of the output transistor Mt (see Figure 2 shown) or the second voltage writing pole p2 in the capacitive structure C1 (see Figure 3 shown).

[0075] Figure 4 is a schematic diagram of a repair process for the Figure 2 shown driving output circuit in the related art. Figure 5 is a schematic diagram of a repair process for the Figure 3 shown driving output circuit in the related art. As Figure 4 and Figure 5As shown, in the related art, when foreign particles appear on the capacitor structure C1 and cause an abnormality in the capacitor structure C1, it is difficult to repair the shift register. This is because when repairing the capacitor structure C1 with a short-circuit abnormality, it is necessary to cut off each second pole d extending to the part directly connected to the second voltage writing pole p2 in the capacitor structure C1.

[0076] After completing the cutting process, Figure 4 In the situation shown, only one second pole d directly connected to the signal output line OUT can write the driving signal to the corresponding signal output line OUT. At this time, the driving ability of the output transistor Mt obviously cannot meet the actual driving requirements; after the cutting process, Figure 5 In the situation shown, no second pole d can write the driving signal to the corresponding signal output line OUT, that is, the output transistor Mt cannot output the driving signal to the corresponding signal output line OUT. Thus, it can be seen that in the related art, when the capacitor structure C1 is abnormal, it is difficult to repair the shift register.

[0077] Figure 6A and Figure 6B are respectively two different layout schematic diagrams of a driving output circuit in an embodiment of the present disclosure, Figure 7 is another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure. As Figure 1 , Figure 6A , Figure 6B and Figure 7 shown, in the shift register provided in the embodiment of the present disclosure, the driving output circuit 12 includes: an output transistor Mt and a capacitor structure C1. The output transistor Mt and the capacitor structure C1 are arranged along the first direction X (for example, the row direction in the drawing). A first conductive line CL1 extending along the second direction Y (for example, the column direction in the drawing) is provided between the output transistor Mt and the capacitor structure C1. The first conductive line CL1 is coupled to the signal output line OUT configured for the driving output circuit.

[0078] The output transistor Mt includes a gate g, a first pole s, and at least two second poles d. The first pole s and the second poles d of the output transistor Mt are alternately arranged in the second direction Y. The gate g of the output transistor Mt is coupled to the output control node PU and the first voltage writing pole p1 of the capacitor structure C1. The first pole s of the output transistor Mt is coupled to the clock signal line CLKD configured for the driving output circuit. The second poles d of the output transistor Mt are coupled to the first conductive line CL1.

[0079] A second conductive line CL2 is provided between the first conductive line CL1 and the capacitor structure C1. The first conductive line CL1 is coupled to the second voltage writing pole p2 of the capacitor structure C1 through the second conductive line CL2.

[0080] It should be noted that Figure 6A and Figure 6B illustrate a case where the signal output line OUT configured in the drive output circuit is directly connected to a second pole d of the output transistor Mt Figure 7 illustrates a case where the signal output line OUT configured in the drive output circuit is directly connected to the second voltage writing pole in the capacitor structure C1

[0081] Figure 8 For Figure 6A is a schematic diagram during the repair process of the drive output circuit shown Figure 9 For Figure 7 is a schematic diagram during the repair process of the drive output circuit shown, as Figure 8 and Figure 9 shown, in the present disclosure, when it is necessary to repair the abnormal capacitor structure C1, it is only necessary to cut off the second conductive line CL2 located between the first conductive line CL1 and the capacitor structure C1

[0082] After cutting off the second conductive line CL2 Figure 8 and Figure 9 each second pole d of the output transistor Mt in the drive output circuit shown can write the drive signal to the corresponding signal output line OUT through the first conductive line CL1, that is, while realizing the repair of the shift register, the normal output function of the output transistor Mt can be ensured

[0083] Figure 10 For Figure 6A is a cross-sectional schematic diagram in the A-A' direction of Figure 11 For Figure 6B is a cross-sectional schematic diagram in the B-B' direction of Figure 11 shown, in some embodiments, the first conductive line CL1 and the second pole d of the output transistor Mt are arranged on the same layer

[0084] It should be noted that the two structures described in the embodiments of the present disclosure being arranged on the same layer means that the two structures are formed by patterning based on the same material thin film layer; that is to say, the two structures can be simultaneously fabricated by performing a patterning process on the same material thin film layer

[0085] In the embodiments of the present disclosure, the first conductive line CL1 and the second pole d of the output transistor Mt are arranged on the same layer. That is to say, based on the existing manufacturing process for preparing the second pole d of the output transistor Mt, only a certain adjustment needs to be made to the mask used in the manufacturing process, and the first conductive line CL1 can be simultaneously fabricated during the manufacturing process of the second pole d; therefore, the setting of the first conductive line CL1 will not result in an increase in the manufacturing process

[0086] In some embodiments, the second conductive line CL2 is disposed on the same layer as the first conductive line CL1. Similarly, based on this design, the setting of the second conductive line CL2 will not cause an increase in the manufacturing process.

[0087] See Figure 10 As shown, in some embodiments, the first voltage writing electrode p1 is a single-layer structure, and the first voltage writing electrode p1 is disposed on the same layer as the gate of the output transistor Mt; the second voltage writing electrode p2 is a single-layer structure, and the second voltage writing electrode p2 is disposed on the same layer as the second pole d of the output transistor Mt. That is, Figure 10 the capacitor structure C1 shown in

[0088] See Figure 11 As shown, in some embodiments, the first voltage writing electrode p1 is a single-layer structure, and the first voltage writing electrode p1 is disposed on the same layer as the gate of the output transistor Mt. The second voltage writing electrode p2 is a double-layer structure, and the second voltage writing electrode p2 includes a first conductive pattern p201 and a second conductive pattern p202 which are stacked. Among them, the output transistor Mt further includes an active layer act, and the second pole d of the output transistor Mt is located on the side of the gate g of the output transistor Mt facing away from the active layer of the output transistor Mt; a second insulating layer is disposed between the gate g and the active layer act, and a third insulating layer is disposed between the gate g and the first pole s / second pole d of the output transistor Mt. A light-shielding pattern BK covering at least the channel region of the active layer is disposed on the side of the active layer of the output transistor Mt facing away from the gate of the output transistor Mt, and the material of the light-shielding pattern BK includes a conductive material. At this time, the first conductive pattern p201 is disposed on the same layer as the second pole d of the output transistor Mt, the second conductive pattern p202 is disposed on the same layer as the light-shielding pattern bk, and the first conductive pattern p201 and the second conductive pattern p202 are coupled through a via. That is, Figure 11 the capacitor structure C1 shown in

[0089] In Figure 10 and Figure 11 when the areas of the first voltage writing electrodes shown are equal, Figure 11 the capacitance of the capacitor structure C1 shown in Figure 10 is about twice the capacitance of the capacitor structure C1 shown in

[0090] Figure 12 This is another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure. As shown in Figure 12As shown, different from the previous embodiments, the capacitance structure C1 in the embodiments of the present disclosure includes at least two capacitance units CU connected in parallel. The first voltage writing electrode p1 of the capacitance unit CU is coupled to the gate of the output transistor Mt, and the second voltage writing electrode p2 of the capacitance unit CU is coupled to the signal output line OUT configured by the driving output circuit.

[0091] In practical applications, the capacitance structure C1 in a driving output circuit occupies a relatively large area, while the size of foreign particles is relatively small. When a foreign particle lands on a certain capacitance structure C1, it is often necessary to cut off the entire capacitance structure C1. The inventor believes that this repair method of cutting off the entire capacitance structure C1 can be improved. Specifically, the embodiments of the present disclosure have improved the capacitance structure C1, so that the repair method changes when a foreign particle lands on the capacitance structure C1.

[0092] Specifically, in the embodiments of the present disclosure, a large-size capacitance structure C1 is designed as a structure in which at least two small-size capacitance units CU are connected in parallel. When a foreign particle lands on a certain small-size capacitance unit CU, only the corresponding partial small-size capacitance units CU need to be cut off. At this time, the uncut small-size capacitance units CU in the capacitance structure C1 can work normally.

[0093] In some embodiments, within the capacitance structure C1, all the capacitance units CU are divided into at least two capacitance unit groups CUG_1 and CUG_2 arranged along the second direction Y. Each capacitance unit group CUG_1 and CUG_2 includes at least one capacitance unit CU; each capacitance unit group CU is configured with a corresponding second conducting wire CL2, and the second conducting wires CL2 corresponding to different power unit groups CUG_1 and CUG_2 are different; within the capacitance unit group, the second voltage writing electrode p2 of the capacitance unit CU closest to the first conducting wire CL1 is coupled to the first conducting wire CL1 through the second conducting wire CL2 corresponding to the capacitance unit group.

[0094] It should be noted that Figure 12 only shows an exemplary case where the capacitance structure C1 includes two capacitance unit groups CUG_1 and CUG_2, and each unit group includes one capacitance unit CU. In the embodiments of the present disclosure, each capacitance unit group may also include a plurality of capacitance units arranged along the first direction and connected in parallel. No corresponding drawings are given for this case.

[0095] Figure 13 For Figure 12 a schematic diagram during the repair process of the shown driving output circuit, as Figure 13As shown, taking the case where foreign object particles fall into the capacitor unit within the capacitor unit group CUG_1 as an example, it is only necessary to cut off the second conductive wire CL2 corresponding to the capacitor unit group CUG_1. At this time, the second conductive wire CL2 corresponding to the capacitor unit group CUG_2 without foreign object particles falling remains intact, and the capacitor units CU in the capacitor unit group CUG_2 can operate normally.

[0096] Figure 14 This is another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure. As Figure 14 shown, in some embodiments, at least two third conductive wires CL3 corresponding one-to-one to the capacitor unit groups CUG_1 and CUG_2 are further provided between the output transistor Mt and the capacitor structure C1; the first voltage writing electrode p1 of the capacitor unit closest to the first conductive wire CL1 in the capacitor unit group is coupled to the gate of the output transistor Mt through the third conductive wire CL3 corresponding to the capacitor unit group.

[0097] In the embodiment of the present disclosure, when foreign object particles fall onto the capacitor units in a certain capacitor unit group, not only can the second conductive wire CL2 corresponding to the capacitor unit group be cut off to remove the capacitor unit group (i.e., the removal method shown in Figure 13 ), but also the third conductive wire CL3 corresponding to the capacitor unit group can be cut off to remove the capacitor unit group. The following only describes in detail the case of cutting off the third conductive wire CL3 corresponding to the capacitor unit group.

[0098] Figure 15 For Figure 14 a schematic diagram when performing maintenance on the driving output circuit shown, as Figure 15 shown, taking the case where foreign object particles fall into the capacitor units in the capacitor unit group CUG_1 as an example, it is only necessary to cut off the third conductive wire CL3 corresponding to the capacitor unit group CUG_1. At this time, the third conductive wire CL3 corresponding to the capacitor unit group CUG_2 without foreign object particles falling remains intact, and the capacitor units CU in the capacitor unit group CUG_1 can operate normally.

[0099] Of course, in some embodiments, when foreign object particles fall onto the capacitor units in a certain capacitor unit group, the second conductive wire CL2 and the third conductive wire CL3 corresponding to the capacitor unit group can be cut off simultaneously.

[0100] In some embodiments, the third conductive wire CL3 is provided on the same layer as the gate g of the output transistor Mt. Based on this design, it can be ensured that the setting of the third conductive wire CL3 will not cause an increase in the manufacturing process.

[0101] Figure 16This is another layout schematic diagram of a driving output circuit in an embodiment of the present disclosure. As Figure 16 shown, in some embodiments, the capacitor units C1_1, C1_2, C2_1, and C2_2 in the capacitor structure C1 are arranged in an array along the first direction X and the second direction Y; the first voltage writing electrodes p1 of any two adjacent capacitor units in the first direction X or in the second direction Y are coupled through a fourth conductive line CL4 located between the two adjacent capacitor units; the second voltage writing electrodes p2 of any two adjacent capacitor units in the first direction X or in the second direction Y are coupled through a fifth conductive line CL5 located between the two adjacent capacitor units.

[0102] Different from the method of removing in units of the capacitor structure C1 or the capacitor unit groups CUG_1 and CUG_2 in the previous embodiments, based on the capacitor structure C1 provided in this embodiment, the capacitor units can be removed in units. Specifically, when a foreign particle falls on a certain capacitor unit, all the conductive lines connected to the first voltage writing electrode p1 of the capacitor unit (the conductive lines connected to the first voltage writing electrode p1 of each capacitor unit at least include the fourth conductive line CL4, and the first voltage writing electrode p1 of the capacitor unit adjacent to the first conductive line CL1 in the first direction X is also connected to the third conductive line CL3. In subsequent embodiments, some capacitor units' first voltage writing electrodes p1 are also connected to a sixth conductive line CL6, and the sixth conductive line CL6 is not involved in Figure 16 this) can be cut off, and / or all the conductive lines connected to the second voltage writing electrode p2 of the capacitor unit (the conductive lines connected to the second voltage writing electrode p2 of each capacitor unit at least include the fifth conductive line CL5, and the second voltage writing electrode p2 of the capacitor unit adjacent to the gate g of the output transistor Mt in the first direction X is also connected to the second conductive line CL2).

[0103] In some embodiments, the fourth conductive line CL4 is arranged on the same layer as the gate g of the output transistor Mt; the fifth conductive line CL5 is arranged on the same layer as the second pole d of the output transistor Mt. Based on this design, it can be ensured that the settings of the fourth conductive line CL4 and the fifth conductive line CL5 do not cause an increase in the manufacturing process.

[0104] Figure 16 In

[0105] Figure 17 For Figure 16 a schematic diagram when performing maintenance processing on the shown driving output circuit. As Figure 17As shown in the figure, taking the case where a foreign particle lands on the capacitor unit C2_1 as an example, the third conductive line CL3 and the fourth conductive line CL4 connected to the first voltage writing electrode p1 of the capacitor unit C2_1 can be cut off.

[0106] Figure 18 For Figure 16 Another schematic diagram when performing maintenance processing on the driving output circuit shown in the figure. As Figure 18 shown in the figure, taking the case where a foreign particle lands on the capacitor unit C2_1 as an example, the second conductive line CL2 and the fifth conductive line CL5 connected to the second voltage writing electrode p2 of the capacitor unit C2_1 can be cut off.

[0107] Refer to Figure 17 and Figure 18 shown in the figure, the capacitor units C1_1, C1_2, and C2_2 in the capacitor structure C1 that do not have foreign particles falling into them can all operate normally.

[0108] It should be noted that when the number of driving output circuits is 1, the output control node PU in the shift register can be regarded as being located on the gate of the output transistor Mt in the driving output circuit.

[0109] Figure 19 Another schematic diagram of the circuit structure of the shift register involved in the present disclosure. Figure 20A A layout schematic diagram of the first driving output circuit and the second driving output circuit in the embodiment of the present disclosure. Figures 20B to 20G For Figure 20A the layout schematic diagram of each layer structure in and the layout schematic diagram when some layer structures are stacked. As Figures 19 to 20G shown in the figure, in some embodiments, the shift register includes at least two driving output circuits, and the at least two driving output circuits include a first driving output circuit 12 and a second driving output circuit 12'; the output transistor Mt in the first driving output circuit 12, the capacitor structure C1 in the first driving output circuit 12, the capacitor structure C1' in the second driving output circuit 12', and the output transistor Mt' in the second driving output circuit 12' are arranged in sequence along the second direction Y; the first voltage writing electrode p1 of the capacitor structure C1 in the first driving output circuit 12 and the first voltage writing electrode p1 of the capacitor structure C1' in the second driving output circuit 12' are coupled through a conductive structure D located between the capacitor structure C1 in the first driving output circuit 12 and the capacitor structure C1' in the second driving output circuit 12. At this time, the output control node PU in the shift register can be regarded as being located on the conductive structure D.

[0110] In an embodiment of the present disclosure, the signal output line OUT of the first driving output circuit 12 and the signal output line OUT' of the second driving output circuit 12 can respectively provide corresponding driving signals for two different gate lines in the display area, that is, a shift register provides driving signals for two different gate lines respectively. For specific content, refer to the description in the following embodiments. In this embodiment, only the circuit structure design of the first driving output circuit and the second driving output circuit in the shift register will be described in detail.

[0111] See Figures 20A to 20G As shown, the shift register includes a light-shielding layer LY1, a first insulating layer, an active layer LY2, a second insulating layer, a first conductive layer LY3, a third insulating layer LY4, and a second conductive layer LY5, which are sequentially arranged in a direction away from the substrate.

[0112] Figure 20B The layout of the light-shielding layer LY1 in the regions where the first driving output circuit 12 and the second driving output circuit 12' are located is shown. The material of the light-shielding layer LY1 can be a conductive material (for example, a metal material), including a shielding pattern for shielding the channel region of the transistor (in some embodiments, the channel region of the output transistor Mt can also be not provided with a shielding pattern) and a second conductive pattern p202 of the second write voltage electrode p2. Figure 20C The layout of the active layer LY2 in the regions where the first driving output circuit 12 and the second driving output circuit 12' are located is shown. The active layer LY2 of the output transistor includes an active layer pattern act of the output transistor, and the active layer pattern act of the output transistor includes a channel region pattern (also referred to as a semiconductor region pattern) and a source-drain conductive region pattern. Figure 20D The layout of the first conductive layer LY3 in the regions where the first driving output circuit 12 and the second driving output circuit 12' are located is shown. The first conductive layer LY3 includes a gate g of the output transistor, a first write voltage electrode p1, and a conductive structure D. Figure 20E The layout of the third insulating layer LY4 in the regions where the first driving output circuit 12 and the second driving output circuit 12' are located is shown, specifically showing the via distribution on the third insulating layer LY4, where some vias K1 are connected to the source-drain conductive regions on the active layer LY2, and some vias K2 are connected to the second conductive pattern p202 of the second write voltage electrode. Figure 20F The layout when the active layer LY2, the first conductive layer LY3, and the third insulating layer LY4 are stacked is shown. Figure 20G The layout of the second conductive layer LY5 in the regions where the first driving output circuit 12 and the second driving output circuit 12' are located is shown. The second conductive layer LY5 includes a first pole s of the output transistor, a second pole d of the output transistor, a first conductive line CL1, a second conductive line CL2, a signal output line OUT, and a first conductive pattern p202 of the second write voltage electrode p2.

[0113] Figure 21 When performing maintenance on the second drive output circuit in Figure 20A , a layout schematic diagram is shown as Figure 21 shown. Taking the case where foreign object particles fall into the capacitor structure C1 in the second drive output circuit 12' as an example, the second conductive wire CL2' configured for the capacitor structure C1' can be cut off. The capacitor structure C1 of the first drive output circuit 12 that has not fallen into foreign object particles can operate normally, and the capacitor structure C1 of the first drive output circuit can meet the voltage storage requirements at the output control node PU.

[0114] Figure 22 This is a layout schematic diagram of the first drive output circuit and the second drive output circuit in an embodiment of the present disclosure, as Figure 22 shown. In some embodiments, the capacitor structures C1 and C1' in the first drive output circuit 12 and the second drive output circuit 12' both include at least two capacitor units C1_1, C1_2, C2_1, C2_2 and C1_1', C1_2', C2_1', C2_2' connected in parallel. The first voltage writing electrode p1 of the capacitor unit is coupled to the gate g of the output transistor Mt, and the second voltage writing electrode p2 of the capacitor unit is coupled to the signal output lines OUT and OUT' configured for the drive output circuit. In the capacitor structure C1 of the first drive output circuit 12 and the capacitor structures C1 and C1' of the second drive output circuit 12', all the capacitor units are divided into at least two capacitor unit groups arranged along the second direction Y, and each capacitor unit group includes at least one capacitor unit.

[0115] The capacitor units in the first drive output circuit 12 are the first capacitor units C1_1, C1_2, C2_1, C2_2, and the capacitor units in the second drive output circuit 12' are the second capacitor units C1_1', C1_2', C2_1', C2_2'; any one first capacitor unit and one second capacitor unit adjacent to each other in the first direction X, the first voltage writing electrode p1 of the one first capacitor unit and the first voltage writing electrode p1 of the adjacent one second capacitor unit are electrically connected through the sixth conductive wire CL6 located between the one first capacitor unit and the one second capacitor unit; the conductive structure D includes the sixth conductive wire CL6.

[0116] In some embodiments, the sixth conductive wire CL6 is disposed on the same layer as the gate g of the output transistor Mt. Based on this design, it can be ensured that the setting of the sixth conductive wire CL6 will not lead to an increase in the manufacturing process.

[0117] It should be noted that when the shift register includes a first drive output circuit 12 and a second drive output circuit 12', the storage structure C1 in the first drive output circuit 12 and the storage structure C1' in the second drive output circuit 12' can be independently selected from, for example, those in the previous embodiments Figure 6A , Figure 6B , Figure 7 , Figure 12 , Figure 14 , Figure 16 shown in the storage structures.

[0118] Figure 22 Exemplarily, in Figure 16 , the case where both the storage structure C1 in the first drive output circuit 12 and the storage structure C1' in the second drive output circuit 12 adopt the Figure 16 capacitance structure shown in Figure 16 is given. This case only serves as an example and will not limit the technical solution of the present disclosure.

[0119] Figure 23 is a schematic diagram for the repair process of the second drive output circuit shown in Figure 22 . As shown in Figure 23 , taking the case where foreign object particles fall on the capacitor unit C1_2' as an example, the third conductive wire CL3 and the fourth conductive wire CL4 connected to the first voltage writing electrode p1 of the capacitor unit C1_2' can be cut off.

[0120] Figure 24 is a schematic diagram for the repair process of the second drive output circuit shown in Figure 22 . As shown in Figure 24 , taking the case where foreign object particles fall on the capacitor unit C1_2' as an example, the second conductive wire CL2 and the fifth conductive wire CL5 connected to the second voltage writing electrode p2 of the capacitor unit C1_2' can be cut off.

[0121] Figure 25 is a schematic diagram for the repair process of the second drive output circuit shown in Figure 22 . As shown in Figure 25 , taking the case where foreign object particles fall on the capacitor unit C1_1' as an example, the fourth conductive wire CL4 and the sixth conductive wire CL6 connected to the first voltage writing electrode p1 of the capacitor unit C1_1' can be cut off.

[0122] Figure 26 is a schematic diagram for the repair process of the second drive output circuit shown in Figure 22 . As shown in Figure 25 , taking the case where foreign object particles fall on the capacitor unit C1_1' as an example, the fifth conductive wire CL5 connected to the second voltage writing electrode p2 of the capacitor unit C1_1' can be cut off.

[0123] Embodiments of the present disclosure also provide a gate driving circuit, which includes a plurality of shift registers, and at least one of the shift registers adopts the shift register provided in the previous embodiments. For the specific description of this shift register, reference can be made to the content in the previous embodiments, and details will not be elaborated here.

[0124] Figure 27 It is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure. As Figure 27 shown, the display substrate includes a substrate 3, and the substrate 3 includes a display area 301 and a peripheral area 302 surrounding the display area 1. Pixel units PIX arranged in an array are provided in the display area 301, and a gate driving circuit GDC for providing driving signals to the pixel units PIX is provided in the peripheral area 302, and the gate driving circuit GDC can adopt the gate driving circuit provided in the previous embodiments.

[0125] Figure 28 It is a schematic circuit structure diagram of a pixel unit in an embodiment of the present disclosure. As Figure 28 shown, the pixel unit PIX includes a pixel circuit and a light-emitting device OLED. The pixel circuit includes a display switch transistor TFT (the gate is connected to the first gate line G1), a driving transistor DTFT, a sensing switch transistor STFT (the gate is connected to the second gate line G2), and a storage capacitor Cst. The pixel circuit includes at least the following two stages during operation: a pixel driving stage (including a data voltage writing process) and a pixel sensing stage (including a current reading process).

[0126] In the pixel driving stage, it is necessary to write the data voltage Vdata in the data line Data into the pixel unit; in the pixel sensing stage, it is necessary to write a test voltage Vsence into the pixel unit through the data line Data, and read the electrical signal at the drain of the driving transistor to the signal reading line Sence through the sensing switch transistor STFT. Among them, during the data writing process and the current reading process, it is necessary to write an effective level voltage to the gate of the sensing switch transistor STFT through the corresponding gate line G2.

[0127] It should be noted that the process of externally compensating the pixel units in the display substrate belongs to the conventional technology in the art, and the specific compensation process and principle will not be elaborated here.

[0128] Figure 29 It is a schematic circuit structure diagram of a shift register involved in an embodiment of the present disclosure. Figure 30 is Figure 29 a working timing diagram of the shift register shown. As Figure 29 and Figure 30As shown, to enable the shift register to provide corresponding driving signals to the first gate line G1 and the second gate line G2 respectively, the shift register must at least include the first driving output circuit and the second driving output circuit in the foregoing embodiments. Among them, the signal output line OUT configured by the first driving output circuit 7 is connected to the first gate line G1, and the signal output line OUT' configured by the second driving output circuit 8 is connected to the second gate line G2.

[0129] In some embodiments, the voltage control circuit includes: a display precharge reset circuit 3, a sense cascade circuit 1, a sense precharge reset circuit 2, an inverter circuit 4, a first output reset circuit 5, and a second output reset circuit 6. The sense cascade circuit 1 and the sense precharge reset circuit 2 are coupled at a sense cascade node H. The display precharge reset circuit 3, the sense precharge reset circuit 2, the first driving output circuit 7, and the second driving output circuit 8 are coupled at a voltage control node PU. The inverter circuit 4, the first output reset circuit 5, and the second output reset circuit 6 are coupled at a pull-down node PD. The first output reset circuit 5 is further coupled to the signal output line OUT configured by the first driving output circuit 7, and the second output reset circuit 6 is further coupled to the signal output line OUT' configured by the second driving output circuit 8.

[0130] The display precharge reset circuit 3 is connected to a first signal input terminal STU1, a reset signal terminal STD, a first power supply terminal, and a second power supply terminal, and is configured to write, in a display precharge stage, a first operating voltage in an active level state provided by the first power supply terminal to the voltage control node PU in response to the control of the first input signal provided by the first signal input terminal STU1, and to write, in a display reset stage, a second operating voltage in a non-active level state provided by the second power supply terminal to the voltage control node PU in response to the control of the reset signal provided by the reset signal terminal STD.

[0131] The sense cascade circuit 1 is connected to a second signal input terminal STU2 and a second clock signal terminal CLKB, and is configured to write, in a sense cascade stage, a second input signal in an active level state provided by the second signal input terminal STU2 to the sense cascade node H in response to the control of the second clock signal provided by the second clock signal terminal CLKB.

[0132] The sense precharge reset circuit 2 is connected to the first clock signal terminal CLKA, the third clock signal terminal CLKC, and the first power supply terminal, and is configured to write the third clock signal in an active level state provided by the third clock signal terminal CLKC to the voltage control node PU in response to the voltage of the sense cascade node H and the control of the first clock signal provided by the first clock signal terminal CLKA during the sense precharge phase, and write the second operating voltage in a non-active level state provided by the second power supply terminal to the voltage control node PU in response to the control of the second clock signal provided by the second clock signal terminal CLKB during the sense reset phase.

[0133] The inverter circuit 4 is configured to invert the voltage of the voltage control node PU and output the inverted voltage to the pull-down node PD.

[0134] Both the first drive output circuit 7 and the second drive output circuit 8 are configured to write the clock signal provided by the corresponding clock signal line CLKD / CLKD' to the corresponding signal output line OUT / OUT' in response to the control of the voltage of the output control node PU in an active level state during the display output phase and the sense output phase.

[0135] Both the first output reset circuit 5 and the second output reset circuit 6 are configured to write the reset operating voltage in a non-active level state provided by the reset power supply terminal to the corresponding signal output line OUT / OUT' in response to the control of the voltage of the pull-down node PD in an active level state during the display reset phase and the sense reset phase.

[0136] In some embodiments, the display precharge reset circuit 3 includes: a first display transistor M1 and a second display transistor M2; in some embodiments, the inverter circuit 4 includes: a third display transistor M3, a fourth display transistor M4, and a fifth display transistor M5; in some embodiments, both the first drive output circuit 7 and the second drive output circuit 8 include a sixth display transistor M6 / M6' (i.e., the output transistor Mt described above) and a capacitive structure C1 / C1'; in some embodiments, both the first output reset circuit 5 and the second output reset circuit 6 include a seventh display transistor M7 / M7'.

[0137] In some embodiments, the sense cascade circuit 1 includes: a first sense transistor T1, and the sense precharge reset circuit 2 includes: a second sense transistor T2, a third sense transistor T3, and a fourth sense transistor T4.

[0138] The operation process of the shift register may include the following 7 stages: a sensing cascade stage t0 (in the sensing stage of the previous frame), a display pre-charge stage t1, a display output stage t2, a display reset stage t3, a sensing pre-charge stage t4, a sensing output stage t5, and a sensing reset stage t6. For the specific operation process of the shift register in each stage, it can be carried out according to Figure 30 the shown operation timing sequence, and the specific process is not described in detail here.

[0139] It should be noted that the voltage control circuit in the shift register adopts Figure 29 the situation shown in [reference], which is only an optional implementation scheme in the present disclosure and will not limit the technical solution of the present disclosure; those skilled in the art should know that the voltage control voltage in the shift register can also adopt other circuit structures, and no further examples will be described here. In addition, the number of driving output circuits in the shift register in the present disclosure can be 1, 2, 3, or even more, and the present disclosure does not limit this either.

[0140] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A shift register, characterized in that, Comprising: A voltage control circuit, coupled to an output control node, configured to control the voltage at the output control node; At least one driving output circuit, the driving output circuit comprising: an output transistor and a capacitive structure, the output transistor and the capacitive structure being arranged along a first direction, the output transistor and the capacitive structure being coupled by a first conductive line extending along a second direction, the first conductive line being coupled to a signal output line configured by the driving output circuit; The output transistor includes a gate, a first pole, and at least two second poles, the first pole and the second poles of the output transistor being alternately arranged in the second direction, the gate of the output transistor being coupled to the output control node and a first voltage writing pole of the capacitive structure, the first pole of the output transistor being coupled to a clock signal line configured by the driving output circuit, and the second poles of the output transistor being coupled to the first conductive line; A second conductive line is provided between the first conductive line and the capacitive structure, and the first conductive line is coupled to a second voltage writing pole of the capacitive structure through the second conductive line.

2. The shift register according to claim 1, characterized in that, The first conductive line is located between at least a part of the structure of the output transistor and the capacitive structure.

3. The shift register according to claim 2, characterized in that, The extending direction of the second conductive line is different from that of the first conductive line.

4. The shift register according to claim 1, characterized in that, The first conductive line and the second poles of the output transistor are arranged on the same layer.

5. The shift register according to claim 1, characterized in that, The second conductive line and the first conductive line are arranged on the same layer.

6. The shift register according to claim 1, characterized in that, The capacitive structure includes: at least two capacitive units connected in parallel, a first voltage writing pole of the capacitive unit being coupled to the gate of the output transistor, and a second voltage writing pole of the capacitive unit being coupled to a signal output line configured by the driving output circuit.

7. The shift register according to claim 6, characterized in that, Within the capacitive structure, all the capacitive units are divided into at least two capacitive unit groups arranged along the second direction, and each capacitive unit group includes at least one capacitive unit; Each capacitive unit group is configured with a corresponding second conductive line, and the second conductive lines corresponding to different capacitive unit groups are different; Within the capacitive unit group, the second voltage writing pole of the capacitive unit closest to the first conductive line is coupled to the first conductive line through the second conductive line corresponding to the capacitive unit group.

8. The shift register according to claim 7, characterized in that, At least two third conductive lines corresponding one-to-one to the capacitive unit groups are further provided between the output transistor and the capacitive structure; The first voltage writing pole of the capacitive unit closest to the first conductive line within the capacitive unit group is coupled to the gate of the output transistor through the third conductive line corresponding to the capacitive unit group.

9. The shift register according to claim 8, characterized in that, The third conductive line and the gate of the output transistor are arranged on the same layer.

10. The shift register according to claim 8, characterized in that, The extending direction of the third conductive line is the same as that of the second conductive line.

11. The shift register according to claim 7, characterized in that, The capacitive units within the capacitive structure are arranged in an array along the first direction and the second direction; The first voltage writing poles of any two adjacent capacitive units in the first direction or in the second direction are coupled by a fourth conductive line located between the two adjacent capacitive units; The second voltage writing electrodes of any two adjacent capacitor units in the first direction or in the second direction are coupled through a fifth conductive line located between the two adjacent capacitor units.

12. The shift register according to claim 11, characterized in that, The fourth conductive line is disposed on the same layer as the gate of the output transistor; The fifth conductive line is disposed on the same layer as the second pole of the output transistor.

13. The shift register according to claim 1, characterized in that, The shift register includes at least two of the driving output circuits, and the at least two driving output circuits include a first driving output circuit and a second driving output circuit; The output transistor in the first driving output circuit, the capacitor structure in the first driving output circuit, the capacitor structure in the second driving output circuit, and the output transistor in the second driving output circuit are arranged in sequence along the second direction; The first voltage writing electrode of the capacitor structure in the first driving output circuit and the first voltage writing electrode of the capacitor structure in the second driving output circuit are coupled through a conductive structure located between the capacitor structure in the first driving output circuit and the capacitor structure in the second driving output circuit.

14. The shift register according to claim 13, characterized in that, The clock signal line configured by the driving output circuit includes a portion extending along the second direction, and the portion of the clock signal line extending along the second direction is located on a side of the output transistor in the corresponding driving output circuit away from the capacitor structure.

15. The shift register according to claim 14, wherein, The first pole in the output transistor extends along the first direction; One end of the first pole away from the capacitor structure is connected to the portion of the clock signal line extending along the second direction.

16. The shift register according to claim 13, wherein, The gate of the output transistor includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion is coupled to the second portion, and the second portion is located on a side of the first portion away from the capacitor structure.

17. The shift register according to any one of claims 1 to 16, wherein, The first voltage writing electrode is a single-layer structure, and the first voltage writing electrode is disposed on the same layer as the gate of the output transistor; The second voltage writing electrode is a single-layer structure, and the second voltage writing electrode is disposed on the same layer as the second pole of the output transistor; A light-shielding pattern is disposed on one side of the output transistor, and a projection of the light-shielding pattern on the substrate at least covers a projection of a channel region of the active layer of the output transistor on the substrate.

18. A gate driving circuit, wherein, Comprising: A plurality of cascaded shift registers, wherein at least one of the shift registers is the shift register according to any one of claims 1 to 17 above.

19. A display substrate, wherein, Comprising: The gate driving circuit according to claim 18 above.

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