A ferroelectric transistor, data read-write method, model training method and device
By introducing an interface layer into the ferroelectric transistor and using specific fabrication techniques to achieve a dense connection between the channel layer and the top gate ferroelectric layer, the problems of low reliability and durability of ferroelectric transistors are solved, and the performance and storage capacity of the device are improved.
CN116189733BActive Publication Date: 2026-06-02HUAWEI TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2021-11-29
- Publication Date
- 2026-06-02
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Figure CN116189733B_ABST
Abstract
The embodiment of the application discloses a ferroelectric transistor, a data reading and writing method, a model training method and a device, and is used for improving the reliability and durability of the ferroelectric transistor. In order to solve the above technical problem, the embodiment of the application provides the following technical scheme: the ferroelectric transistor comprises a substrate, a back gate electrode, a back gate dielectric layer, a channel layer, a source electrode, a drain electrode, an interface layer, a top gate ferroelectric layer and a top gate electrode; wherein the back gate electrode is located at the bottom of the substrate; the back gate dielectric layer is located above the substrate; the channel layer is located above the back gate dielectric layer; the source electrode and the drain electrode are located on both sides above the channel layer; the interface layer is located above the channel layer; the top gate ferroelectric layer is located above the interface layer, wherein the interface layer is used for connecting the channel layer and the top gate ferroelectric layer; and the top gate electrode is located above the top gate ferroelectric layer.
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