Image sensor integrated chip and method of forming the same

Abstract

An image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed on the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connected to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. The bottom surface of the second semiconductor material region is directly above the photodiode region. Embodiments of the present application also relate to methods of forming an image sensor integrated chip.

Description

Technical Field

[0001] Embodiments of this application relate to an image sensor integrated chip and a method for forming the same. Background Technology

[0002] An image sensor is a solid-state device configured to convert incident light into an electrical signal. Image sensors operate based on the photoelectric effect, the phenomenon where electron-hole pairs are generated when incident light strikes atoms within a semiconductor matrix. The electrons and holes move in opposite directions to generate an electrical signal, which can be provided to a processor that converts the electrical signal into data. Integrated circuit chips (ICs) with image sensors are widely used in modern electronic devices such as mobile phones, security cameras, medical devices, and advanced driver assistance systems (e.g., forward collision warning (FCW), automatic emergency braking (AEB), pedestrian detection, etc.). Summary of the Invention

[0003] Some embodiments of this application provide an image sensor integrated chip, including: a photodiode region disposed within a substrate including a first semiconductor material region; a second semiconductor material region disposed on the substrate; a patterned doped layer disposed between the substrate and the second semiconductor material region; and wherein the second semiconductor material region includes a sidewall connected to a bottom surface of the second semiconductor material region, the sidewall extending through the patterned doped layer, and the bottom surface being located directly above the photodiode region.

[0004] Other embodiments of this application provide an image sensor integrated chip, comprising: a photodiode region disposed within a silicon substrate; a patterned doped silicon layer disposed on the silicon substrate, the patterned doped silicon layer having sidewalls directly above the photodiode region; a germanium region disposed on the patterned doped silicon layer, wherein the germanium region includes a protrusion extending outward from the lower surface of the germanium region directly between the sidewalls of the patterned doped silicon layer; a first interconnect coupled to the doped region, the doped region extending from the first interconnect to the photodiode region; and a second interconnect coupled to a first doped contact region disposed within the germanium region directly above the protrusion of the photodiode region and the germanium region.

[0005] Further embodiments of this application provide a method for forming an image sensor integrated chip, comprising: forming a photodiode region within a substrate including a first semiconductor material region; forming a doped layer along an outer surface of the substrate and above the photodiode region; patterning the doped layer to form a patterned doped layer having one or more sidewalls defining one or more channel openings extending through the patterned doped layer located directly above the photodiode region; and forming a second semiconductor material region on the patterned doped layer and within the one or more channel openings. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1C Some embodiments of an image sensor integrated chip including patterned doped layers disposed between different semiconductor materials are shown.

[0008] Figures 2A to 2C Examples of energy barriers associated with different image sensor integrated chips with different doped layers are shown.

[0009] Figures 3A to 3C A top view of some embodiments of an image sensor integrated chip including patterned doped layers is shown.

[0010] Figures 4A to 4B Some additional embodiments of an image sensor integrated chip including patterned doped layers are shown.

[0011] Figure 5 Cross-sectional views of some alternative embodiments of an image sensor integrated chip including a patterned doped layer are shown.

[0012] Figures 6A to 6B Cross-sectional views of some embodiments of a multidimensional integrated chip structure including patterned doped layers are shown.

[0013] Figure 7 A cross-sectional view of an integrated chip structure including a short-wave infrared sensor and a direct time-of-flight (SWIR dToF) sensor (including a patterned doped layer) is shown.

[0014] Figures 8 to 20 Some embodiments of methods for forming an image sensor integrated chip including a patterned doped layer are shown.

[0015] Figures 21 to 31Some alternative embodiments of a method for forming an image sensor integrated chip including a patterned doped layer are shown.

[0016] Figure 32 Flowcharts of some embodiments of a method for forming an image sensor integrated chip including a patterned doped layer are shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] A single-photon avalanche diode (SPAD) is a solid-state photodetector that can be illuminated by incident radiation spanning a wide range of the electromagnetic spectrum, such as gamma rays, X-rays, beta and alpha particles, ultraviolet (UV) radiation, visible light, infrared (IR) radiation, etc. A SPAD typically comprises a first doped region (e.g., a p-doped region) and a second doped region (e.g., an n-doped region) disposed within a semiconductor substrate. During operation, incident photons can bombard the substrate and generate electron-hole pairs. The first and second doped regions are subjected to a high bias voltage that increases the electric field across the depletion region. This high bias voltage is higher than the breakdown voltage so that the SPAD operates in Geiger mode and so that a self-sustaining avalanche current (e.g., with more than 10) is generated from a single incident photon in the multiplication region. 6 (Electrons).

[0020] While silicon is commonly used in CMOS (Complementary Metal-Oxide-Semiconductor) processes, other semiconductor materials can have band gaps that enable photonic devices with better performance than silicon for wavelengths beyond the visible light spectrum. Therefore, during SPAD fabrication, a semiconductor substrate can be etched to form grooves, which are then filled with a second semiconductor material. In such a device, during operation, incident photons can strike the second semiconductor material and generate electron-hole pairs. The electrons then move into the semiconductor substrate, where a self-sustaining avalanche current is generated in the multiplication region.

[0021] However, it has been recognized that the etching process used to form the grooves can damage the semiconductor substrate, thereby creating defects (e.g., interface defects, dangling bonds, etc.) along the interface between the semiconductor substrate and the second semiconductor material. These defects can trap charge carriers (e.g., electrons) and cause unwanted leakage currents, leading to dark current and / or white pixel problems within the SPAD. To prevent dark current and / or white pixel problems within the SPAD, an implantation process can be implemented to implant dopants along the edges of the grooves. The dopants are selected to have a doping type that prevents charge carrier movement, thereby mitigating leakage currents. However, such dopants will increase the barrier height between the semiconductor material and the multiplication region, thereby reducing the performance of the SPAD (e.g., photodiode efficiency).

[0022] This invention relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate comprising a first semiconductor material. A second semiconductor material is disposed on the substrate. The second semiconductor material is separated from the substrate by a patterned doped layer. A photodiode region is disposed within the substrate beneath the second semiconductor material. The patterned doped layer includes sidewalls defining a channel opening directly above the photodiode region. The second semiconductor material extends through the channel opening to contact the substrate. During operation, electron-hole pairs can be formed within the second semiconductor material. However, because the second semiconductor material contacts the first semiconductor material, a relatively low potential barrier exists between the second semiconductor material and the photodiode region. This relatively low potential barrier improves the performance of the image sensor integrated chip, while the patterned doped layer reduces leakage current, thereby providing a disclosed image sensor integrated chip with good performance and low dark current.

[0023] Figure 1A Cross-sectional views of some embodiments of an image sensor integrated chip 100 including patterned doped layers disposed between different semiconductor materials are shown.

[0024] Image sensor integrated chip 100 includes a substrate 102, which includes or is a first semiconductor material (e.g., a region of the first semiconductor material). A second semiconductor material 108 (e.g., a region of the second semiconductor material) is disposed on the substrate 102. In some embodiments, the substrate 102 has sidewalls defining a recess 105 disposed within an upper surface 102u of the substrate 102 and a horizontally extending surface. In such embodiments, the second semiconductor material 108 may be disposed within the recess 105. The second semiconductor material 108 is a different material from the first semiconductor material. For example, the first semiconductor material may be silicon and the second semiconductor material 108 may include or be germanium. In some embodiments, a first doped contact region 110 is disposed along the upper surface of the second semiconductor material 108.

[0025] A patterned doped layer 106 is disposed between a substrate 102 and a second semiconductor material 108. The patterned doped layer 106 is configured to passivate defects (e.g., traps) disposed along one or more surfaces of the substrate 102. By passivating defects along one or more surfaces of the substrate 102, leakage along one or more surfaces can be improved. The patterned doped layer 106 includes sidewalls defining one or more channel openings 107 extending through the patterned doped layer 106. The second semiconductor material 108 includes protrusions 109 extending directly outward from the lower surface of the second semiconductor material 108 between the sidewalls of the patterned doped layer 106. In some embodiments, the protrusions 109 are defined by sidewalls coupled to the bottom surface of the second semiconductor material 108. The protrusions 109 directly contact the substrate 102.

[0026] In some embodiments, the substrate 102 and the patterned doped layer 106 are made of the same semiconductor material. For example, the substrate 102 may include a silicon substrate and the patterned doped layer 106 may include a patterned doped silicon layer. In some embodiments, the patterned doped layer 106 may include an epitaxial layer of the same material as the substrate 102. In other embodiments, the patterned doped layer 106 may include a doped region located within the substrate 102. In some embodiments, the patterned doped layer 106 is disposed along the sidewalls and horizontally extending surfaces of a defined recess 105 in the substrate 102. In such embodiments, the patterned doped layer 106 is located vertically and laterally between the substrate 102 and the second semiconductor material 108.

[0027] A photodiode region 101 is disposed within a substrate 102 located directly below one or more channel openings 107. In some embodiments, the photodiode region 101 may include or be a portion of a single photon avalanche diode (SPAD). In some embodiments, the photodiode region 101 includes a first doped region 104 having a first doping type (e.g., including p-type dopant) and a second doped region 112 having a second doping type (e.g., including n-type dopant). In some embodiments, the second doped region 112 extends continuously from the upper surface 102u of the substrate 102 below the first doped region 104. In such an embodiment, a first portion 112a of the second doped region 112 located directly below the first doped region 104 forms a pn junction of the photodiode region 101, while a second portion 112b of the second doped region 112 located laterally outside the first doped region 104 forms an electrical connection.

[0028] In some embodiments, a first plurality of interconnects 116 and a second plurality of interconnects 118 are disposed within a dielectric structure 114 above the upper surface 102u of the substrate 102. The first plurality of interconnects 116 are coupled to a second doped region 112 and the second plurality of interconnects 118 are coupled to a first doped contact region 110.

[0029] During operation, a first plurality of interconnects 116 are configured to apply a first bias voltage (e.g., a positive bias voltage) to a second doped region 112, and a second plurality of interconnects 118 are configured to apply a second bias voltage (e.g., a negative bias voltage) to a first doped contact region 110. The difference between the bias voltages can be in the range of about 10V and about 30V, about 15V and about 20V, about 17V, or other similar values. When an incident photon 120 strikes an atom within the second semiconductor material 108, the atom can release an electron to form an electron-hole pair 121. The bias voltage causes the electron and hole to move in opposite directions. As the electron leaves the second semiconductor material 108, it travels into a first doped region 104 (e.g., a multiplication region) of the substrate 102. Due to the high reverse bias voltage, impact ionization occurs within the first doped region 104 and causes avalanche multiplication to occur, generating additional electrons. These additional electrons are supplied as a photocurrent to the second doped region 112.

[0030] Typically, an unpatterned doped layer can provide an energy barrier for the flow of electrons and / or holes from the second semiconductor material 108 to the substrate 102, thereby reducing the photocurrent generated by the image sensor integrated chip 100. However, one or more channel openings 107 in the patterned doped layer 106 alleviate the barrier for the flow of electrons and / or holes into the substrate 102 and improve the performance of the image sensor integrated chip 100 (e.g., photodiode efficiency). Furthermore, because the patterned doped layer 106 is retained between the substrate 102 and the second semiconductor material 108, leakage within the image sensor integrated chip 100 is also improved, thereby reducing dark current and / or dark current rate, jitter, etc.

[0031] Figure 1B The section cut along line A-A' is shown. Figure 1A Top view 122 of some embodiments of the image sensor integrated chip 100. Figure 1C The section cut along line B-B' is shown. Figure 1A A top view 128 of some embodiments of the image sensor integrated chip 100. In some embodiments, Figure 1A The cross-sectional view can be taken along the cross-sectional line C-C' of the top view 122.

[0032] As shown in top views 122 and 128, the second semiconductor material 108 extends beyond one or more channel openings 107 in a first direction 124 and in a second direction 126 perpendicular to the first direction 124. A patterned doped layer 106 surrounds the outer periphery of the second semiconductor material 108 in a first closed and uninterrupted loop. In some embodiments, a second doped region 112 may surround the outer periphery of the second semiconductor material 108 in a second closed and uninterrupted loop. In some embodiments, the patterned doped layer 106 and the second doped region 112 may be substantially concentric about the center of the second semiconductor material 108.

[0033] Figure 2A Cross-sectional views of some embodiments of an image sensor integrated chip 200 including unpatterned doped layers disposed between different semiconductor materials are shown.

[0034] The image sensor integrated chip 200 includes a second semiconductor material 108 separated from a substrate 102 by an unpatterned doped layer 201. During operation, incident photons 120 can form electron-hole pairs 121 within the second semiconductor material 108. The electrons of the electron-hole pairs 121 can follow a first path 202 extending from within the second semiconductor material 108 to a first doped region 104 within the substrate 102. The first path 202 extends through the unpatterned doped layer 201.

[0035] Figure 2BCross-sectional views of some embodiments of an image sensor integrated chip 204 including patterned doped layers disposed between different semiconductor materials are shown.

[0036] The image sensor integrated chip 204 includes a second semiconductor material 108 separated from a substrate 102 by a patterned doped layer 106. During operation, incident photons 120 can form electron-hole pairs 121 within the second semiconductor material 108. The electrons of the electron-hole pairs 121 can follow a second path 206 extending from within the second semiconductor material 108 to a first doped region 104 of the substrate 102. The second path 206 extends through one or more channel openings 107 (extending through the patterned doped layer 106).

[0037] Figure 2C The display corresponds to Figure 2A and Figure 2B Some embodiments of the conductive strip diagram of the image sensor integrated chip are shown in Figure 208.

[0038] Curve 208 shows along Figure 2A A first energy band diagram 210 is captured by a first path 202 of the image sensor integrated chip 200. The first energy band diagram 210 includes an energy barrier 211 between the substrate 102 and the second semiconductor material 108. The energy barrier 211 has a barrier height 212 equal to approximately 0.6 eV, approximately 0.4 eV, or other similar values. The diagram 208 also includes a first energy band diagram along... Figure 2B The second energy band pattern 214 is captured by the second path 206 of the image sensor integrated chip 204. The second energy band pattern 214 has a small barrier (e.g., a barrier height of about 0.2 eV, about 0 eV, or other similar values) between the substrate 102 and the second semiconductor material 108. The small barrier is due to the second path 206 extending through one or more channel openings 107 within the patterned doped layer 106. Because the patterned doped layer provides a lower barrier height between the substrate 102 and the second semiconductor material 108, the disclosed image sensor integrated chip is capable of achieving improved performance compared to image sensor integrated chips with unpatterned doped layers.

[0039] It should be understood that, in various embodiments, the disclosed one or more channel openings may have different sizes, shapes, and / or spatial configurations within the patterned doped layer. Different sizes, shapes, and / or spatial configurations allow for different performance characteristics using the corresponding photodiode structures. For example, having one or more channel openings that collectively provide a larger total channel opening size will improve electron transfer from the second semiconductor material to the photodiode region, but may also lead to higher leakage, increased dark current, etc. Conversely, having one or more channel openings that collectively provide a smaller total channel opening size will result in lower leakage, lower dark current, etc., but may also lead to reduced electron transfer from the second semiconductor material to the corresponding photodiode region. Figures 3A to 3C Top views of some embodiments of patterned doped layers having one or more channel openings of different sizes, shapes and / or spatial configurations are shown.

[0040] Figure 3A A top view 300 of some embodiments of an image sensor integrated chip including one or more channel openings 107 surrounded by a patterned doped layer 106 is shown. The patterned doped layer 106 is further surrounded by a second doped region 112. In some embodiments, the one or more channel openings 107 include a single circular channel opening defined by one or more sidewalls of the patterned doped layer 106. In other embodiments, the one or more channel openings 107 may include single channel openings of different shapes (e.g., square channel openings, circular channel openings, elliptical channel openings, polygonal channel openings, etc.). A second semiconductor material 108 extends into the one or more channel openings 107. In some embodiments, the single circular channel opening may be substantially centered within the patterned doped layer 106 along a first direction 124 and along a second direction 126 perpendicular to the first direction 124.

[0041] Figure 3BA top view 302 shows some additional embodiments of an image sensor integrated chip including one or more channel openings 107 surrounded by a patterned doped layer 106. The one or more channel openings 107 include a plurality of individual channel openings, each defined by one or more sidewalls of the patterned doped layer 106. A second semiconductor material 108 extends into the one or more channel openings 107. In some embodiments, the plurality of individual channel openings are arranged within a one-dimensional array such that the plurality of individual channel openings are separated from each other by the patterned doped layer 106 along a first direction 124. In some embodiments, the plurality of individual channel openings include a plurality of rectangular channel openings. In other embodiments, the plurality of individual channel openings may include channel openings of different shapes (e.g., square channel openings, circular channel openings, elliptical channel openings, polygonal channel openings, etc.). In some embodiments, the one-dimensional array is centered within the patterned doped layer 106. In some embodiments, the plurality of individual channel openings include a central channel opening 107c, which is centered within the patterned doped layer 106 along the first direction 124 and along a second direction 126. In some additional embodiments, the plurality of individual channel openings also include peripheral channel openings 107p symmetrically arranged on opposite sides of the central channel opening 107c along the first direction 124.

[0042] Figure 3C A top view 304 shows some additional embodiments of an integrated chip including one or more channel openings 107 surrounded by a patterned doped layer 106. The one or more channel openings 107 include a plurality of individual channel openings, each defined by one or more sidewalls of the patterned doped layer 106. A second semiconductor material 108 extends into the one or more channel openings 107. In some embodiments, the plurality of individual channel openings are arranged in a two-dimensional array such that the plurality of individual channel openings are separated from each other by the patterned doped layer 106 along a first direction 124 and a second direction 126. In some embodiments, the plurality of individual channel openings include a plurality of circular channel openings. In other embodiments, the plurality of individual channel openings may include channel openings of different shapes (e.g., square channel openings, rectangular channel openings, elliptical channel openings, polygonal channel openings, etc.). In some embodiments, the two-dimensional array is centered within the patterned doped layer 106. In some embodiments, the plurality of individual channel openings include a central channel opening 108c, which is centered within the patterned doped layer 106 along a first direction 124 and a second direction 126. In some additional embodiments, the plurality of individual channel openings also include peripheral channel openings 108p, which are symmetrically arranged along the first direction 124 and the second direction 126 on opposite sides of the central channel opening 108c.

[0043] Figure 4A Cross-sectional views of some additional embodiments of an image sensor integrated chip 400 including the disclosed patterned doped layers are shown.

[0044] Image sensor integrated chip 400 includes a substrate 102 having sidewalls and a horizontally extending surface defining a recess 105 disposed within an upper surface of the substrate 102. In some embodiments, the substrate 102 may include a first semiconductor material. In some embodiments, the recess 105 may extend into the substrate 102 to a first depth 402, the first depth 402 being in the range of about 0 micrometers (μm) and about 5 μm, about 0 μm and about 3 μm, about 1 μm and about 3 μm, or other similar values. In some embodiments, the recess 105 is disposed within a pixel region 410. In some embodiments, the pixel region 410 may have a width in the range of about 5 μm and about 20 μm, about 1 μm and about 10 μm, or other similar values.

[0045] A patterned doped layer 106 is disposed along the sidewalls and horizontally extending surface of the substrate 102. The patterned doped layer 106 includes sidewalls defining one or more channel openings 107. In some embodiments, the patterned doped layer 106 may include a doped epitaxial layer extending along the sidewalls and horizontally extending surface of the substrate 102. In other embodiments, the patterned doped layer 106 may include doped regions implanted into the substrate 102. In some embodiments, the patterned doped layer 106 may include a first doping type (e.g., p-type silicon doped with boron, aluminum, gallium, etc.). In some embodiments, the patterned doped layer 106 may have a substantially uniform thickness 404. In some embodiments, the thickness 404 may be approximately 0 angstroms. Peace Treaty Between, in the agreement Peace Treaty Between, in the agreement Peace Treaty Within the range of or other similar values.

[0046] A second semiconductor material 108 is disposed within the recess 105 and on the patterned doped layer 106. The second semiconductor material 108 is a different material from the substrate 102. In some embodiments, the second semiconductor material 108 may be selected to be highly efficient for incident radiation having wavelengths above the visible light spectrum. For example, the second semiconductor material 108 may include germanium. The patterned doped layer 106 is located between the substrate 102 and the second semiconductor material 108. In some embodiments, the patterned doped layer 106 is located vertically and laterally between the substrate 102 and the second semiconductor material 108.

[0047] The second semiconductor material 108 includes a protrusion 109 extending directly outward from the lower surface of the second semiconductor material 108 to the sidewalls of the patterned doped layer 106. In some embodiments, the protrusion 109 may extend to a non-zero distance 406 below the bottom of the patterned doped layer 106. In such an embodiment, the protrusion 109 of the second semiconductor material 108 contacts the substrate 102 below the bottom of the patterned doped layer 106 vertically and laterally. In some embodiments, the non-zero distance 406 may be approximately Peace Treaty Between, in the agreement Peace Treaty Between, in the agreement Peace Treaty Within the range of or other similar values. In some embodiments, the protrusion 109 may be completely laterally confined between opposite sides of the photodiode region 101. In other embodiments (not shown), the protrusion 109 extends laterally beyond opposite sides of the photodiode region 101.

[0048] In some embodiments, a capping layer 408 is disposed over the second semiconductor material 108. The capping layer 408 may include a third semiconductor material. In some embodiments, the third semiconductor material may include, or be the same semiconductor material as the first semiconductor material of the substrate 102. For example, the first and third semiconductor materials may include, or be silicon. The capping layer 408 extends vertically from the upper surface of the substrate 102 to contact the top of the second semiconductor material 108. In some embodiments, the capping layer 408 and the upper surface 102u of the substrate 102 are substantially coplanar (e.g., planar within the tolerances of a chemical mechanical planarization (CMP) process). In some embodiments, the capping layer 408 completely covers the top of the second semiconductor material 108. In some embodiments, the capping layer 408 may include a relatively outermost wall that laterally contacts the sidewalls of the substrate 102. In other embodiments (not shown), the capping layer 408 may include a relatively outermost wall that laterally contacts the sidewalls of the patterned doped layer 106.

[0049] A first doped contact region 110 is disposed within the capping layer 408. In some embodiments, the first doped contact region 110 is disposed directly above one or more channel openings 107. In some embodiments, the first doped contact region 110 includes a p-type region. For example, the first doped contact region 110 may include a first doping type (e.g., p-type silicon doped with boron, aluminum, gallium, etc.). In some embodiments, the first doped contact region 110 may be confined within the capping layer 408. In other embodiments (not shown), the first doped contact region 110 may extend from within the capping layer 408 into the second semiconductor material 108.

[0050] A photodiode region 101 is disposed within a substrate 102 below one or more channel openings 107. In some embodiments, the photodiode region 101 includes a first doped region 104 having a first doping type (e.g., p-type doping) and a second doped region 112 having a second doping type (e.g., n-type doping). In some embodiments, the first doped region 104 may include p-type silicon (e.g., doped with boron, aluminum, gallium, etc.), and the second doped region 112 may include n-type silicon (e.g., doped with arsenic, phosphorus, etc.). In some embodiments, the second doped region 112 extends from the upper surface 102u of the substrate 102 below the first doped region 104. In such embodiments, the second doped region 112 includes a horizontally extending second doped region 112h and a vertically extending second doped region 112v projecting outward from the top of the horizontally extending second doped region 112h. In some alternative embodiments (not shown), the photodiode region 101 may extend into a second semiconductor material 108. In some such embodiments, a portion of the second semiconductor material 108 may include the first doping type to serve as the first doped region. In some embodiments, the portion of the second semiconductor material 108 including the first doping type can be separated from the second doped region 112 within the substrate 102 by an inherently doped portion of the substrate 102 vertically disposed therebetween.

[0051] In some embodiments, a dielectric structure 114 is disposed over an upper surface 102u of a substrate 102. The dielectric structure 114 surrounds a first plurality of interconnects 116 and a second plurality of interconnects 118. The first plurality of interconnects 116 are electrically coupled to a second doped region 112. In some embodiments, the first plurality of interconnects 116 are coupled to the second doped region 112 via a second doped contact region 412 disposed along the upper surface 102u of the substrate 102. The second doped contact region 412 has a higher doping concentration than the second doped region 112 to reduce contact resistance with the first plurality of interconnects 116. In some embodiments, the first plurality of interconnects 116 may include a first conductive contact 116a contacting the second doped contact region 412 and a first interconnect line 116b located above the first conductive contact 116a. The second plurality of interconnects 118 are electrically coupled to the first doped contact region 110. In some embodiments, the second plurality of interconnects 118 may include a second conductive contact 118a contacting the first doped contact region 110 and a second interconnect line 118b located above the second conductive contact 118a.

[0052] In some embodiments, the dielectric structure 114 includes a plurality of stacked interlayer dielectric (ILD) layers 114a-114b. The plurality of stacked ILD layers 114a-114b laterally surround a first plurality of interconnects 116 and a second plurality of interconnects 118. In some embodiments, the plurality of stacked ILD layers 114a-114b may include one or more of silicon dioxide, SiCOH, fluorosilicate glass, phosphate glass (e.g., borosilicate glass), etc. In some embodiments, for example, the first plurality of interconnects 116 and / or the second plurality of interconnects 118 may include conductive metals such as copper, aluminum, and / or tungsten. In some embodiments, two or more adjacent ILD layers in the plurality of stacked ILD layers 114a-114b may be separated by an etch stop layer (not shown) including nitrides, carbides, etc.

[0053] Figure 4B The section cut along line A-A' is shown. Figure 4A Top view 414 of the image sensor integrated chip.

[0054] As shown in top view 414, one or more channel openings 107 include a first width 416 extending in a first direction 124 and a first height 418 extending in a second direction 126 perpendicular to the first direction 124. The first width 416 and the first height 418 give the one or more channel openings 107 a first area, the first area being approximately equal to the first width 416 multiplied by the first height 418. A second semiconductor material 108 includes a second width 420 extending in the first direction 124 and a second height 422 extending in the second direction 126. The second width 420 and the second height 422 give the second semiconductor material 108 a second area, the second area being approximately equal to the second width 420 multiplied by the second height 422. The ratio of the first area to the second area is in the range of greater than about 0% and less than about 100%, greater than about 10% and less than about 80%, or other similar values.

[0055] Figure 5 Cross-sectional views of some embodiments of an image sensor integrated chip 500 including a disclosed patterned doped layer are shown.

[0056] Image sensor integrated chip 500 includes a photodiode region 101 disposed within a substrate 102. In some embodiments, the photodiode region 101 includes a first doped region 104 and a second doped region 112 disposed below the first doped region 104. The first doped region 104 includes a first doping type (e.g., p-type), and the second doped region 112 includes a second doping type (e.g., n-type). A patterned doped layer 106 is disposed along the upper surface 102u of the substrate 102. In various embodiments, the patterned doped layer 106 may include a doped epitaxial layer on the substrate 102 or a doped region within the substrate 102. The patterned doped layer 106 includes one or more sidewalls defining one or more channel openings 107 located directly above the first doped region 104.

[0057] A second semiconductor material 108 is disposed on the patterned doped layer 106 and on the upper surface 102u of the substrate 102. A first doped contact region 110 is disposed along the upper surface of the second semiconductor material 108 and within the second semiconductor material 108. The first doped contact region 110 includes a first doping type (e.g., p-type).

[0058] A dielectric structure 114 is disposed along the lower surface 102L of the substrate 102. The dielectric structure 114 surrounds a first plurality of interconnects 116 coupled to a second doped region 112. In some embodiments, the dielectric structure 114 may include a first plurality of stacked ILD layers. In some embodiments, the first plurality of interconnects 116 may include a first conductive contact 116a, an interconnect via, and / or a first interconnect line 116b. An additional dielectric structure 502 is disposed along the upper surface of a second semiconductor material 108 opposite to the substrate 102. The additional dielectric structure 502 surrounds a second plurality of interconnects 118 coupled to a first doped contact region 110. In some embodiments, the additional dielectric structure 502 may include a second plurality of stacked ILD layers. In some embodiments, the second plurality of interconnects 118 may include a second conductive contact 118a, a second interconnect via, and / or a second interconnect line 118b.

[0059] Figure 6A Cross-sectional views of some embodiments of a multidimensional integrated chip 600 including a disclosed patterned doped layer are shown.

[0060] The multidimensional integrated chip 600 includes an image sensor integrated chip (IC) die 602, which includes a photodiode region 101 disposed within a substrate 102. The photodiode region 101 includes a second doped region 112 disposed within the substrate 102. A second semiconductor material 108 is disposed within a recess in the substrate 102 above the photodiode region 101. A first doped contact region 110 is disposed along the surface of the second semiconductor material 108 facing away from the substrate 102. The second doped region 112 is coupled to a first plurality of interconnects 116 within a dielectric structure 114, and the first doped contact region 110 is coupled to a second plurality of interconnects 118 within the dielectric structure 114. The first plurality of interconnects 116 and the second plurality of interconnects 118 are coupled to a first plurality of bonding structures 604 (e.g., bonding pads).

[0061] The multidimensional integrated chip 600 also includes an additional IC die 606. The additional IC die 606 includes a plurality of semiconductor devices 608 disposed within an additional substrate 610. The plurality of semiconductor devices 608 may include transistor devices (e.g., planar FETs, FinFETs, gate all-around (GAA) devices, nanosheet devices, etc.) coupled to a third plurality of additional interconnects 612 within an additional dielectric structure 614 above the additional substrate 610. In some embodiments, the plurality of semiconductor devices 608 may be portions of a processor (e.g., a signal processing unit) configured to receive signals from the image sensor IC die 602. The third plurality of additional interconnects 612 are coupled to a plurality of additional bonding structures 616 (e.g., bonding pads) disposed on and / or within the additional dielectric structure 614.

[0062] The image sensor IC die 602 is bonded to an additional IC die 606 along a hybrid bonding interface, wherein a first plurality of bonding structures 604 contacts a plurality of additional bonding structures 616 along a conductive interface, and a dielectric structure 114 contacts an additional dielectric structure 614 along a dielectric interface.

[0063] Figure 6B Cross-sectional views of some additional embodiments of the multidimensional integrated chip 618, including the disclosed patterned doped layers, are shown.

[0064] The multidimensional integrated chip 618 includes an image sensor IC die 602 having a photodiode region 101 disposed within a substrate 102. The photodiode region 101 includes a second doped region 112 disposed within the substrate 102. A second semiconductor material 108 is disposed on the substrate 102. A first doped contact region 110 is disposed within the second semiconductor material 108. The second doped region 112 is coupled to a first plurality of interconnects 116 within a dielectric structure 114, and the first doped contact region 110 is coupled to a second plurality of interconnects 118 within an additional dielectric structure 502. The second plurality of interconnects 118 are coupled to a first plurality of bonding structures 604 (e.g., bonding pads).

[0065] The multidimensional integrated chip 600 also includes an additional IC die 606 bonded to the image sensor IC die 602 along a hybrid bonding interface, wherein a first plurality of bonding structures 604 contacts a plurality of additional bonding structures 616 along a conductive interface, and a dielectric structure 114 contacts the additional dielectric structure 614 along a dielectric interface.

[0066] It should be understood that the disclosed image sensor integrated chip can be implemented in different types of integrated chip applications. In some embodiments, the disclosed image sensor integrated chip can be implemented in short-wave infrared direct time-of-flight (SWIR dToF) sensors used in mobile phones, automotive applications (e.g., LiDAR), etc. The disclosed image sensor integrated chip provides a high-performance SWIR dToF due to its good performance (e.g., high sensitivity and / or photon detection efficiency) in the short-wave infrared spectrum (e.g., for wavelengths between about 1.3 and about 1.5 micrometers, between about 1.4 micrometers and about 3 micrometers, or other similar values).

[0067] Figure 7 A cross-sectional view of an integrated chip structure 700 including a SWIR dToF sensor with a publicly disclosed photodiode structure is shown.

[0068] The integrated chip structure 700 includes a first IC die 701 coupled to a substrate 702. In various embodiments, the substrate 702 may include an interposer substrate, a packaging substrate, a printed circuit board, etc. The first IC die 701 includes a photodiode region 101 disposed within the substrate 102. A second semiconductor material 108 is separated from the substrate 102 by a patterned doped layer 106.

[0069] In some embodiments, one or more color filters 704 are disposed on substrate 102. The one or more color filters 704 are configured to transmit incident radiation of a specific wavelength. For example, a first color filter among the one or more color filters 704 may be configured to transmit radiation having wavelengths within a first range (e.g., corresponding to green light) while reflecting radiation having wavelengths within a second range different from the first range (e.g., corresponding to red light), and so on. One or more microlenses 706 are disposed on the one or more color filters 704. The one or more microlenses 706 are configured to focus radiation toward photodiode region 101.

[0070] An integrated lighting chip 708 is also disposed on a substrate 702. In some embodiments, the integrated lighting chip 708 may include a light-emitting diode, a VCSEL (vertical-cavity surface-emitting laser), etc. In some embodiments, a package 710 surrounds the first IC die 701 and the integrated lighting chip 708.

[0071] During operation, the lighting integrated chip 708 is configured to generate lighting electromagnetic radiation 712 (e.g., NIR radiation). The lighting electromagnetic radiation 712 can be reflected from the target object 714 and reflected back towards the first IC die 701 as reflected electromagnetic radiation 716. The first IC die 701 is configured to detect the reflected electromagnetic radiation 716 and thereby generate a signal. A processing integrated chip (not shown) is configured to process the signal (e.g., to determine the distance to the target object 714).

[0072] Figures 8 to 20 Cross-sectional views 800-2000 illustrate some embodiments of a method for forming an image sensor integrated chip including a disclosed patterned doped layer. While the method is described... Figures 8 to 20 However, it should be understood that Figures 8 to 20 The disclosed structure is not limited to this method, but can exist independently of it. Furthermore, it should be understood that... Figures 1A to 7 The structure shown can be Figures 8 to 20 The method shown is formed within the range of optional embodiments.

[0073] like Figure 8 As shown in cross-sectional view 800, a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments (not shown), one or more semiconductor devices are formed on and / or within the substrate 102.

[0074] like Figure 8As shown in cross-sectional view 800, a horizontally extending second doped region 112h is formed within a substrate 102. The horizontally extending second doped region 112h is perpendicularly separated from the upper surface 102u of the substrate 102 by a non-zero distance. The horizontally extending second doped region 112h is formed to extend laterally from a first end to an opposite second end. In some embodiments, the horizontally extending second doped region 112h can be formed by selectively implanting a first dopant material 802 into the substrate 102 according to a first mask 804. In various embodiments, the first mask 804 may include oxides, photoresists, or other similar materials. In some embodiments, the first mask 804 may be formed on the upper surface 102u of the substrate 102, and the first dopant material 802 may be selectively implanted into the upper surface 102u of the substrate 102. In various embodiments, the first dopant material 802 may include arsenic, phosphorus, etc.

[0075] like Figure 9 As shown in cross-sectional view 900, a vertically extending second doped region 112v is formed within a substrate 102. The vertically extending second doped region 112v extends vertically from the horizontally extending second doped region 112h to the upper surface 102u of the substrate 102 to form the second doped region 112. In some embodiments, the vertically extending second doped region 112v can be formed by selectively implanting a second dopant material 902 into the substrate 102 according to a second mask 904. In various embodiments, the second mask 904 may include oxides, photoresists, or other similar materials. In some embodiments, the second mask 904 may be formed on the upper surface 102u of the substrate 102, and the second dopant material 902 may be selectively implanted into the upper surface 102u of the substrate 102. In various embodiments, the second dopant material 902 may include arsenic, phosphorus, etc.

[0076] like Figure 10 As shown in cross-sectional view 1000, a second doped contact region 412 is formed within the substrate 102 along the top of the vertically extending second doped region 112v and along the upper surface 102u of the substrate 102. The second doped contact region 412 has a higher doping concentration than the second doped region 112 in order to reduce the contact resistance with the interconnects above it. In some embodiments, the second doped contact region 412 can be formed by selectively implanting a third dopant material 1002 into the substrate 102 according to a third mask 1004. In various embodiments, the third mask 1004 may include oxides, photoresists, or other similar materials. In various embodiments, the third dopant material 1002 may include arsenic, phosphorus, etc.

[0077] like Figure 11As shown in cross-sectional view 1100, a substrate 102 is selectively etched according to a first patterning process to form a groove 105 within an upper surface 102u of the substrate 102. In some embodiments, the first patterning process can be implemented by selectively exposing the substrate 102 to a first etchant 1102 according to a fourth mask 1104. The first patterning process forms one or more sidewalls of the substrate 102 defining the groove 105 and a horizontally extending surface of the substrate 102. In some embodiments, the first etchant 1102 may include a dry etchant (e.g., a plasma etchant having a fluorine-based etching chemical, SF6 plasma, etc.) or a wet etchant. In some embodiments, the fourth mask 1104 may include a photosensitive material (e.g., photoresist), a hard mask, etc. The groove 105 is formed to extend into the substrate 102 to a first depth 402. In some embodiments, the first depth 402 may be in the range of about 0 μm and about 5 μm, about 0 μm and about 3 μm, about 1 μm and about 3 μm, or other similar values.

[0078] like Figure 12 As shown in cross-sectional view 1200, a first doped region 104 is formed within a substrate 102. In some embodiments, the first doped region 104 can be formed by selectively implanting a fourth dopant material 1202 into the substrate 102 according to a fifth mask 1204. The first doped region 104 can be formed to contact a second doped region 112 in order to form a photodiode region 101 within the substrate 102. In various embodiments, the fifth mask 1204 may include oxides, photoresists, or other similar materials. In various embodiments, the fourth dopant material 1202 may include boron, gallium, aluminum, etc.

[0079] like Figure 13 As shown in cross-sectional view 1300, a doped layer 1302 is formed along one or more sidewalls and horizontally extending surfaces of substrate 102. The doped layer 1302 is configured to eliminate defects (e.g., traps) that may form along one or more sidewalls and horizontally extending surfaces of substrate 102. In some embodiments, the doped layer 1302 may be formed such that approximately Peace Treaty Between, in the agreement Peace Treaty Between, in the agreement Peace Treaty Thickness 404, within the range of or other similar values.

[0080] In some embodiments, the doped layer 1302 can be formed by a selective epitaxial growth process. The selective epitaxial growth process forms the doped layer 1302 along one or more sidewalls and a horizontally extending surface of the substrate 102. The selective epitaxial growth process can form the doped layer 1302 to have a substantially uniform thickness 404 along one or more sidewalls and a horizontally extending surface of the substrate 102. In some embodiments, prior to the selective epitaxial growth process, a first sacrificial dielectric 1306 is formed on the upper surface 102u of the substrate 102. The first sacrificial dielectric 1306 blocks the formation of the doped layer 1302, such that the doped layer 1302 is confined within a recess 105. In some embodiments, the first sacrificial dielectric 1306 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), etc.

[0081] In other embodiments, the doped layer 1302 can be formed by selectively implanting a fifth dopant material into the substrate 102. In some embodiments, a high-temperature annealing process can be performed after the implantation process to diffuse the fifth dopant material into the substrate 102. In some embodiments, the fifth dopant material may include boron, gallium, aluminum, etc. In some embodiments, the high-temperature annealing can be performed at a temperature greater than about 750°C, greater than about 900°C, greater than about 1000°C, or other similar values. In some such embodiments, the doped layer 1302 can be formed by implanting a fifth dopant material into the substrate 102 according to a first sacrificial dielectric 1306. The implantation process can form the doped layer 1302 to have a thickness along one or more sidewalls that is smaller than the horizontally extending surface of the substrate 102.

[0082] like Figure 14 As shown in cross-sectional view 1400, a second sacrificial dielectric 1402 is formed on the doped layer 1302 and the first sacrificial dielectric 1306. In some embodiments, the second sacrificial dielectric 1402 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), etc. In some embodiments, the second sacrificial dielectric 1402 may be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, high-density IMP deposition, high-density ICP deposition, sputtering process, LP-CVD, etc.).

[0083] like Figure 15 As shown in the cross-sectional view 1500, the doped layer is selectively etched according to the second patterning process (e.g., Figure 14(1302) to form one or more channel openings 107 extending through the patterned doped layer 106. In some embodiments, one or more channel openings 107 may extend into the substrate 102 such that one or more channel openings 107 are defined by the sidewalls of both the patterned doped layer 106 and the substrate 102.

[0084] In some embodiments, the second patterning process can be performed by applying a doped layer (e.g., according to a sixth mask 1504) to the doped layer. Figure 14 The second sacrificial dielectric 1402 is selectively exposed to the second etchant 1502. The second sacrificial dielectric 1402 separates the doped layer from the sixth mask 1504. By separating the doped layer from the sixth mask 1504, the second sacrificial dielectric 1402 can prevent damage and / or contamination of the patterned doped layer 106 that could lead to increased leakage current within the image sensor integrated chip. In some embodiments, the second etchant 1502 may include a dry etchant (e.g., a plasma etchant with fluorine-based etching chemicals, SF6 plasma, etc.) or a wet etchant (e.g., hydrofluoric acid (HF), potassium hydroxide (KOH), piranha etchant, etc.). In some embodiments, the sixth mask 1504 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0085] like Figure 16 As shown in cross-sectional view 1600, the first and second sacrificial dielectrics are removed. In various embodiments, the first and second sacrificial dielectrics can be removed by planarization processes (e.g., chemical mechanical planarization (CMP) processes), etching processes, etc.

[0086] like Figure 17 As shown in cross-sectional view 1700, a second semiconductor material 108 is formed within a groove 105 and on a patterned doped layer 106. The second semiconductor material 108 is formed having protrusions 109 extending through one or more channel openings 107 to contact the substrate 102 at or below the bottom of the patterned doped layer 106. In some embodiments, the second semiconductor material 108 can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, low-pressure chemical vapor deposition (LP-CVD), etc.). In some embodiments, a planarization process (e.g., CMP) can be performed after the second semiconductor material 108 is formed in the groove 105 to remove excess portions of the second semiconductor material from above the upper surface 102u of the substrate 102.

[0087] like Figure 18As shown in cross-sectional view 1800, a capping layer 408 is formed on a second semiconductor material 108. In some embodiments, the capping layer 408 can be formed by recessing the second semiconductor material 108 to a non-zero distance below the upper surface 102u of the substrate 102. Subsequently, a capping semiconductor material is formed on the second semiconductor material 108, followed by a planarization process (e.g., chemical mechanical planarization (CMP) process) that removes excess portions of the capping semiconductor material from above the upper surface 102u of the substrate 102 to define the capping layer 408. In some embodiments, the capping semiconductor material may comprise silicon formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, high-density IMP deposition, high-density ICP deposition, sputtering process, LP-CVD, etc.).

[0088] like Figure 19 As shown in cross-sectional view 1900, a first doped contact region 110 is formed within the capping layer 408. In some embodiments, the first doped contact region 110 can be formed by selectively implanting a sixth dopant material 1902 into the capping layer 408 according to a seventh mask 1904. In some embodiments, the first doped contact region 110 can extend into the second semiconductor material 108. In various embodiments, the seventh mask 1904 can include oxides, photoresists, or other similar materials. In some embodiments, the sixth dopant material 1902 can include gallium, boron, etc.

[0089] like Figure 20 As shown in the cross-sectional view 2000, a dielectric structure 114 is formed above the upper surface 102u of the substrate 102. In some embodiments, the dielectric structure 114 can be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, high-density IMP deposition, high-density ICP deposition, sputtering, LP-CVD, etc.). In various embodiments, the dielectric structure 114 may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, porous dielectric materials (e.g., porous carbon-doped silicon dioxide), etc.

[0090] A first plurality of interconnects 116 and a second plurality of interconnects 118 are formed within a dielectric structure 114. The first plurality of interconnects 116 are coupled to a second doped region 112 via a second doped contact region 412, and the second plurality of interconnects 118 are coupled to a first doped contact region 110. In some embodiments, the first plurality of interconnects 116 and / or the second plurality of interconnects 118 may include conductive contacts, interconnect vias, and / or interconnects. In some embodiments, the first plurality of interconnects 116 and the second plurality of interconnects 118 may be formed simultaneously by selectively etching the dielectric structure 114 to define vias and / or trenches within the dielectric structure 114, forming a conductive material (e.g., copper, aluminum, etc.) within the vias and / or trenches, and performing a planarization process (e.g., chemical mechanical planarization). In some embodiments, the planarization process may include a CMP process.

[0091] Figures 21 to 31 Cross-sectional views 2100-3100 illustrate some alternative embodiments of a method for forming an image sensor integrated chip including a disclosed patterned doped layer. While the method is described... Figures 21 to 31 However, it should be understood that Figures 21 to 31 The disclosed structure is not limited to this method, but can exist independently of it. Furthermore, it should be understood that... Figures 1A to 7 The structure shown can be Figures 21 to 31 The method shown is formed within the range of optional embodiments.

[0092] like Figure 21 As shown in cross-sectional view 2100, a first doped region 104 is formed within the substrate 102. In some embodiments, the first doped region 104 can be formed by selectively implanting a first dopant material 2102 into the substrate 102 according to a first mask 2104.

[0093] like Figure 22 As shown in cross-sectional view 2200, a second doped region 112 is formed within the substrate 102. The second doped region 112 is perpendicularly separated from the upper surface 102u of the substrate 102 by a non-zero distance. The second doped region 112 may be formed to contact the first doped region 104 in order to form a photodiode region 101 within the substrate 102. In some embodiments, the second doped region 112 may be formed by selectively implanting a second dopant material 2202 into the substrate 102 according to a second mask 2204.

[0094] like Figure 23As shown in cross-sectional view 2300, a dielectric structure 114 is formed on the upper surface 102u of the substrate 102. In some embodiments, the dielectric structure 114 can be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, high-density IMP deposition, high-density ICP deposition, sputtering, LP-CVD, etc.). A first plurality of interconnects 116 are formed within the dielectric structure 114. The first plurality of interconnects 116 are formed to contact the second doped region 112. In some embodiments, the first plurality of interconnects 116 may include a first conductive contact 116a and a first interconnect line 116b.

[0095] like Figure 24 As shown in cross-sectional view 2400, substrate 102 can be thinned to reduce its thickness. In various embodiments, substrate 102 can be thinned by etching and / or mechanically grinding the lower surface 102L of substrate 102 to reduce the thickness of substrate 102 from a first thickness t1 to a second thickness t2. In some embodiments, the first thickness t1 can be in the range of about 700 μm and about 800 μm. In some embodiments, the second thickness t2 can be in the range of about 20 μm and about 80 μm.

[0096] like Figure 25 As shown in cross-sectional view 2500, a sacrificial dielectric 2502 is formed on the lower surface 102L of the substrate 102. In some embodiments, the sacrificial dielectric 2502 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), etc.

[0097] like Figure 26 As shown in cross-sectional view 2600, a doped layer 2602 is formed along the lower surface 102L of the substrate 102. The doped layer 2602 is configured to eliminate doping in the thinned substrate 102 (e.g., ...). Figure 23 Defects (e.g., traps) that may form along the lower surface 102L of the substrate 102 during the process (as shown in the diagram). In some embodiments, the doped layer 2602 can be formed by implanting a third dopant material 2604 into the lower surface 102L of the substrate 102. In other embodiments, the doped layer 2602 can be formed by a selective epitaxial growth process. In such an embodiment, the doped layer 1302 can be formed prior to the formation of the sacrificial dielectric 2502.

[0098] like Figure 27 As shown in cross-sectional view 2700, a third mask 2702 is formed on the sacrificial dielectric 2502. By separating the doped layer 2602 from the third mask 2702, the sacrificial dielectric 2502 can prevent damage and / or contamination of the doped layer 2602 that could lead to increased leakage current within the image sensor integrated chip.

[0099] like Figure 28 As shown in the cross-sectional view 2800, the doped layer is selectively etched according to the first patterning process (e.g., Figure 26 The first patterning process (2602) forms one or more channel openings 107 extending through the patterned doped layer 106. In some embodiments, the one or more channel openings 107 may extend into the substrate 102 such that the one or more channel openings 107 are defined by the sidewalls of both the patterned doped layer 106 and the substrate 102. In some embodiments, the first patterning process may be implemented by selectively exposing the doped layer to the first etchant 2802 according to the fourth mask 2804. In some embodiments, the first etchant 2802 may include a dry etchant (e.g., a plasma etchant having a fluorine-based etching chemical, SF6 plasma, etc.) or a wet etchant (e.g., hydrofluoric acid (HF), potassium hydroxide (KOH), piranha etchant, etc.). In some embodiments, the fourth mask 2804 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0100] like Figure 29 As shown in cross-sectional view 2900, a second semiconductor material 108 is formed on a patterned doped layer 106. The second semiconductor material 108 is formed having protrusions 109 that extend through one or more channel openings 107 to contact the substrate 102 at or below the bottom of the patterned doped layer 106. In some embodiments, the second semiconductor material 108 can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, high-density IMP deposition, high-density ICP deposition, sputtering, LP-CVD, etc.).

[0101] like Figure 30 As shown in cross-sectional view 3000, a first doped contact region 110 is formed within the second semiconductor material 108. In some embodiments, the first doped contact region 110 can be formed by selectively implanting a fourth dopant material 3002 into the second semiconductor material 108 according to a fourth mask 3004. In various embodiments, the fourth mask 3004 may include oxides, photoresists, or other similar materials.

[0102] like Figure 31As shown in cross-sectional view 3100, an additional dielectric structure 502 is formed over the second semiconductor material 108. In some embodiments, the additional dielectric structure 502 can be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, high-density IMP deposition, high-density ICP deposition, sputtering, LP-CVD, etc.). A second plurality of interconnects 118 are formed in the additional dielectric structure 502. In some embodiments, the second plurality of interconnects 118 may include conductive contacts, interconnects, and / or interconnect lines.

[0103] Figure 32 Flowcharts of some embodiments of a method 3200 for forming an image sensor integrated chip including a disclosed patterned doped layer are shown.

[0104] Although method 3200 is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown to achieve one or more aspects or embodiments described herein. Moreover, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0105] In step 3202, a photodiode region is formed within a substrate comprising a first semiconductor material. In some embodiments, the photodiode region may be formed according to steps 3204-3206.

[0106] In 3204, in some embodiments, a first doped region may be formed within the substrate. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of step 3204. Figure 21 Cross-sectional view 2100 is shown, corresponding to some additional embodiments of step 3204.

[0107] In 3206, a second doped region is formed within the substrate. Figures 8 to 9 Cross-sectional views 800-900 are shown for some embodiments corresponding to step 3206. Figure 22 Cross-sectional view 2200 is shown, corresponding to some additional embodiments of step 3206.

[0108] In 3208, in some embodiments, the substrate may be patterned to form a groove within the upper surface of the substrate above the photodiode region. Figure 11 A cross-sectional view 1100 is shown, corresponding to some embodiments of step 3208.

[0109] In 3210, a doped layer is formed along the outer surface of the substrate and above the photodiode region. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of step 3210 is shown. Figure 26 A cross-sectional view 2600 is shown, corresponding to some additional embodiments of step 3210.

[0110] In step 3212, the doped layer is patterned to form a patterned doped layer having one or more channel openings located directly above the photodiode region. Figure 15 A cross-sectional view 1500 corresponding to some embodiments of step 3212 is shown. Figures 27 to 28 Cross-sectional views 2700-2800 are shown corresponding to some additional embodiments of step 3212.

[0111] In step 3214, a second semiconductor material is formed on the patterned doped layer and within one or more channel openings. Figure 17 A cross-sectional view 1700 is shown, corresponding to some embodiments of step 3214. Figure 29 Cross-sectional view 2900 is shown, corresponding to some additional embodiments of step 3214.

[0112] In step 3216, a doped contact region is formed along the upper surface of the second semiconductor material and directly above one or more channel openings. Figures 18 to 19 Cross-sectional views 1800-1900 are shown for some embodiments corresponding to step 3216. Figure 30 A cross-sectional view 3000 corresponding to some additional embodiments of step 3216 is shown.

[0113] In step 3218, an interconnect is formed that will be coupled to the second doped region and the doped contact region. Figure 20 Cross-sectional view 2000 is shown for some embodiments corresponding to step 3218. Figure 23 and Figure 31 Cross-sectional views 2300 and 3100 are shown corresponding to some additional embodiments of step 3218.

[0114] Therefore, the present invention relates to an image sensor integrated chip comprising a patterned doped layer disposed between a photodiode region within a substrate comprising a first semiconductor material and a second semiconductor material on the substrate. The second semiconductor material extends through one or more channel openings in the patterned doped layer to provide a relatively low barrier between the second semiconductor material and the photodiode region. The relatively low barrier improves the performance of the image sensor integrated chip, while the patterned doped layer reduces leakage current, thereby providing a disclosed image sensor integrated chip with good performance and low dark current.

[0115] In some embodiments, the present invention relates to an image sensor integrated chip. The image sensor integrated chip includes: a photodiode region disposed within a substrate having a first semiconductor material region; a second semiconductor material region disposed on the substrate; a patterned doped layer disposed between the substrate and the second semiconductor material region; and the second semiconductor material region including a sidewall connected to a bottom surface of the second semiconductor material region, the sidewall extending through the patterned doped layer and the bottom surface being directly above the photodiode region. In some embodiments, the sidewall of the patterned doped layer laterally contacts the sidewall of the second semiconductor material region along an interface directly above the photodiode region. In some embodiments, the substrate includes a sidewall defining a recess within an upper surface of the substrate and a horizontally extending surface, the second semiconductor material region being disposed within the recess. In some embodiments, the image sensor integrated chip further includes: a capping layer disposed on the second semiconductor material region and directly disposed between the sidewalls of the substrate. In some embodiments, the patterned doped layer includes boron. In some embodiments, the second semiconductor material region extends vertically below the bottom of the patterned doped layer. In some embodiments, the patterned doped layer is laterally and vertically located between the first and second semiconductor material regions. In some embodiments, the patterned doped layer is the same semiconductor material region as the first semiconductor material region. In some embodiments, the photodiode region includes: a first doped region having a first doping type, the first doped region being located directly below the bottom surface of the second semiconductor material region; and a second doped region having a second doping type, the second doped region including a vertically extending second doped region coupled to a horizontally extending second doped region contacting the bottom of the first doped region.

[0116] In other embodiments, the present invention relates to an image sensor integrated chip. The image sensor integrated chip includes: a photodiode region disposed within a silicon substrate; a patterned doped silicon layer disposed on the silicon substrate, the patterned doped silicon layer having sidewalls directly above the photodiode region; a germanium region disposed on the patterned doped silicon layer, the germanium region having a protrusion extending outwardly from the lower surface of the germanium region directly between the sidewalls of the patterned doped silicon layer; a first interconnect coupled to the doped region, the doped region extending from the first interconnect to the photodiode region; and a second interconnect coupled to a first doped contact region disposed within the germanium region directly above the protrusion of the photodiode region and the germanium region. In some embodiments, the image sensor integrated chip further includes: a dielectric structure disposed above the germanium region and the silicon substrate, the dielectric structure laterally surrounding the first interconnect and the second interconnect. In some embodiments, the image sensor integrated chip further includes: a first dielectric structure disposed below the silicon substrate and surrounding the first interconnect; and a second dielectric structure disposed above the germanium region and surrounding the second interconnect. In some embodiments, the patterned doped silicon layer includes a plurality of sidewalls laterally spaced from each other by the patterned doped silicon layer, the plurality of sidewalls defining a plurality of individual channel openings extending through the patterned doped silicon layer; and a germanium region extending through the plurality of individual channel openings to contact a silicon substrate. In some embodiments, the plurality of individual channel openings are arranged in an array and spaced from each other along a first direction and a second direction perpendicular to the first direction, the first direction and the second direction being parallel to the lower surface of the germanium region. In some embodiments, protrusions extend laterally beyond the opposite side of the photodiode region.

[0117] In some other embodiments, the present invention relates to a method of forming an image sensor integrated chip. The method includes: forming a photodiode region within a substrate having a first semiconductor material region; forming a doped layer along an outer surface of the substrate and above the photodiode region; patterning the doped layer to form a patterned doped layer having one or more sidewalls defining one or more channel openings extending through the patterned doped layer directly above the photodiode region; and forming a second semiconductor material region on the patterned doped layer and within the one or more channel openings. In some embodiments, the method further includes: forming the photodiode region by performing a first implantation process to form a first doped region having a first doping type; and performing a second implantation process to form a second doped region having a second doping type, the second doped region being located below the first doped region. In some embodiments, the second doped region includes a horizontally extending second doped region extending below the bottom of the second semiconductor material region and a vertically extending second doped region extending along the sidewalls of the second semiconductor material region. In some embodiments, the method further includes: patterning the substrate to form a groove within an upper surface of the substrate; forming the second semiconductor material region within the groove; and performing a planarization process to remove excess portions of the second semiconductor material region from above the substrate. In some embodiments, the method further includes: performing an etching process to recess the second semiconductor material region below the upper surface of the substrate; forming a capping layer over the second semiconductor material region; and forming a doped contact region within the capping layer.

[0118] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. An image sensor integrated chip, comprising: The photodiode region is disposed within a substrate including a first semiconductor material region; A second semiconductor material region is disposed on the substrate; A patterned doped layer is disposed between the substrate and the region of the second semiconductor material; as well as The second semiconductor material region includes a sidewall connected to the bottom surface of the second semiconductor material region, the sidewall extending through the patterned doped layer, and the bottom surface being located directly above the photodiode region.

2. The image sensor integrated chip according to claim 1, wherein, The sidewall of the patterned doped layer laterally contacts the sidewall of the second semiconductor material region along the interface located directly above the photodiode region.

3. The image sensor integrated chip according to claim 1, wherein, The substrate includes sidewalls defining a groove within an upper surface of the substrate and a horizontally extending surface, wherein the second semiconductor material region is disposed within the groove.

4. The image sensor integrated chip according to claim 3, further comprising: A capping layer is disposed on the second semiconductor material region and directly between the sidewalls of the substrate.

5. The image sensor integrated chip according to claim 1, wherein, The patterned doped layer includes boron.

6. The image sensor integrated chip according to claim 1, wherein, The second semiconductor material region extends vertically below the bottom of the patterned doped layer.

7. The image sensor integrated chip according to claim 1, wherein, The patterned doped layer is located laterally and vertically between the first semiconductor material region and the second semiconductor material region.

8. The image sensor integrated chip according to claim 1, wherein, The patterned doped layer is the same semiconductor material region as the first semiconductor material region.

9. The image sensor integrated chip according to claim 1, wherein, The photodiode region includes: A first doped region, having a first doping type, wherein the first doped region is located directly below the bottom surface of the second semiconductor material region; and The second doped region has a second doping type, wherein the second doped region includes a vertically extending second doped region coupled to a horizontally extending second doped region that contacts the bottom of the first doped region.

10. An image sensor integrated chip, comprising: The photodiode region is disposed within the silicon substrate; A patterned doped silicon layer is disposed on the silicon substrate, the patterned doped silicon layer having sidewalls directly located above the photodiode region; A germanium region is disposed on the patterned doped silicon layer, wherein the germanium region includes a protrusion extending directly outward from the lower surface of the germanium region to the space between the sidewalls of the patterned doped silicon layer; A first interconnect, coupled to a doped region extending from the first interconnect to the photodiode region; and A second interconnect is coupled to a first doped contact region, which is located within the germanium region directly above the protrusion in the photodiode region and the germanium region.

11. The image sensor integrated chip according to claim 10, further comprising: A dielectric structure is disposed above the germanium region and the silicon substrate, wherein the dielectric structure laterally surrounds the first interconnect and the second interconnect.

12. The image sensor integrated chip according to claim 10, further comprising: A first dielectric structure is disposed beneath the silicon substrate and surrounds the first interconnect; as well as A second dielectric structure is disposed above the germanium region and surrounding the second interconnect.

13. The image sensor integrated chip according to claim 10, in, The patterned doped silicon layer includes a plurality of sidewalls laterally spaced from each other by the patterned doped silicon layer, the plurality of sidewalls defining a plurality of separate channel openings extending through the patterned doped silicon layer; as well as The germanium region extends through the plurality of individual channel openings to contact the silicon substrate.

14. The image sensor integrated chip according to claim 13, wherein, The plurality of individual channel openings are arranged in an array and spaced apart from each other along a first direction and a second direction perpendicular to the first direction, the first direction and the second direction being parallel to the lower surface of the germanium region.

15. The image sensor integrated chip according to claim 10, wherein, The protrusion extends laterally beyond the opposite side of the photodiode region.

16. A method for forming an integrated image sensor chip, comprising: A photodiode region is formed within a substrate including a first semiconductor material region; A doped layer is formed along the outer surface of the substrate and above the photodiode region; The doped layer is patterned to form a patterned doped layer having one or more sidewalls, the one or more sidewalls defining one or more channel openings extending through the patterned doped layer located directly above the photodiode region; as well as A second semiconductor material region is formed on the patterned doped layer and within the one or more channel openings.

17. The method according to claim 16, wherein, The region forming the photodiode includes: Perform a first implantation process to form a first doped region having a first doping type; and A second implantation process is performed to form a second doped region having a second doping type, the second doped region being located below the first doped region.

18. The method according to claim 17, wherein, The second doped region includes a horizontally extending second doped region extending below the bottom of the second semiconductor material region and a vertically extending second doped region extending along the sidewall of the second semiconductor material region.

19. The method of claim 16, further comprising: The substrate is patterned to form grooves within the upper surface of the substrate; A second semiconductor material region is formed within the groove; as well as A planarization process is performed to remove excess portions of the second semiconductor material region from above the substrate.

20. The method of claim 16, further comprising: An etching process is performed to recess the second semiconductor material region below the upper surface of the substrate; A capping layer is formed over the second semiconductor material region; as well as A doped contact region is formed within the capping layer.

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