A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises: a substrate, the substrate having a plurality of shallow trench isolation structures; a plurality of first doped regions in the substrate, the edge of each first doped region coinciding with one side of the adjacent shallow trench isolation structure, the first doped region having the same conductive type as the substrate, and the ion doping concentration of the first doped region being greater than that of the substrate; a dielectric layer covering the shallow trench isolation structures and the substrate; a plurality of plugs in the dielectric layer, each plug covering the corresponding first doped region and part of the surface of the shallow trench isolation structure, the first doped region forming a larger potential barrier in the substrate to prevent the leakage current at the junction of the plug, the substrate and the shallow trench isolation structure from flowing into the substrate, thereby avoiding the device failure caused by the leakage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller. Figure 1 This is a partial structural diagram of a semiconductor device, such as... Figure 1 As shown, the substrate 20 of the semiconductor device has a shallow trench isolation structure 21, and a dielectric layer 22 covers the shallow trench isolation structure 21 and the substrate 20. Generally, an opening is formed in the dielectric layer 22 to expose the substrate 20, and a metal material is filled in the opening to form a plug 23. The plug 23 is electrically connected to the substrate 20. A metal wiring layer is also formed on the dielectric layer 22 to lead out a number of plugs 23. In order to prevent short circuits between the metal lines of the metal wiring layer, a certain distance is required between the plugs 23. However, due to the shrinking size of the semiconductor device, the area of ​​the substrate 20 between the shallow trench isolation structures 21 is also continuously shrinking. Under the premise of meeting the distance requirements between the plugs 23 of the metal wiring layer, the position of the opening will be shifted, thereby exposing part of the shallow trench isolation structure 21 adjacent to the substrate 20. In addition, the etching process to form the opening will also erode the junction between the shallow trench isolation structure 21 and the substrate 20, resulting in a gap at the junction between the shallow trench isolation structure 21 and the substrate 20. When the plug 23 is formed, the metal material will also fill the gap. When the semiconductor device is working, the part of the plug located in the gap is prone to leakage current, causing device failure. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the leakage problem caused by plug misalignment and the gap at the interface between the shallow trench isolation structure and the substrate in existing semiconductor devices.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0005] A substrate having a plurality of shallow trench isolation structures;

[0006] A plurality of first doped regions are located within the substrate, the edge of each first doped region coincides with one side of the adjacent shallow trench isolation structure, the conductivity type of the first doped region is the same as the conductivity type of the substrate, and the ion doping concentration of the first doped region is greater than the ion doping concentration of the substrate.

[0007] A dielectric layer covers the shallow trench isolation structure and the substrate;

[0008] A plurality of plugs are located within the dielectric layer, and each plug covers a portion of the surface of the corresponding first doped region and the shallow trench isolation structure.

[0009] Optional, also includes:

[0010] A gate structure is located within the dielectric layer and on the substrate between the shallow trench isolation structures;

[0011] The source / drain regions are located within the substrate on both sides of the gate structure, and the ion doping concentration of the source / drain regions is greater than the ion doping concentration of the substrate.

[0012] Optionally, the ion doping concentration of the first doped region is equal to the ion doping concentration of the source / drain region.

[0013] Optional, also includes:

[0014] A metal silicide layer is located on the substrate, and the plug partially covers the metal silicide layer.

[0015] Optional, also includes:

[0016] A plurality of second doped regions are located within the corresponding shallow trench isolation structure, each second doped region being in contact with and electrically connected to an adjacent first doped region, the first doped region and the second doped region having the same ion doping concentration and conductivity type, and the plug also covering the corresponding second doped region.

[0017] Based on the same inventive concept, the present invention also provides a method for fabricating a semiconductor device, comprising:

[0018] A substrate is provided in which a plurality of shallow trench isolation structures are formed;

[0019] A plurality of first doped regions are formed in the substrate, the edge of each first doped region coincides with one side of the adjacent shallow trench isolation structure, the conductivity type of the first doped region is the same as the conductivity type of the substrate, and the ion doping concentration of the first doped region is greater than the ion doping concentration of the substrate.

[0020] A dielectric layer is formed on the substrate, the dielectric layer covering the shallow trench isolation structure and the substrate;

[0021] A plurality of plugs are formed within the dielectric layer, and each plug covers a portion of the surface of the corresponding first doped region and the shallow trench isolation structure.

[0022] Optionally, after forming the shallow trench isolation structure and before forming the dielectric layer, the method further includes:

[0023] A gate structure is formed on the substrate, the gate structure covering a portion of the substrate;

[0024] Metal silicide layers are formed on the substrates on both sides of the gate structure.

[0025] Optionally, after forming the dielectric layer, the step of forming the first doped region includes:

[0026] The dielectric layer is etched to form a plurality of openings within the dielectric layer, the openings exposing a portion of the surface of the substrate and the shallow trench isolation structure;

[0027] An ion implantation process is performed on the substrate to form the first doped region within the substrate.

[0028] Optionally, while performing ion implantation on the substrate, the shallow trench isolation structure within the opening is also subjected to ion implantation to form a second doped layer within the shallow trench isolation structure. Each second doped region is in contact with and electrically connected to an adjacent first doped region. The second doped layer and the first doped layer have the same ion doping concentration and conductivity type.

[0029] Optionally, while etching the dielectric layer to form the opening, a portion of the thickness of the shallow trench isolation structure at the bottom of the opening is etched to form a notch in the shallow trench isolation structure. When forming the plug, the plug fills the notch.

[0030] When a semiconductor device is operating, a large electric field exists at the interface between the shallow trench isolation structure and the substrate. If the plug simultaneously covers both the shallow trench isolation structure and part of the substrate surface, leakage current is easily generated at the interface between the shallow trench isolation structure and the substrate. In the semiconductor device provided by this invention, a first doped region is formed in the substrate below the plug. The edge of each first doped region coincides with one side of the adjacent shallow trench isolation structure. The ion doping concentration of the first doped region is greater than the ion doping concentration of the substrate. The first doped region can form a large potential barrier in the substrate, preventing leakage current at the interface between the plug, the substrate, and the shallow trench isolation structure from flowing into the substrate, thereby avoiding device failure caused by leakage current. Furthermore, the conductivity type of the first doped region is the same as that of the substrate, avoiding adverse effects of the conductivity type of the doped ions in the first doped region on the semiconductor device. Attached Figure Description

[0031] Figure 1 This is a partial structural diagram of a semiconductor device;

[0032] Figure 2A flowchart of a method for fabricating a semiconductor device is provided for embodiments of the present invention;

[0033] Figures 3-6 The diagram shows the corresponding structural steps of the semiconductor device fabrication method provided in the embodiments of the present invention. Figure 6 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0034] The attached figures are labeled as follows:

[0035] 20, 100 - Substrate; 21, 101 - Shallow trench isolation structure; 102 - Metal silicide layer; 22, 103 - Dielectric layer; 104 - First doped region; 105 - Second doped region; 24, 106 - Notch; 23, 107 - Plug. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0037] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the steps presented herein are not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described in the text may be added to the method.

[0038] Figure 6 This is a schematic diagram of the semiconductor device provided in this embodiment, as shown below. Figure 6 As shown, the semiconductor device includes a substrate 100, a dielectric layer 103, a gate structure, source and drain regions, and several plugs 107.

[0039] Specifically, the substrate 100 has a plurality of shallow trench isolation structures 101, the gate structure (not shown) is located on the substrate 100 between the shallow trench isolation structures 101, and the gate structure covers a portion of the substrate 100. The source and drain regions are located in the substrate 100 on both sides of the gate structure, and the dielectric layer 103 covers the gate structure, the source and drain regions, and the shallow trench isolation structures 101.

[0040] The ion doping concentration of the shallow trench isolation structure 101 is lower than that of the substrate 100, the ion doping concentration of the source / drain region is higher than that of the substrate 100, and the source / drain region and the substrate 100 form a vertical concentration difference.

[0041] The semiconductor device also has a metal wiring layer (not shown) and a plurality of plugs 107, wherein the plugs 107 are located within the dielectric layer 103 and electrically connected to the substrate 100, and the metal wiring layer is located on the dielectric layer 103 and electrically connected to the plurality of plugs 107.

[0042] As the size of the semiconductor device continues to decrease, the area of ​​the substrate 100 between the shallow trench isolation structures 101 also decreases. Furthermore, to prevent short circuits between the metal lines of the metal wiring layer, the plugs 107 need to have a certain spacing, resulting in some plugs 107 not being completely located on the substrate 100. The plugs 107 exhibit varying degrees of positional offset, and some plugs 107 may cover part of the substrate 100 and the upper surface of an adjacent shallow trench isolation structure 101. When the semiconductor device is operating, a large electric field exists at the interface between the shallow trench isolation structure 101 and the substrate 100. If the plugs 107 simultaneously cover both the shallow trench isolation structure 101 and the substrate 100, leakage current is likely to occur at the interface between the shallow trench isolation structure 101 and the substrate 100.

[0043] Furthermore, during the formation of the plug 107, the dielectric layer 103 needs to be etched to form an opening within the dielectric layer 103 exposing the substrate 100. If the position of the plug 107 is offset, the process of forming the opening will erode the interface between the shallow trench isolation structure 101 and the substrate 100, thereby creating a longitudinally extending gap 106 at the interface between the substrate 100 and the shallow trench isolation structure 101 into the substrate 100. When the plug 107 is formed, it fills the gap 106 and then electrically connects with the substrate 100 within the gap 106. Due to the longitudinal concentration difference between the source / drain region and the substrate 100, when the gap 106 extends into the substrate 100, the ion doping concentration of the substrate 100 below the plug 107 will be lower than the ion doping concentration of the source / drain region, causing leakage current to easily occur in areas with lower ion doping concentration during semiconductor device operation.

[0044] The semiconductor device provided in this embodiment forms a first doped region 104 within the substrate 100 below the plug 107. The edge of each first doped region 107 coincides with one side of the adjacent shallow trench isolation structure 101, and the ion doping concentration of the first doped region 104 is greater than that of the substrate 100. This reduces the concentration difference along the longitudinal direction of the notch 106, forming a uniform ion concentration interface at the junction of the plug 107 and the substrate 100, thereby creating a uniform potential barrier and preventing weak points, thus avoiding leakage. In this embodiment, the ion doping concentration of the first doped region 104 is equal to the ion doping concentration of the source / drain regions, minimizing the concentration difference within the notch 106 and further ensuring the performance of the semiconductor device. Furthermore, the conductivity type of the first doped region 104 is the same as that of the substrate 100, avoiding adverse effects of the conductivity type of the doped ions within the doped region on the semiconductor device.

[0045] It should be noted that in this embodiment, while forming the first doped region 104, a second doped region 105 is also formed in the shallow trench isolation structure 101 within the notch 106. Each second doped region 105 is in contact with and electrically connected to the adjacent first doped region 104, and the ion doping concentration and type of the second doped region 105 and the first doped region 104 are the same, which further improves the uniformity of the doped ion concentration of the film layer below the plug 107, thereby reducing leakage current and improving the reliability of the semiconductor device.

[0046] Continue reading Figure 6 The semiconductor device provided in this embodiment also includes a metal silicide layer 102, which covers the substrate 100.

[0047] Based on this, this embodiment also provides a method for fabricating a semiconductor device. Figure 2 This is a flowchart of the method for fabricating the semiconductor device. Figure 2 As shown, the method for fabricating the semiconductor device includes:

[0048] Step S1: Provide a substrate and form a plurality of shallow trench isolation structures within the substrate;

[0049] Step S2: A plurality of first doped regions are formed in the substrate, the edge of each first doped region coincides with one side of the adjacent shallow trench isolation structure, the conductivity type of the first doped region is the same as the conductivity type of the substrate, and the ion doping concentration of the first doped region is greater than the ion doping concentration of the substrate.

[0050] Step S3: Form a dielectric layer on the substrate, the dielectric layer covering the shallow trench isolation structure and the substrate;

[0051] Step S4: A plurality of plugs are formed in the dielectric layer, and each plug covers a portion of the surface of the corresponding first doped region and the shallow trench isolation structure.

[0052] Figures 3-6 This is a schematic diagram of the corresponding steps in the fabrication method of the semiconductor device provided in this embodiment. Next, we will combine... Figures 3-6 The method for fabricating the semiconductor device is described in detail.

[0053] like Figure 3 As shown, a substrate 100 is provided, and a plurality of shallow trench isolation structures 101 are formed in the substrate 100. A gate structure (not shown) and source / drain regions (not shown) are formed on the substrate 100. The doping ion type of the source / drain regions is greater than that of the substrate 100. The gate structure covers a portion of the substrate 100, and the source / drain regions are located in the substrate 100 on both sides of the gate structure. Then, a metal silicide layer 102 is formed on the source / drain regions. Finally, a dielectric layer 103 is formed on the substrate 100. The dielectric layer 103 covers the entire surface of the gate structure, the metal silicide layer 102, and the shallow trench isolation structures 101.

[0054] like Figure 4 As shown, the dielectric layer 103 is etched to form a plurality of openings within the dielectric layer 103. In order to meet other process parameters, in this embodiment, the openings expose part of the upper surface of the metal silicide layer 102 and the shallow trench isolation structure 101. During the etching process, erosion occurs at the junction of the shallow trench isolation structure 101 and the substrate 100, forming a notch 106 at the junction of the substrate 100 and the shallow trench isolation structure 101. The notch 106 extends longitudinally into the substrate 100.

[0055] like Figure 5 As shown, an ion implantation process is performed on the substrate 100 and the shallow trench isolation structure 101 within the opening to form a first doped region 104 in the substrate 100 within the notch 106 and a second doped region 105 in the shallow trench isolation structure 101 within the notch 106. The edge of each first doped region 104 coincides with one side of the adjacent shallow trench isolation structure 101. Each second doped region 105 is in contact with and electrically connected to the adjacent first doped region 104. The ion doping concentration and conductivity type of the first doped region 104 and the second doped region 105 are the same. The ion doping concentration of the first doped region 104 is the same as that of the source / drain region.

[0056] like Figure 6As shown, a metal material layer is formed, the portion of which fills the notch 106 and the opening constitutes a plug 107, and the portion of which covers the dielectric layer 103 constitutes a metal wiring layer (not shown).

[0057] Because of the longitudinal concentration difference between the source / drain region and the substrate 100, when the position of the plug 107 shifts, a notch 106 is formed at the junction of the substrate 100 and the shallow trench isolation structure 101 during the formation of the plug 107. The substrate 100 on the sidewall of the notch 106 also has a longitudinal concentration difference. In this embodiment, the first doped region 104 is formed in the substrate 100 on the sidewall of the notch 106, and the second doped region 105 is formed on the sidewall of the shallow trench isolation structure 101 to reduce the longitudinal concentration difference and make the plug 107 located in the notch 106 have a uniform potential barrier around it, thereby reducing leakage current.

[0058] It should be noted that, since the area of ​​a typical wafer is relatively large, the displacement of the plug 107 usually occurs at the edge of the wafer. If the plug 107 does not shift, the opening only exposes the metal silicide layer 102. The ion implantation process cannot penetrate the metal silicide layer 102 to implant ions into the substrate 100 and the source / drain regions below. Therefore, it will not change the doping ion concentration of the substrate 100 and the source / drain regions in the original semiconductor device. The semiconductor fabrication process provided in this embodiment has good compatibility with existing processes.

[0059] In summary, the semiconductor device provided in this embodiment of the invention includes: a substrate 100 having a plurality of shallow trench isolation structures 101 therein; a plurality of first doped regions 104 located within the substrate 100, the edge of each first doped region 104 coinciding with one side of an adjacent shallow trench isolation structure 101, the conductivity type of the first doped region 104 being the same as that of the substrate 100, and the ion doping concentration of the first doped region 104 being greater than that of the substrate 100; a dielectric layer 103 covering the shallow trench isolation structures 101 and the substrate 100; and a plurality of plugs 107 located within the dielectric layer 103, each plug 107 covering a corresponding first doped region 101. 04 and a portion of the surface of the shallow trench isolation structure 101; In the semiconductor device provided by the present invention, a first doped region 104 is formed in the substrate 100 below the plug 107. The ion doping concentration of the first doped region 104 is greater than that of the substrate 100. The first doped region 104 can form a large potential barrier in the substrate 100, preventing leakage current at the junction of the plug 107, the substrate 100 and the shallow trench isolation structure 101 from flowing into the substrate 100, thereby avoiding device failure caused by leakage current; and the conductivity type of the doped region is the same as that of the substrate 100, avoiding adverse effects of the conductivity type of the doped ions in the doped region on the semiconductor device.

[0060] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a plurality of shallow trench isolation structures; A plurality of first doped regions are located within the substrate, the edge of each first doped region coincides with one side of the adjacent shallow trench isolation structure, the conductivity type of the first doped region is the same as the conductivity type of the substrate, and the ion doping concentration of the first doped region is greater than the ion doping concentration of the substrate. A dielectric layer covers the shallow trench isolation structure and the substrate; A plurality of plugs are located within the dielectric layer, and each plug covers a portion of the surface of the corresponding first doped region and the shallow trench isolation structure; It also includes: a plurality of second doped regions located within the corresponding shallow trench isolation structure, each second doped region being in contact with and electrically connected to an adjacent first doped region, the first doped region and the second doped region having the same ion doping concentration and conductivity type, and the plug also covering the corresponding second doped region.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A gate structure is located within the dielectric layer and on the substrate between the shallow trench isolation structures; The source / drain regions are located within the substrate on both sides of the gate structure, and the ion doping concentration of the source / drain regions is greater than the ion doping concentration of the substrate.

3. The semiconductor device as described in claim 2, characterized in that, The ion doping concentration of the first doped region is equal to the ion doping concentration of the source / drain region.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A metal silicide layer is located on the substrate, and the plug partially covers the metal silicide layer.

5. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided in which a plurality of shallow trench isolation structures are formed; A dielectric layer is formed on the substrate, the dielectric layer covering the shallow trench isolation structure and the substrate; The dielectric layer is etched to form a plurality of openings within the dielectric layer, the openings exposing a portion of the surface of the substrate and the shallow trench isolation structure, and a notch is formed at the junction of the substrate and the shallow trench isolation structure during the etching process; An ion implantation process is performed on the substrate and the shallow trench isolation structure within the opening to form a first doped region within the substrate within the opening and a second doped region within the shallow trench isolation structure within the opening. The edge of each first doped region coincides with one side of the adjacent shallow trench isolation structure. The conductivity type of the first doped region is the same as that of the substrate. The ion doping concentration of the first doped region is greater than that of the substrate. Each second doped region is in contact with and electrically connected to the adjacent first doped region. The ion doping concentration and conductivity type of the second doped region are the same as those of the first doped region. A plurality of plugs are formed within the dielectric layer, and each plug covers a portion of the surface of the corresponding first doped region and the shallow trench isolation structure.

6. The semiconductor device as claimed in claim 5, characterized in that, After forming the shallow trench isolation structure and before forming the dielectric layer, the method further includes: A gate structure is formed on the substrate, the gate structure covering a portion of the substrate; Metal silicide layers are formed on the substrates on both sides of the gate structure.

7. The semiconductor device as claimed in claim 5, characterized in that, While etching the dielectric layer to form the opening, a portion of the thickness of the shallow trench isolation structure at the bottom of the opening is etched to form a notch in the shallow trench isolation structure. When forming the plug, the plug fills the notch.

Images