IGBT device and method of manufacturing the same
By introducing NMOS, NPN, and PNP transistors into IGBT devices, the potential change of the dummy gate is controlled, which solves the problem of high conduction and switching losses in IGBT devices and improves device performance and frequency application capabilities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI GONGCHENG SEMICON TECH CO LTD
- Filing Date
- 2022-11-10
- Publication Date
- 2026-06-02
AI Technical Summary
Existing IGBT devices struggle to effectively balance conduction and switching losses, resulting in significant losses.
By introducing NMOS, NPN, and PNP transistor structures into IGBT devices, the potential changes of the dummy gate can be controlled under different operating states to reduce turn-on, turn-off, and turn-off losses.
It effectively reduces the conduction, turn-on, and turn-off losses of IGBT devices, improves device performance, is suitable for higher frequency applications, and is achieved without increasing device area and manufacturing equipment costs.
Smart Images
Figure CN116190435B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an IGBT device and its fabrication method. Background Technology
[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a Bipolar Junction Transistor (BJT) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). IGBT devices have advantages such as low saturation voltage drop, high current density, low drive power, and fast switching speed, making them suitable for power management systems with a withstand voltage of 600V or higher.
[0003] The losses of IGBT devices typically include conduction losses and switching losses. In device design, a trade-off usually needs to be made between conduction losses and switching losses. In order to optimize the switching losses of the device, a dummy gate is usually used to reduce the switching losses of the device. However, setting a dummy gate will increase the conduction losses of the IGBT device.
[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an IGBT device and its fabrication method to solve the problem of large conduction losses and / or switching losses in the prior art IGBT devices.
[0006] To achieve the above and other related objectives, the present invention provides an IGBT device, comprising: a substrate on which an IGBT emitter, an IGBT gate, and an IGBT collector are formed; a dummy gate disposed between the gate and the IGBT emitter; an NMOS transistor disposed on the substrate and between the IGBT gate and the dummy gate, wherein the source and gate of the NMOS transistor are electrically connected to the IGBT gate, and the drain is electrically connected to the dummy gate; and an NPN transistor. A transistor is disposed on the substrate and between the dummy gate and the emitter of the IGBT. The collector of the NPN transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor. A PNP transistor is also disposed on the substrate and between the dummy gate and the emitter of the IGBT. The collector of the PNP transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor.
[0007] Optionally, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, thereby connecting the IGBT gate with the dummy gate, and forming a channel below the dummy gate to reduce the conduction loss of the IGBT device.
[0008] Optionally, when the IGBT device is turned on, the current at the emitter of the IGBT increases, and there is a voltage change in the inductance between the PNP transistor and the emitter of the IGBT, which causes the PNP transistor to be in an amplification state and turn on, so that the dummy gate is connected to the emitter of the IGBT, thereby reducing the turn-on loss of the IGBT device.
[0009] Optionally, when the IGBT device is turned off, the current at the emitter of the IGBT decreases, and there is a voltage change in the inductance between the NPN transistor and the emitter of the IGBT, which causes the NPN transistor to be turned on in an amplification state, thereby connecting the dummy gate to the emitter of the IGBT and reducing the turn-off loss of the IGBT device.
[0010] Optionally, the threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is less than or equal to 5V.
[0011] Optionally, the IGBT gate and the dummy gate are configured as rings, with the dummy gate surrounding the IGBT emitter and the IGBT gate surrounding the dummy gate.
[0012] Optionally, the substrate includes a first side and a second side opposite to each other, the IGBT emitter and the IGBT gate are disposed on the first side of the substrate, the IGBT collector is disposed on the second side of the substrate, and / or the IGBT device further includes a field cutoff layer disposed in the substrate and close to the IGBT collector.
[0013] Optionally, the inductance value of the inductor is 10nH to 20nH.
[0014] This invention also provides a method for fabricating an IGBT device, the method comprising the steps of: providing a substrate, forming an IGBT emitter, an IGBT gate, an IGBT collector, and a dummy gate on the substrate, the dummy gate being disposed between the IGBT gate and the IGBT emitter; disposing an NMOS transistor on the substrate, the NMOS transistor being disposed between the IGBT gate and the dummy gate, the source and gate of the NMOS transistor being electrically connected to the IGBT gate, and the drain being electrically connected to the dummy gate; and disposing an NMOS transistor on the substrate. An NPN transistor is disposed between the dummy gate and the emitter of the IGBT. The collector of the NPN transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor. A PNP transistor is disposed on the substrate, disposed between the dummy gate and the emitter of the IGBT. The collector of the PNP transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor.
[0015] Optionally, the process of fabricating an NMOS transistor, an NPN transistor, and a PNP transistor on the substrate includes the following steps: forming a first P-well, a second P-well, and an N-well in the substrate using an ion implantation process; forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate, and the gate of the NMOS transistor using a patterning process; forming the source and drain of the NMOS transistor in the first P-well using an ion implantation process, forming the base and emitter of the NPN transistor in the N-well, and forming the base and emitter of the PNP transistor in the second P-well; and forming an insulating layer on the substrate. A layer is formed in the insulating layer, a metal layer is formed on the contact holes and the insulating layer, and a wiring layer is formed by a patterning process. Through the contact holes and the wiring layer, the source and gate of the NMOS transistor are electrically connected to the gate of the IGBT, and the drain is electrically connected to the dummy gate. The collector of the NPN transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is connected to the contact point. The collector of the PNP transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is connected to the contact point.
[0016] Optionally, the method further includes the step of connecting an inductor between the contact point of the base of the NPN transistor and the PNP transistor and the emitter of the IGBT via an external pin, wherein the inductance value of the inductor is 10nH to 20nH.
[0017] Optionally, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, thereby connecting the IGBT gate with the dummy gate. A channel is formed below the dummy gate to reduce the conduction loss of the IGBT device. When the IGBT device is turned on, the current at the IGBT emitter increases, and there is a voltage change in the inductance between the PNP transistor and the IGBT emitter, causing the PNP transistor to be in an amplification state and turn on, connecting the dummy gate with the IGBT emitter, thereby reducing the turn-on loss of the IGBT device. When the IGBT device is turned off, the current at the IGBT emitter decreases, and there is a voltage change in the inductance between the NPN transistor and the IGBT emitter, causing the NPN transistor to be in an amplification state and turn on, connecting the dummy gate with the IGBT emitter, thereby reducing the turn-off loss of the IGBT device.
[0018] Optionally, the threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is less than or equal to 5V.
[0019] Optionally, the IGBT gate and the dummy gate are configured as rings, with the dummy gate surrounding the IGBT emitter and the IGBT gate surrounding the dummy gate.
[0020] Optionally, the substrate includes a first side and a second side opposite to each other, the IGBT emitter and the IGBT gate are disposed on the first side of the substrate, the IGBT collector is disposed on the second side of the substrate, and / or the IGBT device further includes a field cutoff layer disposed in the substrate and close to the IGBT collector.
[0021] As described above, the IGBT device and its fabrication method of the present invention have the following beneficial effects:
[0022] This invention applies a threshold voltage to the IGBT gate when the IGBT is turned on. This threshold voltage is simultaneously applied to the gate of the NMOS transistor, causing the NMOS transistor to conduct. This connects the IGBT gate to a dummy gate, forming a channel beneath the dummy gate to reduce the IGBT's turn-on losses. When the IGBT is turned on, the emitter current increases, causing a voltage change in the inductance between the PNP transistor and the IGBT emitter. This causes the PNP transistor to conduct in an amplification state, connecting the dummy gate to the IGBT emitter and reducing the IGBT's turn-on losses. When the IGBT is turned off, the emitter current decreases, causing a voltage change in the inductance between the NPN transistor and the IGBT emitter. This causes the NPN transistor to conduct in an amplification state, connecting the dummy gate to the IGBT emitter and reducing the IGBT's turn-off losses. By controlling the potential change of the dummy gate during different operating states, this invention effectively improves device heating, increases power density, and ultimately enhances device performance, enabling the IGBT to be used in higher frequency applications.
[0023] The NMOS transistor, NPN transistor, and PNP transistor of this invention are disposed between the IGBT gate, the dummy gate, and the IGBT emitter, without requiring additional device area. This ensures that the device can reduce both turn-off and turn-on losses in a smaller volume. Furthermore, this invention is compatible with conventional IGBT device manufacturing processes, requiring no additional manufacturing equipment and effectively controlling device manufacturing costs. Attached Figure Description
[0024] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.
[0025] Figure 1The diagram shows the layout structure of an IGBT device according to an embodiment of the present invention.
[0026] Figure 2 The diagram shown is a schematic diagram of the circuit principle of an IGBT device according to an embodiment of the present invention.
[0027] Figures 3-8 The diagram shows the structural schematics of each step in the fabrication method of the IGBT device according to an embodiment of the present invention.
[0028] Component designation explanation
[0029] 10 IGBT gate
[0030] 11. Dummy gate
[0031] 12 IGBT Emitter
[0032] 13 NMOS transistors
[0033] 14 NPN transistor
[0034] 15 Inductors
[0035] 16 PNP transistor
[0036] 101 substrate
[0037] 102 First P-well
[0038] 103 N-well
[0039] 104 NMOS gate
[0040] 106 NMOS source
[0041] 107 NMOS drain
[0042] 108 NPN base
[0043] 109 NPN emitter
[0044] 110 Insulation Layer
[0045] 111 First wiring
[0046] 112 Second wiring
[0047] 113 Contact Point
[0048] 201 Second P-well
[0049] 202 PNP base
[0050] 203 PNP emitter Detailed Implementation
[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0052] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0053] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0054] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0055] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0056] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0057] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0058] like Figures 1 to 8As shown, this embodiment provides an IGBT device, which includes: a substrate 101 on which an IGBT emitter 12, an IGBT gate 10, and an IGBT collector are formed; a dummy gate 11 disposed between the gate and the IGBT emitter 12; an NMOS transistor 13 disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, wherein the source 109 and gate 104 of the NMOS transistor 13 are electrically connected to the IGBT gate 10, and the drain 107 is electrically connected to the dummy gate 11; and an NPN transistor 14 disposed on the substrate. On substrate 101, and disposed between the dummy gate 11 and the IGBT emitter 12, the collector 108 of the NPN transistor 14 is electrically connected to the dummy gate 11, the emitter 109 is electrically connected to the IGBT emitter 12, and the base 108 is electrically connected to the IGBT emitter 12 through inductor 15; a PNP transistor 16 is disposed on substrate 101, and disposed between the dummy gate 11 and the IGBT emitter 12, the collector of the PNP transistor is electrically connected to the dummy gate 11, the emitter 203 is electrically connected to the IGBT emitter 12, and the base 202 is electrically connected to the IGBT emitter 12 through inductor 15.
[0059] The substrate 101 may be, for example, a silicon substrate 101, and may also include other semiconductors, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe). The substrate 101 may include compound semiconductors and / or alloy semiconductors, such as gallium nitride, gallium arsenide, etc. Furthermore, the substrate 101 may include an epitaxial layer (epitaxy layer) and may be strained to improve performance. In this embodiment, the substrate 101 includes drift regions, such as lightly doped N-type drift regions.
[0060] The substrate 101 includes a first side and a second side opposite to each other. The IGBT emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, and the IGBT collector is disposed on the second side of the substrate 101. The IGBT device further includes a field cutoff layer disposed in the substrate 101 and close to the IGBT collector.
[0061] In one embodiment, the IGBT emitter 12 of the IGBT device includes an N+ type emitter region and a P type body region disposed between the N+ type emitter region and the N- type drift region, which is not shown in the figure.
[0062] like Figure 1As shown, the IGBT gate 10 and the dummy gate 11 are configured as rings, such as rectangular rings, rounded rectangular rings, elliptical rings, circular rings, etc. The dummy gate 11 surrounds the IGBT emitter 12, and the IGBT gate 10 surrounds the dummy gate 11. There is a gap between the IGBT gate 10 and the dummy gate 11, and there is a gap between the dummy gate 11 and the IGBT emitter 12.
[0063] like Figure 1 and Figure 8 As shown, where, Figure 8 Displayed as Figure 1 The diagram shows cross-sectional views at points A-A' and B-B', with the left side showing the cross-sectional view at A-A' and the right side showing the cross-sectional view at B-B'. The NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11. The NMOS transistor 13 includes a first P-well 102 disposed in the substrate 101, an NMOS gate 104 located on the first P-well 102, and a source 106 and a drain 107 disposed in the first P-well 102 on both sides of the NMOS gate 104. In one embodiment, the threshold voltage of the NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the difference between the threshold voltage of the IGBT gate 10 and the threshold voltage of the NMOS transistor 13 is less than or equal to 5V. For example, the threshold voltage of the IGBT device's gate can be 15V, and the threshold voltage of the NMOS transistor 13's gate can be set between 13.5V and 15V.
[0064] like Figure 1 and Figure 8 As shown, the NPN transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the IGBT emitter 12. The NPN transistor 14 includes an N-well 103 (as the collector of the NPN transistor) disposed in the substrate 101, an NPN base 108 (P-type) located on the N-well 103, and an emitter 109 (N-type) disposed in the NPN base 108. The base 108 separates the emitter 109 from the N-well 103.
[0065] like Figure 1 and Figure 8As shown, the PNP transistor 116 is disposed on the substrate 101 and between the dummy gate 11 and the IGBT emitter 12. The PNP transistor 16 includes a second P-well 201 disposed in the substrate 101 as the collector of the PNP transistor, a PNP base 202 located on the second P-well 201, and a PNP emitter 203 disposed in the PNP base 202. The PNP base 202 separates the PNP emitter 203 from the second P-well 201.
[0066] This invention effectively improves device heating, increases power density, and enhances device performance by controlling the potential change of the dummy gate during different operating states of the device, enabling IGBT devices to be used in higher frequency applications.
[0067] like Figure 8 As shown, the source and gate of the NMOS transistor 13 are electrically connected to the gate 10 of the IGBT via a first wiring 111. The drain of the dummy gate 11 is electrically connected to the collector of the NPN transistor 14 via a second wiring 112. The emitter 109 of the NPN transistor 14 is electrically connected to the emitter 12 of the IGBT. The base 108 is provided with a contact point 113 via wiring. When setting the pins later, this contact point 113 is electrically connected to the emitter 12 of the IGBT via an inductor 15. The collector of the PNP transistor 16 is electrically connected to the dummy gate 11 via the second wiring 112. The emitter 203 is electrically connected to the emitter 12 of the IGBT. The PNP base 202 is connected to the contact point 113, so that the PNP base 202 is connected to the NPN base 108 of the NPN transistor 14.
[0068] In one embodiment, the inductance value of the inductor 15 is 10nH to 20nH, for example, the inductance value of the inductor 15 can be 13nH.
[0069] In one embodiment, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate 10, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor 13 to turn on the NMOS transistor 13, thereby connecting the IGBT gate 10 with the dummy gate 11, and forming a channel below the dummy gate 11 to reduce the conduction loss of the IGBT device.
[0070] In one embodiment, when the IGBT device is turned on, the current at the IGBT emitter 12 increases, and there is a voltage change in the inductor 15 between the PNP transistor 16 and the IGBT emitter 12, thereby causing the PNP transistor 16 to be in an amplification state and conduct, so that the dummy gate 11 is connected to the IGBT emitter 12, thereby reducing the turn-on loss of the IGBT device.
[0071] In one embodiment, when the IGBT device is turned off, the current at the IGBT emitter 12 decreases, and there is a voltage change in the inductor 15 between the NPN transistor 14 and the IGBT emitter 12, thereby causing the NPN transistor 14 to be turned on in an amplification state, so that the dummy gate 11 is connected to the IGBT emitter 12, thereby reducing the turn-off loss of the IGBT device.
[0072] The circuit schematic of the IGBT device in this embodiment is as follows: Figure 2 As shown, specifically, when the IGBT device is in the on state, the gate voltage is usually about 15V. At this time, the drain of NMOS transistor 13 is shorted to the IGBT gate 10, and the dummy gate 11 is shorted to the source. When the voltage of NMOS gate 104 is 15V, NMOS transistor 13 is turned on, and the potentials of IGBT gate 10 and dummy gate 11 are the same. This will open the channels on both sides of the dummy gate 11, reduce the VCESAT of the device, and thus reduce the conduction loss of the device.
[0073] In this embodiment, the IGBT emitter 12 of the IGBT device has an inductor 15. For example, the inductor 15 integrated inside the TO247 is about 13nH. When the device is in the turn-on process, the current of the IGBT emitter 12 increases. Taking a 650V 15A IGBT device as an example, during the turn-on process, the current change di / dt in the inductor 15 is about 130A / us to 300A / us. Thus, the voltage change across the inductor 15 of the IGBT emitter 12 is 1.69-3.9V, which causes the PNP transistor 16 to be in the amplification state and conduct, so as to connect the dummy gate 11 with the IGBT emitter 12, thereby effectively reducing the device turn-on loss.
[0074] In this embodiment, the IGBT emitter 12 of the IGBT device has an inductor 15. For example, the inductor 15 integrated inside the TO247 is about 13nH. When the device is in the turn-on process, the current of the IGBT emitter 12 decreases. Taking a 650V 15A IGBT device as an example, during the turn-on process, the current change di / dt in the inductor 15 is about 150A / us. Thus, the voltage change across the inductor 15 of the IGBT emitter 12 is 1.95V, which causes the NPN transistor 14 to be in the amplification state and conduct, so as to connect the dummy gate 11 with the IGBT emitter 12, thereby effectively reducing the device turn-off loss.
[0075] like Figures 1 to 8 As shown, this embodiment also provides a method for fabricating an IGBT device, the method comprising the following steps: providing a substrate 101, forming an IGBT emitter 12, an IGBT gate 10, an IGBT collector, and a dummy gate 11 on the substrate 101, the dummy gate 11 being disposed between the IGBT gate 10 and the IGBT emitter 12; and disposing an NMOS transistor 13 on the substrate 101, the NMOS transistor 13 being positioned between the IGBT gate 10 and the dummy gate 11. The source 106 and gate 104 of the NMOS transistor 13 are electrically connected to the gate 10 of the IGBT, and the drain 107 is electrically connected to the dummy gate 11. An NPN transistor 14 is disposed on the substrate 101, positioned between the dummy gate 11 and the emitter 12 of the IGBT. The collector of the NPN transistor 14 is electrically connected to the dummy gate 11, the emitter 109 is electrically connected to the emitter 12 of the IGBT, and the base 108 is electrically connected to the emitter 12 of the IGBT through an inductor 15. A PNP transistor 16 is disposed on the substrate 101, positioned between the dummy gate 11 and the emitter 12 of the IGBT. The collector of the PNP transistor 16 is electrically connected to the dummy gate 11, the emitter 203 is electrically connected to the emitter 12 of the IGBT, and the base 202 is electrically connected to the emitter 12 of the IGBT through an inductor 15. Among them, such as Figure 1 As shown, the NPN transistor 14 and PNP transistor 16 are respectively disposed on opposite sides of the emitter 12, and the NMOS transistor is disposed below the emitter 12, so that there is a large gap and fabrication space between the NMOS transistor 13, the NPN transistor 14 and the PNP transistor 16, so as to facilitate their fabrication and subsequent electrical connection through contact holes and wiring.
[0076] In one embodiment, such as Figures 3-8 As shown, the process of setting an NMOS transistor 13, an NPN transistor 14, and a PNP transistor 16 on the substrate 101 includes the following steps:
[0077] like Figures 3-4 As shown, step 1) is performed first, in which a first P-well 102, a second P-well 201 and an N-well 103 are formed in the substrate 101 by ion implantation. Of course, during this process, structures such as the P-type body region of the IGBT device can also be fabricated at the same time to save process costs.
[0078] like Figure 5 As shown, step 2) is then performed, forming a gate dielectric layer and a gate layer on the substrate 101, and forming the IGBT gate 10, the dummy gate 11, and the gate of the NMOS transistor 13 through a patterning process. The gate dielectric layer can be, for example, silicon dioxide, or a high-k dielectric such as hafnium oxide, and the gate layer can be polysilicon or metal.
[0079] like Figure 6 Then, in step 3), the source 106 and drain 107 of the NMOS transistor 13 are formed in the first P-well 102 by ion implantation, the P-type base 108 and N-type emitter 109 of the NPN transistor 14 are formed in the N-well 103, and the base 202 and emitter 203 of the PNP transistor are formed in the second P-well 201. Of course, during this process, structures such as the emitter region of the IGBT can also be fabricated simultaneously to save on process costs.
[0080] like Figures 7-8 As shown, in step 4), an insulating layer 110 is formed on the substrate 101, a contact hole is formed in the insulating layer 110, a metal layer is formed on the contact hole and the insulating layer 110, and a wiring layer is formed by patterning. Through the contact hole and the wiring layer, the source and gate of the NMOS transistor 13 are electrically connected to the gate of the IGBT 10, and the drain is electrically connected to the dummy gate 11. The collector of the NPN transistor 14 is electrically connected to the dummy gate 11, the emitter 109 is electrically connected to the emitter 12 of the IGBT, and the base 108 is connected to the contact point 113. The collector of the PNP transistor 16 is electrically connected to the dummy gate 11, the emitter 203 is electrically connected to the emitter 12 of the IGBT, and the base 202 is connected to the contact point 113.
[0081] In one embodiment, the method further includes the step of connecting an inductor 15 between the contact point 113 of the base 108 of the NPN transistor 14 and the base 202 of the PNP transistor and the emitter 12 of the IGBT via an external pin, wherein the inductance value of the inductor 15 is 10nH to 20nH.
[0082] In one embodiment, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate 10, and this threshold voltage is simultaneously applied to the gate of the NMOS transistor 13 to turn on the NMOS transistor 13, thereby connecting the IGBT gate 10 to the dummy gate 11. A channel is formed below the dummy gate 11 to reduce the conduction loss of the IGBT device. When the IGBT device is turned on, the current at the IGBT emitter 12 increases, and there is a voltage change in the inductor 15 between the PNP transistor 16 and the IGBT emitter 12. The PNP transistor 16 is turned on in an amplification state, connecting the dummy gate 11 to the IGBT emitter 12, thereby reducing the turn-on loss of the IGBT device. When the IGBT device is turned off, the current at the IGBT emitter 12 decreases, and there is a voltage change in the inductor 15 between the NPN transistor 14 and the IGBT emitter 12, causing the NPN transistor 14 to turn on in an amplification state, connecting the dummy gate 11 to the IGBT emitter 12, thereby reducing the turn-off loss of the IGBT device.
[0083] In one embodiment, the threshold voltage of the NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the threshold voltage of the IGBT gate 10 differs from the threshold voltage of the NMOS transistor 13 by less than or equal to 5V.
[0084] In one embodiment, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, with the dummy gate 11 surrounding the IGBT emitter 12 and the IGBT gate 10 surrounding the dummy gate 11.
[0085] In one embodiment, the substrate 101 includes a first side and a second side opposite to each other, the IGBT emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, the IGBT collector is disposed on the second side of the substrate 101, and / or the IGBT device further includes a field cutoff layer disposed in the substrate 101 and close to the IGBT collector.
[0086] As described above, the IGBT device and its fabrication method of the present invention have the following beneficial effects:
[0087] In this invention, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate 10. This threshold voltage is simultaneously applied to the gate of the NMOS transistor 13, causing the NMOS transistor 13 to conduct. This connects the IGBT gate 10 to the dummy gate 11, forming a channel below the dummy gate 11 to reduce the IGBT device's turn-on losses. When the IGBT device is turned on, the current at the IGBT emitter 12 increases, causing a voltage change in the inductor 15 between the PNP transistor 16 and the IGBT emitter 12. This causes the PNP transistor 16 to conduct in an amplification state, connecting the dummy gate 11 to the IGBT emitter 12, thereby reducing the IGBT device's turn-on losses. When the IGBT device is turned off, the current at the IGBT emitter 12 decreases, causing a voltage change in the inductor 15 between the NPN transistor 14 and the IGBT emitter 12. This causes the NPN transistor 14 to conduct in an amplification state, connecting the dummy gate 11 to the IGBT emitter 12, thereby reducing the IGBT device's turn-off losses. This invention effectively improves device heating, increases power density, and enhances device performance by controlling the potential change of the dummy gate 11 during different operating states of the device (including device turn-on, turn-on, and turn-off), enabling IGBT devices to be used in higher frequency applications.
[0088] The NMOS transistor 13 and NPN transistor 14 of the present invention are disposed between the IGBT gate 10, the dummy gate 11 and the IGBT emitter 12, without occupying additional device area. This ensures that the device can reduce both turn-off and turn-on losses in a smaller volume. Furthermore, the present invention is compatible with the manufacturing process of conventional IGBT devices, without requiring additional manufacturing equipment, and can effectively control the manufacturing cost of the device.
[0089] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. An IGBT device, characterized in that, The IGBT device includes: A substrate on which the IGBT emitter, IGBT gate and IGBT collector of an IGBT device are formed; A dummy gate is provided, which is positioned between the gate and the emitter of the IGBT; An NMOS transistor is disposed on the substrate and between the IGBT gate and the dummy gate. The source and gate of the NMOS transistor are electrically connected to the IGBT gate, and the drain is electrically connected to the dummy gate. An NPN transistor is disposed on the substrate and between the dummy gate and the emitter of the IGBT. The collector of the NPN transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor. A PNP transistor is disposed on the substrate and between the dummy gate and the emitter of the IGBT. The collector of the PNP transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through the inductor.
2. The IGBT device according to claim 1, characterized in that: When the IGBT device is turned on, a threshold voltage is applied to the IGBT gate, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, thereby connecting the IGBT gate with the dummy gate. A channel is formed under the dummy gate to reduce the conduction loss of the IGBT device.
3. The IGBT device according to claim 1, characterized in that: When the IGBT device is turned on, the current at the IGBT emitter increases, and there is a voltage change in the inductance between the PNP transistor and the IGBT emitter, which causes the PNP transistor to be in an amplification state and turn on, so that the dummy gate is connected to the IGBT emitter, thereby reducing the turn-on loss of the IGBT device.
4. The IGBT device according to claim 1, characterized in that: When the IGBT device is turned off, the current at the IGBT emitter decreases, and there is a voltage change in the inductance between the NPN transistor and the IGBT emitter, which causes the NPN transistor to be turned on in an amplification state, thus connecting the dummy gate to the IGBT emitter and reducing the turn-off loss of the IGBT device.
5. The IGBT device according to claim 1, characterized in that: The threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is less than or equal to 5V.
6. The IGBT device according to claim 1, characterized in that: The IGBT gate and the dummy gate are arranged in a ring shape, with the dummy gate surrounding the IGBT emitter and the IGBT gate surrounding the dummy gate.
7. The IGBT device according to claim 1, characterized in that: The substrate includes a first side and a second side opposite to each other. The IGBT emitter and IGBT gate are disposed on the first side of the substrate, and the IGBT collector is disposed on the second side of the substrate. The IGBT device further includes a field cutoff layer disposed in the substrate and close to the IGBT collector.
8. The IGBT device according to claim 1, characterized in that: The inductance value of the inductor is 10nH to 20nH.
9. A method for fabricating an IGBT device, characterized in that, The preparation method includes the following steps: A substrate is provided on which an IGBT emitter, an IGBT gate, an IGBT collector, and a dummy gate of an IGBT device are formed, wherein the dummy gate is disposed between the IGBT gate and the IGBT emitter; An NMOS transistor is disposed on the substrate and placed between the gate of the IGBT and the dummy gate. The source and gate of the NMOS transistor are electrically connected to the gate of the IGBT, and the drain is electrically connected to the dummy gate. An NPN transistor is disposed on the substrate and placed between the dummy gate and the emitter of the IGBT. The collector of the NPN transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor. A PNP transistor is disposed on the substrate and placed between the dummy gate and the emitter of the IGBT. The collector of the PNP transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is electrically connected to the emitter of the IGBT through an inductor.
10. The method for fabricating an IGBT device according to claim 9, characterized in that: The steps of fabricating NMOS transistors, NPN transistors, and PNP transistors on the substrate include: A first P-well, a second P-well, and an N-well are formed in the substrate by ion implantation. A gate dielectric layer and a gate layer are formed on the substrate, and an IGBT gate, a dummy gate, and an NMOS transistor gate are formed by a patterning process. The source and drain of an NMOS transistor are formed in the first P-well by ion implantation, the base and emitter of an NPN transistor are formed in the N-well, and the base and emitter of a PNP transistor are formed in the second P-well. An insulating layer is formed on the substrate, a contact hole is formed in the insulating layer, a metal layer is formed on the contact hole and the insulating layer, and a wiring layer is formed by a patterning process. Through the contact hole and the wiring layer, the source and gate of the NMOS transistor are electrically connected to the gate of the IGBT, and the drain is electrically connected to the dummy gate. The collector of the NPN transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is connected to the contact point. The collector of the PNP transistor is electrically connected to the dummy gate, the emitter is electrically connected to the emitter of the IGBT, and the base is connected to the contact point.
11. The method for fabricating an IGBT device according to claim 10, characterized in that: The method also includes the step of connecting an inductor between the contact point of the base of the NPN transistor and the PNP transistor and the emitter of the IGBT via an external pin, wherein the inductance value of the inductor is 10nH to 20nH.
12. The method for fabricating an IGBT device according to claim 11, characterized in that: When the IGBT device is turned on, a threshold voltage is applied to the IGBT gate. This threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, thereby connecting the IGBT gate to the dummy gate. A channel is formed below the dummy gate to reduce the conduction loss of the IGBT device. When the IGBT device is turned on, the current at the IGBT emitter increases, and there is a voltage change in the inductance between the PNP transistor and the IGBT emitter, causing the PNP transistor to conduct in an amplification state. This connects the dummy gate to the IGBT emitter, thereby reducing the turn-on loss of the IGBT device. When the IGBT device is turned off, the current at the IGBT emitter decreases, and there is a voltage change in the inductance between the NPN transistor and the IGBT emitter, causing the NPN transistor to conduct in an amplification state. This connects the dummy gate to the IGBT emitter, thereby reducing the turn-off loss of the IGBT device.
13. The method for fabricating an IGBT device according to claim 9, characterized in that: The threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is less than or equal to 5V.
14. The method for fabricating an IGBT device according to claim 9, characterized in that: The IGBT gate and the dummy gate are arranged in a ring shape, with the dummy gate surrounding the IGBT emitter and the IGBT gate surrounding the dummy gate.
15. The method for fabricating an IGBT device according to claim 9, characterized in that: The substrate includes a first side and a second side opposite to each other. The IGBT emitter and IGBT gate are disposed on the first side of the substrate, and the IGBT collector is disposed on the second side of the substrate. The IGBT device further includes a field cutoff layer disposed in the substrate and close to the IGBT collector.