A time-frequency signal generating device for quickly approximating an external clock reference

Abstract

The present invention provides a time-frequency signal generating device for quickly approximating an external clock reference, belonging to the technical field of time-frequency signal generation and clock synchronization. The device of the present invention includes a built-in clock, a signal approximation module, and a signal distribution module. Among them, the built-in clock outputs a local clock signal; the signal approximation module enables the clock signal output by the built-in clock to quickly approximate the externally input reference signal, generating a time-frequency signal with the same frequency and phase as the external reference signal; the signal distribution module realizes the multi-channel distribution, power amplification and output of the frequency signal and the second pulse signal. The device has low cost and fast approximation speed, and the frequency signal and the timing signal can meet the requirements of most application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical fields of time-frequency signal generation and clock synchronization, and particularly to a time-frequency signal generation device that can rapidly approximate an external clock reference. Background Art

[0002] Large electronic information systems such as satellite navigation systems, space TT&C systems, and network radar systems are highly complex and have a large number of devices. The system usually consists of a main node and many distributed sub-nodes. An important prerequisite for these system nodes to work collaboratively is high-precision time-frequency synchronization between these nodes. Therefore, during the construction of large electronic information systems, a high-precision and high-stability time-frequency system is generally built at the main node, and then the time-frequency signal is transmitted to other distributed sub-nodes through optical fibers or RF cables; these sub-nodes generally regenerate the local time-frequency signal based on the externally transmitted time-frequency reference. Currently, there have emerged various methods for regenerating time-frequency signals locally, including methods for locally constructing a secondary time-frequency reference based on a time comparison link, methods for locally taming a clock based on Beidou / GPS second pulses, methods for regenerating a phase-locked clock frequency signal based on an external frequency signal, and many other methods. Among them, the method for locally constructing a secondary time-frequency reference based on a time comparison link can achieve the regeneration of high-precision time-frequency signals at the sub-node and can also achieve high-precision synchronization with the time-frequency reference of the main node, but its construction cost is high and the link complexity is also high; the method for locally taming a clock based on Beidou / GPS second pulses can achieve the regeneration of relatively high-precision time-frequency signals at the sub-node and can also achieve relatively high-precision synchronization with the time-frequency reference of the main node, but it depends on the navigation satellite link, has insufficient anti-interference ability, and is easily interfered; the method for regenerating a phase-locked clock frequency signal based on an external frequency signal has a lower cost and stronger anti-interference ability, but it can only obtain an accurate frequency signal and cannot achieve the calibration of the timing signal. Summary of the Invention

[0003] In view of this, in the process of regenerating the local time-frequency signal by the sub-node based on the external reference signal transmitted from the main node or other nodes during the construction of large electronic information systems, the present invention aims at the problems of large frequency deviation and phase deviation that may occur, and the deficiencies that the existing solutions often have high costs, complex links, or weak anti-interference ability. A time-frequency signal generation device that can rapidly approximate an external clock reference is proposed, which can rapidly approximate the local time-frequency signal to the external reference clock signal, that is, both the locally regenerated frequency signal and the timing signal are synchronized with the external reference signal. Its construction cost is low, the approximation speed is fast, and the frequency signal and the timing signal can also meet the requirements of most application scenarios.

[0004] The object of the present invention is achieved as follows:

[0005] A time-frequency signal generating device for quickly approximating an external clock reference, comprising a built-in clock, a signal approximation module, and a signal distribution module, wherein:

[0006] The built-in clock is used to generate a local clock signal of 10 MHz Rb ;

[0007] The signal approximation module is used to measure the time difference between the 10 MHz clock signal output by the built-in clock Rb and the 1 pps reference signal input externally IN perform time difference measurement, calculate the phase deviation and frequency deviation, and then realize the rapid approximation of the local clock signal to the external reference signal through phase compensation and frequency adjustment, and generate a clock signal with the same frequency and phase as the external reference signal;

[0008] The signal distribution module is used to realize the multi-channel distribution, power amplification and output of the frequency signal and the second pulse signal.

[0009] Furthermore, the built-in clock has 2 interfaces: RS232 Rb , 10 MHz Rb ; among them, RS232 Rb is the frequency control input interface, which is the serial interface of RS232 and is used to control the frequency of the built-in clock; 10 MHz Rb adopts the SMA physical interface and is used to output 1 path of 10 MHz sine signal.

[0010] Furthermore, the signal approximation module has 5 interfaces: 1 pps IN , 10 MHz IN , 1 pps OUT , 10 MHz OUT , RS232 BJ ; among them, 1 pps IN receives the 1 pps timing signal from the outside, 10 MHz IN receives the 10 MHz signal output by the 10 MHz interface of the built-in clock Rb , 1 pps OUT outputs the 1 pps signal, 10 MHz OUT outputs the 10 MHz signal, and the RS232 BJ interface is connected to the RS232 Rb interface of the built-in clock and controls the output frequency of the built-in clock.

[0011] Further, the signal approximation module includes a shaping circuit, a frequency division circuit, a phase comparison circuit, a control circuit, a phase compensation circuit, and a phase-locked circuit. The shaping circuit is used to shape the 10 MHz signal into a 10 Mpps signal. The frequency division circuit is used to divide the 10 Mpps signal into a 1 pps signal. The phase comparison circuit is used to compare the phase of the 1 pps signal obtained by frequency division with the externally input 1 pps signal. The control circuit calculates the phase deviation and frequency deviation of the local clock signal relative to the external signal. The phase compensation circuit compensates for the phase deviation. The phase-locked circuit regenerates the 10 MH signal.

[0012] Further, the signal distribution module has multiple interfaces: Freq IN 、Pulse IN ,Freq OUT1 、Freq OUT2 、...、Freq OUTk ,Pulse OUT1 、Pulse OUT2 、...、Pulse OUTk ;Among them, Freq IN is connected to the 10 MHz OUT interface of the signal approximation module, Pulse IN is connected to the 1 pps OUT interface of the signal approximation module, Freq OUT1 、Freq OUT2 、...、Freq OUTk are k frequency signal output interfaces, and Pulse OUT1 、Pulse OUT2 、...、Pulse OUTk are k pulse signal output interfaces.

[0013] Further, the specific method for the signal approximation module to achieve the rapid approximation of the local clock signal to the external reference signal is as follows:

[0014] The phase comparison circuit compares the phase deviation between the 1 pps n signal output by the frequency division circuit within the nth measurement period T DIV and the externally input 1 pps IN signal to obtain the phase deviation ΔT n , where T n ranges from 60 s to 3600 s;

[0015] The phase compensation circuit approximately uniformly compensates for the phase difference ΔT n+1 in the (n + 1)th measurement period T n , then the phase deviation compensation value ΔT com,n+1 in the (n + 1)th measurement period is:

[0016] ΔT com,n+1 = -ΔT n (1)

[0017] To prevent the jump of the timing signal during the phase compensation process, the phase compensation circuit uses DDS + PLL with more than 32 bits for fine and slow adjustment;

[0018] The control circuit calculates the frequency deviation Δf of the built-in clock in the nth measurement period according to the measurement result of the phase comparison circuit n :

[0019]

[0020] where E0 is the frequency deviation factor;

[0021] The control circuit takes the frequency deviation Δf of the nth measurement period n as the compensation amount and sends it to the built-in clock through a serial structure. The built-in clock compensates for the frequency deviation in the (n + 1)th measurement period, and the built-in clock frequency deviation compensation value Δf in the (n + 1)th measurement period com,n+1 is:

[0022] Δf com,n+1 = -Δf n ×E com (3)

[0023] where E com is the frequency compensation factor, and the value of E com ranges from 0.5 to 0.9;

[0024] Repeat the above process to realize the compensation of the phase deviation and frequency deviation in the next measurement period, so as to realize the approximation of the local time-frequency signal to the external reference signal and generate a clock signal with the same frequency and phase as the external reference signal.

[0025] The beneficial effects of the present invention are as follows:

[0026] 1. The present invention can quickly realize the approximation of the local time-frequency signal to the external reference clock signal, that is, both the locally regenerated frequency signal and the timing signal are synchronized with the external reference signal.

[0027] 2. The present invention has low cost and fast approximation speed, and the frequency signal and the timing signal can meet the requirements of most application scenarios.

[0028] 3. The present invention can solve the problems of large frequency deviation and phase deviation that may occur during the process of regenerating local time-frequency signals from external reference signals transmitted by sub-nodes based on the master node or other nodes in the construction of large electronic information systems, and can also solve the deficiencies in the prior art, such as high cost, complex link, or weak anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic structural diagram of a time-frequency signal generating device for quickly approximating an external clock reference. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The present invention will be further described in detail below with reference to the accompanying drawings.

[0031] A time-frequency signal generating device for quickly approximating an external clock reference measures the time difference between the time-frequency signal output by the built-in clock and the reference signal input externally, and then calculates the phase deviation and frequency deviation. Through rapid phase compensation and frequency adjustment, the local time-frequency signal is quickly approximated to the external reference signal. As Figure 1 shown, the device includes three core modules: a built-in clock, a signal approximation module, and a signal distribution module. The three modules cooperate to achieve the rapid approximation of the local signal to the external reference signal and multi-channel output. Among them:

[0032] The built-in clock is used to generate a local clock signal of 10 MHz Rb ;

[0033] The signal approximation module is used to measure the time difference between the 10 MHz clock signal output by the built-in clock Rb and the 1 pps reference signal input externally IN , calculate the phase deviation and frequency deviation, and then achieve the rapid approximation of the local clock signal to the external reference signal through phase compensation and frequency adjustment, generating a clock signal with the same frequency and phase as the external reference signal;

[0034] The signal distribution module is used to achieve multi-channel distribution, power amplification, and output of the frequency signal and the second pulse signal.

[0035] The built-in clock has two interfaces: RS232 Rb , 10 MHz Rb . Among them, RS232 Rb is the frequency control input interface, which is a serial interface of RS232 and can be used to control the frequency of the built-in clock; 10 MHz Rb is the 10 MHz output interface, generally using an SMA physical interface, and can output one 10 MHz sine signal.

[0036] The signal approximation module has five interfaces: 1 ppsIN 、10 MHz IN 、1 pps OUT 、10 MHz OUT 、RS232 BJ 。Among them, 1 pps IN receives the external 1 pps timing signal, and 10 MHz IN receives the built-in clock 10 MHz Rb signal output by the interface. 1 pps OUT outputs the 1 pps signal, and 10 MHz OUT outputs the 10 MHz signal. The RS232 BJ interface is connected to the RS232 Rb interface of the built-in clock and controls the output frequency of the built-in clock.

[0037] The signal approximation module mainly consists of a shaping circuit, a frequency division circuit, a phase comparison circuit, a control circuit, a phase compensation circuit, and a phase-locked circuit. Among them, the shaping circuit shapes the 10 MHz signal into a 10 Mpps signal, the frequency division circuit divides the 10 Mpps signal into a 1 pps signal, the phase comparison circuit compares the phase of the 1 pps signal obtained by frequency division with the externally input 1 pps signal, the control circuit calculates the phase deviation and frequency deviation of the local clock signal relative to the external signal, the phase compensation circuit compensates for the phase deviation, and the phase-locked circuit regenerates the 10 MH signal.

[0038] The signal distribution module has multiple interfaces: Freq IN 、Pulse IN ,Freq OUT1 、Freq OUT2 、...、Freq OUTk ,Pulse OUT1 、Pulse OUT2 、...、Pulse OUTk ;Among them, Freq IN is connected to the 10 MHz OUT interface of the signal approximation module, Pulse IN is connected to the 1 pps OUT interface of the signal approximation module, Freq OUT1 、Freq OUT2 、...、Freq OUTk are k frequency signal output interfaces, and Pulse OUT1 、Pulse OUT2 、...、Pulse OUTk are k pulse signal output interfaces.

[0039] The specific method for the signal approximation module to achieve the rapid approximation of the local clock signal to the external reference signal is as follows:

[0040] The phase comparison circuit compares the phase deviation between the 1PPS signal output by the frequency division circuit within the nth measurement period T n and the 1PPS signal externally input, DIV obtaining the phase deviation ΔT IN , where n is a natural number, and T n ranges from 60s to 3600s; n

[0041] The phase compensation circuit approximately uniformly compensates for the phase difference ΔT n+1 in the (n + 1)th measurement period T n . Then, the phase deviation compensation value ΔT com,n+1 in the (n + 1)th measurement period is:

[0042] ΔT com,n+1 = -ΔT n (1)

[0043] To prevent jumps in the timing signal during the phase compensation process, the phase compensation circuit uses DDS + PLL with more than 32 bits for fine and slow adjustment;

[0044] The control circuit calculates the frequency deviation Δf of the built-in clock in the nth measurement period according to the measurement result of the phase comparison circuit n :

[0045]

[0046] where T n is the nth measurement period, ΔT n is the phase deviation measurement result of the phase comparison circuit in the nth measurement period, and E0 is the frequency deviation factor;

[0047] The control circuit takes the frequency deviation Δf in the nth measurement period n as the compensation amount and sends it to the built-in clock through a serial structure. The built-in clock compensates for the frequency deviation in the (n + 1)th measurement period. Then, the built-in clock frequency deviation compensation value Δf com,n+1 in the (n + 1)th measurement period is:

[0048] Δf com,n+1 = -Δf n × E com (3)

[0049] where E com is the frequency compensation factor. To prevent overshoot of the frequency, E com generally ranges from 0.5 to 0.9; ​

[0050] Repeat the above process to achieve the compensation of the phase deviation and frequency deviation in the next measurement cycle. By iterating in this way, the local time-frequency signal can be approximated to the external reference signal, and a time-frequency signal with the same frequency and phase as the external reference signal can be generated.

[0051] In summary, the present invention can quickly approximate the local time-frequency signal to the external reference clock signal, so that both the locally regenerated frequency signal and timing signal are synchronized with the external reference signal. It has low construction cost and fast approximation speed, and the frequency signal and timing signal can meet the requirements of most application scenarios.

Claims

1. A time-frequency signal generating device for quickly approximating an external clock reference, characterized in that It includes a built-in clock, a signal approximation module, and a signal distribution module, where: The built-in clock is used to generate a local clock signal of 10 MHz Rb ; The signal approximation module is used to approximate the 10MHz clock signal output by the built-in clock Rb and the 1pps reference signal input from the outside IN to measure the time difference, calculate the phase deviation and frequency deviation, and then realize the rapid approximation of the local clock signal to the external reference signal through phase compensation and frequency adjustment, generating a clock signal with the same frequency and phase as the external reference signal; The signal distribution module is used to achieve multi-channel distribution, power amplification, and output of frequency signals and second pulse signals; The signal approximation module includes a shaping circuit, a frequency division circuit, a phase comparison circuit, a control circuit, a phase compensation circuit, and a phase-locked circuit; among them, the shaping circuit is used to shape the 10 MHz signal into a 10 Mpps signal, the frequency division circuit is used to divide the 10 Mpps signal into a 1 pps signal, the phase comparison circuit is used to compare the phase of the 1 pps signal obtained by frequency division with the externally input 1 pps signal, the control circuit calculates the phase deviation and frequency deviation of the local clock signal relative to the external signal, the phase compensation circuit compensates for the phase deviation, and the phase-locked circuit regenerates the 10 MH signal; The specific way for the signal approximation module to achieve the rapid approximation of the local clock signal to the external reference signal is: The phase comparison circuit compares the phase deviation between the 1PPS signal output by the frequency division circuit within the nth measurement period T n and the externally input 1PPS signal to obtain the phase deviation ΔT DIV where T IN ranges from 60 s to 3600 s; n n ​​ The phase compensation circuit is in the (n + 1)-th measurement period T n+1 for the phase difference ΔT n to perform approximately uniform compensation. Then, the phase deviation compensation value ΔT in the (n + 1)-th measurement period com,n+1 is as follows: ΔT com,n+1 = -ΔT n (1) In order to prevent the jump of the timing signal during the phase compensation process, the phase compensation circuit uses DDS+PLL with more than 32 bits for fine and slow adjustment; The control circuit calculates the frequency deviation Δf of the built-in clock in the nth measurement period according to the measurement result of the phase comparison circuit n : Among them, E0 is the frequency deviation factor; The control circuit takes the frequency deviation Δf of the nth measurement period n as the compensation amount and sends it to the built-in clock through a serial structure. The built-in clock compensates for the frequency deviation in the (n + 1)th measurement period. Then, the built-in clock frequency deviation compensation value Δf com,n+1 in the (n + 1)th measurement period is: Δf com,n+1 = -Δf n × E com (3) Among them, E com is the frequency compensation factor, and E com takes values between 0.5 and 0.9; Repeat the above process to compensate for the phase deviation and frequency deviation in the next measurement cycle, so as to achieve the approximation of the local time-frequency signal to the external reference signal and generate a clock signal with the same frequency and phase as the external reference signal.

2. The time-frequency signal generating device for quickly approximating an external clock reference according to claim 1, wherein The built-in clock has two interfaces: RS232 Rb , 10 MHz Rb ; Among them, RS232 Rb is the frequency control input interface, which is the serial interface of RS232 and is used to control the built-in clock frequency; 10 MHz Rb adopts the SMA physical interface and is used to output a 10 MHz sine signal.

3. The time-frequency signal generating device for rapidly approximating an external clock reference according to claim 2, wherein The signal approximation module has 5 interfaces: 1pps IN , 10MHz IN , 1pps OUT , 10MHz OUT 、RS232 BJ ; Among them, 1pps IN Receive 1pps timing signal from external, 10MHz IN Receives 10MHz built-in clock Rb 10MHz signal output by the interface, 1pps OUT Output 1pps signal, 10MHz OUT Output 10MHz signal, RS232 BJ RS232 interface with built-in clock Rb The interface connects and controls the output frequency of the built-in clock.

4. A time-frequency signal generating device for quickly approximating an external clock reference according to claim 3, wherein The signal distribution module has multiple interfaces: Freq IN , Pulse IN , Freq OUT1 , Freq OUT2 ,..., Freq OUTk , Pulse OUT1 , Pulse OUT2 ,..., Pulse OUTk ; among them, Freq IN is connected to the 10MHz OUT interface of the signal approximation module, Pulse IN is connected to the 1pps OUT interface of the signal approximation module, Freq OUT1 , Freq OUT2 ,..., Freq OUTk are k frequency signal output interfaces, Pulse OUT1 , Pulse OUT2 ,..., Pulse OUTk are k pulse signal output interfaces.

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