Isolated digital output circuit and control method

Abstract

The present invention provides an isolated digital output circuit and a control method thereof. A first processor is configured to alternately send drive signals to NMOS transistors Q1 and Q2, receive feedback signals from the NMOS transistors Q1 and Q2, and determine the states of the NMOS transistors Q1 and Q2; a second processor is configured to alternately send drive signals to NMOS transistors Q3 and Q4, receive feedback signals from the NMOS transistors Q3 and Q4, and determine the states of the NMOS transistors Q1 and Q2; the first processor is further configured to stop sending drive signals to the NMOS transistors Q1 and Q2 when one of the NMOS transistors Q3 and Q4 fails, and the second processor is further configured to stop sending drive signals to the NMOS transistors Q3 and Q4 when one of the NMOS transistors Q1 and Q2 fails.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit systems, and in particular to an isolated digital output circuit and a control method. Background Art

[0002] Digital output circuits are common in the industrial field, outputting voltage signals. Rail transit vehicle control systems, in particular, require numerous digital output circuits to control digital signals from various systems to achieve system control. Because these controlled signals originate from different power supply circuits, most employ isolated outputs.

[0003] In current control systems, some digital signals are critical. Hardware failures in digital output boards can cause system output anomalies. If the CPU cannot effectively detect the signal anomaly, vehicle safety can be affected. Alternatively, even if the CPU can detect the output anomaly, it may be unable to maintain the expected output, impacting normal vehicle operation. Therefore, the accuracy and reliability of critical digital signal outputs in vehicles are crucial.

[0004] In the prior art, the input and output ends of the isolated digital output circuit are connected by one or two NMOS tubes connected in series. When the input and output are working, the NMOS tube is in the normally open state, and the input and output system cannot identify the state of the NMOS tube. The input and output system does not have the ability to disconnect the NMOS tube. This system has the following problems: (1) The NMOS tube is a power device and generates significant heat when it is turned on, which affects its service life; (2) When the NMOS tube is short-circuited, it will be in the normally open state, the load current will increase, and there will be a risk of fire; (3) Most existing digital output circuits are independent NMOS tube outputs. Although they have fault detection functions, when the NMOS short-circuit fault occurs, it cannot be discovered in time, which may cause the fault to expand on the board and lead to safety accidents. Summary of the Invention

[0005] The object of the present invention is to provide a highly reliable isolated digital output circuit and a control method thereof in order to solve the problem of low reliability of digital output circuits in the prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] An isolated digital output circuit, comprising:

[0008] The first processor and the second processor are respectively used to output a driving signal and receive a feedback signal;

[0009] NMOS transistor Q1: its gate is connected to the first processor and is used to receive the driving signal from the first processor. Its source is also connected to the first processor and is used to feed back a status signal to the first processor.

[0010] NMOS transistor Q2: its gate is connected to the first processor and is used to receive the driving signal from the first processor. Its source is also connected to the first processor and is used to feed back a status signal to the first processor.

[0011] NMOS transistor Q3: its gate is connected to the second processor and is used to receive the driving signal from the second processor. Its source is connected to the second processor and is used to feed back a status signal to the second processor.

[0012] NMOS transistor Q4: its gate is connected to the second processor and is used to receive the driving signal from the second processor. Its source is connected to the second processor and is used to feed back a status signal to the second processor.

[0013] The drain of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2 as an input terminal; the source of the NMOS transistor Q3 is connected to the source of the NMOS transistor Q4 as an output terminal; the source of the NMOS transistor Q1 and the source of the NMOS transistor Q2 are connected to the first terminal, the drain of the NMOS transistor Q3 and the drain of the NMOS transistor Q4 are connected to the second terminal, and the first terminal is connected to the second terminal;

[0014] The first processor is configured to alternately send drive signals to the NMOS transistors Q1 and Q2, receive feedback signals from the NMOS transistors Q1 and Q2, and determine the states of the NMOS transistors Q1 and Q2; the second processor is configured to alternately send drive signals to the NMOS transistors Q3 and Q4, receive feedback signals from the NMOS transistors Q3 and Q4, and determine the states of the NMOS transistors Q1 and Q2;

[0015] The first processor is further configured to send drive signals and feedback status signals of Q1 and Q2 to the second processor according to a fixed communication cycle; the second processor is further configured to send drive signals and feedback status signals of Q3 and Q4 to the first processor according to a fixed communication cycle; the first processor is further configured to stop sending drive signals to NMOS transistors Q1 and Q2 when NMOS transistor Q3 or NMOS transistor Q4 fails, and the second processor is further configured to stop sending drive signals to NMOS transistors Q3 and Q4 when NMOS transistor Q1 or NMOS transistor Q2 fails.

[0016] In some embodiments of the present invention, the isolated digital output circuit further includes:

[0017] A first isolation driver and a second isolation driver: both connected to the first processor, receiving a driving signal sent by the first processor and respectively sending a driving signal;

[0018] NMOS transistor Q1: its gate is connected to the first isolation driver, and is used to receive the driving signal sent by the first isolation driver;

[0019] NMOS transistor Q2: its gate is connected to the second isolation driver, and is used to receive the driving signal sent by the second isolation driver;

[0020] The third isolation driver and the fourth isolation driver are both connected to the second processor, receive the driving signal sent by the second processor and respectively send out driving signals;

[0021] NMOS transistor Q3: its gate is connected to the third isolation driver, and is used to receive a driving signal from the third isolation driver;

[0022] NMOS transistor Q4: its gate is connected to the fourth isolation driver, and is used to receive the driving signal sent by the fourth isolation driver.

[0023] In some embodiments of the present invention, the isolated digital output circuit further includes:

[0024] A first isolation detector: an input end is connected to the source output end of the NMOS transistor Q1, and an output end is connected to the first processor;

[0025] A second isolation detector: an input end is connected to the source output end of the NMOS transistor Q2, and an output end is connected to the first processor;

[0026] A third isolation detector: an input end is connected to the source output end of the NMOS transistor Q1, and an output end is connected to the second processor;

[0027] The fourth isolation detector has an input end connected to the source output end of the NMOS transistor Q2 and an output end connected to the second processor.

[0028] In some embodiments of the present invention: the first processor is configured such that a period of the conduction control level output to the NMOS transistor Q1 overlaps with a period of the conduction control level output to the NMOS transistor Q2;

[0029] The second processor is configured such that a period of the conduction control level output to the NMOS transistor Q3 overlaps with a period of the conduction control level output to the NMOS transistor Q4.

[0030] A second embodiment of the present invention provides a control method for an isolated digital output circuit, which is used to control the isolated digital output circuit described in the above embodiment, including the following steps:

[0031] The conduction control levels alternately output to the NMOS transistors Q1 and Q2, and the conduction control levels alternately output to the NMOS transistors Q3 and Q4;

[0032] Detect the conduction status of NMOS tube Q1 and NMOS tube Q2;

[0033] If the control level of NMOS transistor Q1 does not match the conduction state of NMOS transistor Q1, or the control level of NMOS transistor Q2 does not match the conduction state of NMOS transistor Q2, the conduction control level is stopped from being sent to NMOS transistors Q1, NMOS transistors Q2, NMOS transistors Q3, and NMOS transistors Q4.

[0034] In some embodiments of the present invention, the following steps are further included:

[0035] Detecting the conduction status of NMOS tube Q3 and NMOS tube Q4;

[0036] If the control level of NMOS transistor Q3 does not match the conduction state of NMOS transistor Q3, or the control level of NMOS transistor Q4 does not match the conduction state of NMOS transistor Q4, the conduction control level is stopped from being sent to NMOS transistors Q1, NMOS transistors Q2, NMOS transistors Q3, and NMOS transistors Q4.

[0037] In some embodiments of the present invention, a period of the conduction control level output by the first processor to the NMOS transistor Q1 overlaps with a period of the conduction control level output by the first processor to the NMOS transistor Q2.

[0038] In some embodiments of the present invention, the period of the conduction control level output by the second processor to the NMOS transistor Q3 overlaps with the period of the conduction control level output by the second processor to the NMOS transistor Q4.

[0039] In some embodiments of the present invention, the first processor sends drive signals and feedback status signals of the NMOS transistors Q1 and Q2 to the second processor according to a fixed communication cycle; and the second processor sends drive signals and feedback status signals of the NMOS transistors Q3 and Q4 to the first processor according to a fixed communication cycle.

[0040] The isolated digital output circuit and control method provided by the present invention have the following beneficial effects:

[0041] 1) Most existing digital output circuits use independent NMOS transistors for output. In the present invention, four NMOS transistors are connected in parallel in pairs, achieving dynamic conduction and shutdown, ensuring that there is a conduction loop at any time. This shortens the conduction time of a single NMOS transistor, reduces device loss, and extends the service life of the device.

[0042] 2) When the output circuit of the present invention is turned on, it adopts an output structure in which two NMOS transistors are connected in parallel as a group. The processor dynamically switches the NMOS transistors on and off alternately, and detects the conduction state of the NMOS transistors in real time. This can promptly identify NMOS short-circuit faults and guide the faults to the safe side, thereby improving the safety of the circuit.

[0043] 3) The present invention adopts an output structure in which two NMOS are connected in parallel as a group and the two groups of NMOS are connected in series. When one group of NMOS fails and cannot be effectively disconnected, the processor corresponding to the faulty group of NMOS transmits the fault to the processor corresponding to the other group of NMOS, and the output structure in which the two groups of NMOS are connected in series can be disconnected in time, directing the fault to the safe side, thereby improving the safety of the circuit.

[0044] 4) The present invention electrically isolates the processor and digital logic control circuit from the NMOS tube and the fault detection module to prevent strong electricity from interfering with the normal operation of the weak current control circuit, thereby improving the safety of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 It is an isolated digital output circuit topology;

[0047] Figure 2 A logic diagram for controlling and detecting the NMOS transistor Q1 and the NMOS transistor Q2 by the first processor;

[0048] Figure 3 This is a flow chart of the control method for the isolated digital output circuit. DETAILED DESCRIPTION

[0049] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0050] The first embodiment of the present invention provides an isolated digital output circuit, the structure of which is referenced Figure 1 .

[0051] The isolated digital output circuit structure is as follows.

[0052] It includes a first processor and a second processor: respectively used for outputting a driving signal and receiving a feedback signal; wherein the driving signal is used to drive the conduction of the four NMOS tubes described below.

[0053] NMOS transistor Q1: its gate is connected to the first processor and is used to receive the driving signal from the first processor. Its source is also connected to the first processor and is used to feed back a status signal to the first processor.

[0054] NMOS transistor Q2: its gate is connected to the first processor and is used to receive the driving signal from the first processor. Its source is also connected to the first processor and is used to feed back a status signal to the first processor.

[0055] NMOS transistor Q3: its gate is connected to the second processor and is used to receive the driving signal from the second processor. Its source is connected to the second processor and is used to feed back a status signal to the second processor.

[0056] NMOS transistor Q4: its gate is connected to the second processor and is used to receive the driving signal from the second processor. Its source is connected to the second processor and is used to feed back a status signal to the second processor.

[0057] The drain of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2, serving as an input terminal, which is usually connected to an external power supply. The source of the NMOS transistor Q3 is connected to the source of the NMOS transistor Q4, serving as an output terminal, which is usually a power supply output terminal that outputs an electrical signal. The source of the NMOS transistor Q1 and the source of the NMOS transistor Q2 are connected to a first terminal, and the drain of the NMOS transistor Q3 and the drain of the NMOS transistor Q4 are connected to a second terminal. The first terminal and the second terminal are connected.

[0058] The first processor is configured to alternately send drive signals to the NMOS transistors Q1 and Q2, receive feedback signals from the NMOS transistors Q1 and Q2, and determine the states of the NMOS transistors Q1 and Q2; the second processor is configured to alternately send drive signals to the NMOS transistors Q3 and Q4, receive feedback signals from the NMOS transistors Q3 and Q4, and determine the states of the NMOS transistors Q1 and Q2;

[0059] The first processor is further configured to stop sending drive signals to NMOS transistors Q1 and Q2 when NMOS transistor Q3 or NMOS transistor Q4 fails, and the second processor is further configured to stop sending drive signals to NMOS transistors Q3 and Q4 when NMOS transistor Q1 or NMOS transistor Q2 fails.

[0060] The above structure discloses two groups of NMOS transistor units, each of which includes a processor and two NMOS transistors connected in parallel. The two groups of NMOS transistor units are interconnected. The first and second processors are signal processing modules responsible for signal detection and arbitration control. Through this structure, the two processor modules control the on / off state of the four NMOS transistors and detect the on / off state of the four NMOS transistors. Based on specific control and detection logic, the on / off state of the four NMOS transistors in the main circuit is detected. Faults are promptly identified based on the on / off state of the four NMOS transistors, ensuring the functional safety of the controller.

[0061] In some embodiments of the present invention, the isolated digital output circuit further includes:

[0062] The first isolation driver U1 and the second isolation driver U4 are both connected to the first processor, receive the driving signal sent by the first processor and respectively send out driving signals;

[0063] NMOS transistor Q1: its gate is connected to the first isolation driver U1, and is used to receive the driving signal sent by the first isolation driver U1;

[0064] NMOS transistor Q2: its gate is connected to the second isolation driver U4, and is used to receive the driving signal sent by the second isolation driver U4;

[0065] The third isolation driver U6 and the fourth isolation driver U9 are both connected to the second processor, receive the driving signal sent by the second processor and respectively send out driving signals;

[0066] NMOS transistor Q3: its gate is connected to the third isolation driver U6, and is used to receive the driving signal sent by the third isolation driver U6;

[0067] NMOS transistor Q4: its gate is connected to the fourth isolation driver U9, and is used to receive the driving signal sent by the fourth isolation driver U9.

[0068] The first isolation driver U1, the second isolation driver U4, the third isolation driver U6, and the fourth isolation driver U9 are isolation driver modules for the four output drive signals output by the data processor. Each output signal isolation driver module electrically isolates the control output signal from the signal processor from the main circuit of the controlled side, and generates a drive signal to drive the corresponding NMOS tube on and off. The four NMOS field-effect transistors execute the on-off logic issued by the execution processor.

[0069] In some embodiments of the present invention, the isolated digital output circuit further includes an isolation detector, wherein each isolation detection module detects the on / off state of the corresponding NMOS transistor and transmits the state information to the corresponding processor. Specifically,

[0070] First isolation detector U2: The input end is connected to the source output end of the NMOS transistor Q1, and the output end is connected to the first processor, and is used to detect the state of the NMOS transistor Q1 and feed back to the first processor;

[0071] Second isolation detector U3: the input end is connected to the source output end of the NMOS transistor Q2, and the output end is connected to the first processor, for detecting the state of the NMOS transistor Q2 and feeding back to the first processor;

[0072] A third isolation detector U7 has an input end connected to the source output end of the NMOS transistor Q1 and an output end connected to the second processor, and is used to detect the state of the NMOS transistor Q3 and feed back the state to the second processor;

[0073] The fourth isolation detector U8 has an input end connected to the source output end of the NMOS transistor Q2 and an output end connected to the second processor, and is used to detect the state of the NMOS transistor Q4 and feed back the state to the second processor.

[0074] The first processor module sends on / off logic signals to the first isolation driver U1 and the second isolation driver U4 modules. First and second isolation drivers U1 and U4 perform high-voltage electrical isolation on the logic from the first processor and generate on / off drive logic signals to respectively turn NMOS transistors Q1 and Q2 on and off. When NMOS transistors Q1 and Q2 are on, the main circuit input voltage is transmitted from the drain to the source. First and second isolation detectors U2 and U3 detect the main circuit input voltage and feed the isolated logic level back to the first processor.

[0075] The second processor module sends on / off logic signals to the third isolation driver U6 and the fourth isolation driver U9. Third and fourth isolation drivers U6 and U9 perform high-voltage isolation processing on the logic from the processor and generate on / off drive logic signals to respectively turn NMOS transistors Q3 and Q4 on and off. When NMOS transistors Q3 and Q4 are on, the main circuit input voltage is transmitted from the drain to the source. The third and fourth isolation detectors U7 and U8 detect the main circuit input voltage and feed the isolated logic level back to the second processor.

[0076] In some embodiments of the present invention: the first processor is configured such that a period of the conduction control level output to the NMOS transistor Q1 overlaps a period of the conduction control level output to the NMOS transistor Q2;

[0077] The second processor is configured such that a period of the conduction control level output to the NMOS transistor Q3 overlaps with a period of the conduction control level output to the NMOS transistor Q4.

[0078] The above method for controlling the NMOS transistor by the processor will be described in detail in the second embodiment.

[0079] A second embodiment of the present invention provides a control method for an isolated digital output circuit, which is used to control the isolated digital output circuit described in the first embodiment.

[0080] Method flow reference Figure 3 , specifically including the following steps:

[0081] The conduction control levels alternately output to the NMOS transistors Q1 and Q2, and the conduction control levels alternately output to the NMOS transistors Q3 and Q4;

[0082] Detect the conduction status of NMOS tube Q1 and NMOS tube Q2;

[0083] If the control level of NMOS transistor Q1 does not match the conduction state of NMOS transistor Q1, or if the control level of NMOS transistor Q2 does not match the conduction state of NMOS transistor Q2, the transmission of the conduction control level to NMOS transistors Q1, Q2, Q3, and Q4 is stopped. The control level and conduction state monitoring method is as follows: the first processor transmits the drive signal and feedback state signal of NMOS transistors Q1 and Q2 to the second processor according to a fixed communication cycle; and the second processor transmits the drive signal and feedback state signal of NMOS transistors Q3 and Q4 to the first processor according to a fixed communication cycle.

[0084] The details are as follows.

[0085] The first processor module generates a logic-level EN_A1 signal, which is passed through the first isolation driver module U1 to generate a logic-level P_EN_A1. The first processor module also generates a logic-level EN_B1 signal, which is passed through the second isolation driver module U4 to generate a logic-level P_EN_B1. When P_EN_A1 and P_EN_B1 are logic 1, NMOS transistors Q1 and Q2 are turned on. The input voltage is transmitted through the turned-on NMOS transistors Q1 and Q2 to their respective source stages, corresponding to logic levels P_FB_A1 and P_FB_B1, respectively. Logic level P_FB_A1 is passed through the first isolation detector U2 to generate logic level FB_A1, and P_FB_B1 is passed through the second isolation detector U3 to generate logic level FB_B1. If FB_A1 and FB_B1 are logic 1, it indicates that Q1 and Q2 are turned on.

[0086] The first processor module compares the logic levels of the control level signal EN_A1 and the conduction state signal FB_A1, and the control level signal EN_B1 and the conduction state signal FB_B1. When the logic levels of EN_A1 and FB_A1 match, it indicates that NMOS transistor Q1 has executed the processor's turn-on instruction and its detection function is normal. When the logic levels of EN_A1 and FB_A1 do not match, it indicates that the closed-loop circuit formed by the first isolation drive circuit U1, NMOS transistor Q1, and the first isolation detection circuit U2 is malfunctioning. The first processor immediately controls NMOS transistor Q2 to disconnect and sends a fault message to the second processor, which immediately disconnects NMOS transistors Q3 and Q4. This prevents the fault from escalating and redirects the output circuit to a safe location, preventing any safety incidents.

[0087] In some embodiments of the present invention, the control method further includes a detection and control step of the NMOS transistor Q3 and the NMOS transistor Q4 controlled by the second processor. The control method further includes the following steps:

[0088] Detecting the conduction status of NMOS tube Q3 and NMOS tube Q4;

[0089] If the control level of NMOS transistor Q3 does not match the conduction state of NMOS transistor Q3, or the control level of NMOS transistor Q4 does not match the conduction state of NMOS transistor Q4, the conduction control level is stopped from being sent to NMOS transistors Q1, NMOS transistors Q2, NMOS transistors Q3, and NMOS transistors Q4.

[0090] The above control principle is the same as the control method and principle of the first processor on the NMOS transistor Q1 and the NMOS transistor Q2 described in detail above, and will not be repeated here.

[0091] The two groups of NMOS tubes are connected in series. Through the above control method, when one group of NMOS tubes fails, the other group of NMOS tubes can be controlled to be disconnected in time and stop working, thereby improving the reliability of the circuit.

[0092] refer to Figure 2 The first processor has two output control signals, EN_A1 and EN_B1, and two input detection signals, FB_A1 and FB_B1. The second processor, identical to processor-1, has two output control signals, EN_A2 and EN_B2, and two input detection signals, FB_A2 and FB_B2. In some embodiments of the present invention, the period of the conduction control level output by the first processor to NMOS transistor Q1 overlaps with the period of the conduction control level output to NMOS transistor Q2.

[0093] Specifically, the output control logic signal EN_A1 for NMOS transistor Q1 and the output control logic signal EN_B1 for NMOS transistor Q2 are sent alternately, causing NMOS transistors Q1 and Q2 to alternately turn on. Detection signals FB-A1 and FB-B1 provide feedback on the switching conditions of NMOS transistors Q1 and Q2, thereby diagnosing whether the NMOS transistors are faulty. When the control logic signal EN_A1 and the control logic signal EN_B1 have an overlapping high-level region, both NMOS transistors Q1 and Q2 are turned on, ensuring continuity of the parallel structure of NMOS transistors Q1 and Q2 and preventing interruptions in system output.

[0094] Similarly, in some embodiments of the present invention, the period of the conduction control level output by the second processor to NMOS transistor Q3 overlaps with the period of the conduction control level output to NMOS transistor Q4. The control period for NMOS transistor Q3 can be the same as the control period for NMOS transistor Q1, and the control period for NMOS transistor Q4 can be the same as the control period for NMOS transistor Q2. The principles are the same as those described above for the control logic signals for NMOS transistors Q1 and Q2 and are not further elaborated.

[0095] The present invention provides a high-security isolated digital output circuit and acquisition method. Applying the output circuit provided by the present invention to rail vehicles can effectively improve the reliability and safety of the vehicle's key digital signal output, and can effectively avoid vehicle control failures caused by output abnormalities due to hardware failures in the output board. This is of great significance to improving the reliability and safety of vehicle operation and meets high-reliability and high-safety application scenarios.

[0096] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An isolated digital output circuit, characterized in that: include: The first processor and the second processor are respectively used to output a driving signal and receive a feedback signal; NMOS transistor Q1: its gate is connected to the first processor and is used to receive the driving signal from the first processor. Its source is connected to the first processor and is used to feed back a status signal to the first processor. NMOS transistor Q2: its gate is connected to the first processor and is used to receive the driving signal from the first processor. Its source is also connected to the first processor and is used to feed back a status signal to the first processor. NMOS transistor Q3: its gate is connected to the second processor and is used to receive the driving signal from the second processor. Its source is connected to the second processor and is used to feed back a status signal to the second processor. NMOS transistor Q4: its gate is connected to the second processor and is used to receive the driving signal from the second processor. Its source is connected to the second processor and is used to feed back a status signal to the second processor. The drain of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2 as an input terminal; the source of the NMOS transistor Q3 is connected to the source of the NMOS transistor Q4 as an output terminal; the source of the NMOS transistor Q1 and the source of the NMOS transistor Q2 are connected to the first terminal, the drain of the NMOS transistor Q3 and the drain of the NMOS transistor Q4 are connected to the second terminal, and the first terminal is connected to the second terminal; The first processor is configured to alternately send drive signals to the NMOS transistors Q1 and Q2, receive feedback signals from the NMOS transistors Q1 and Q2, and determine the states of the NMOS transistors Q1 and Q2; the second processor is configured to alternately send drive signals to the NMOS transistors Q3 and Q4, receive feedback signals from the NMOS transistors Q3 and Q4, and determine the states of the NMOS transistors Q1 and Q2; The first processor is further configured to stop sending drive signals to NMOS transistors Q1 and Q2 when NMOS transistor Q3 or NMOS transistor Q4 fails; the second processor is further configured to stop sending drive signals to NMOS transistors Q3 and Q4 when NMOS transistor Q1 or NMOS transistor Q2 fails.

2. The isolated digital output circuit according to claim 1, wherein: Further including: A first isolation driver and a second isolation driver: both connected to the first processor, receiving a driving signal sent by the first processor and respectively sending a driving signal; NMOS transistor Q1: its gate is connected to the first isolation driver, and is used to receive the driving signal sent by the first isolation driver; NMOS transistor Q2: its gate is connected to the second isolation driver, and is used to receive the driving signal sent by the second isolation driver; The third isolation driver and the fourth isolation driver are both connected to the second processor, receive the driving signal sent by the second processor and respectively send out driving signals; NMOS transistor Q3: its gate is connected to the third isolation driver, and is used to receive a driving signal from the third isolation driver; NMOS transistor Q4: its gate is connected to the fourth isolation driver, and is used to receive the driving signal sent by the fourth isolation driver.

3. The isolated digital output circuit according to claim 1, wherein: Further including: A first isolation detector: an input end is connected to the source output end of the NMOS transistor Q1, and an output end is connected to the first processor; A second isolation detector: an input end is connected to the source output end of the NMOS transistor Q2, and an output end is connected to the first processor; A third isolation detector: an input end is connected to the source output end of the NMOS transistor Q1, and an output end is connected to the second processor; The fourth isolation detector has an input end connected to the source output end of the NMOS transistor Q2 and an output end connected to the second processor.

4. The isolated digital output circuit according to claim 1, wherein: The first processor is configured to: overlap a period of the conduction control level output to the NMOS transistor Q1 with a period of the conduction control level output to the NMOS transistor Q2; The second processor is configured such that a period of the conduction control level output to the NMOS transistor Q3 overlaps with a period of the conduction control level output to the NMOS transistor Q4.

5. The isolated digital output circuit according to any one of claims 1 to 4, wherein: The first processor is further configured to send drive signals and feedback status signals of NMOS transistors Q1 and Q2 to the second processor according to a fixed communication cycle; the second processor is further configured to send drive signals and feedback status signals of NMOS transistors Q3 and Q4 to the first processor according to a fixed communication cycle.

6. A control method for an isolated digital output circuit, used for controlling the isolated digital output circuit according to any one of claims 1 to 4, characterized in that: The following steps are involved: The conduction control levels alternately output to the NMOS transistors Q1 and Q2, and the conduction control levels alternately output to the NMOS transistors Q3 and Q4; Detect the conduction status of NMOS tube Q1 and NMOS tube Q2; If the control level of NMOS transistor Q1 does not match the conduction state of NMOS transistor Q1, or the control level of NMOS transistor Q2 does not match the conduction state of NMOS transistor Q2, the conduction control level is stopped from being sent to NMOS transistors Q1, NMOS transistors Q2, NMOS transistors Q3, and NMOS transistors Q4.

7. The control method of the isolated digital output circuit according to claim 5, wherein: Further comprising the steps of: Detecting the conduction status of NMOS tube Q3 and NMOS tube Q4; If the control level of NMOS transistor Q3 does not match the conduction state of NMOS transistor Q3, or the control level of NMOS transistor Q4 does not match the conduction state of NMOS transistor Q4, the conduction control level is stopped from being sent to NMOS transistors Q1, NMOS transistors Q2, NMOS transistors Q3, and NMOS transistors Q4.

8. The control method of the isolated digital output circuit according to claim 6, wherein: The period of the conduction control level output by the first processor to the NMOS transistor Q1 overlaps with the period of the conduction control level output by the first processor to the NMOS transistor Q2.

9. The control method of the isolated digital output circuit according to claim 6, wherein: The period of the conduction control level output by the second processor to the NMOS transistor Q3 overlaps with the period of the conduction control level output by the second processor to the NMOS transistor Q4.

10. The control method of the isolated digital output circuit according to claim 7, wherein: The first processor sends the driving signals and feedback status signals of NMOS transistors Q1 and Q2 to the second processor according to a fixed communication cycle; the second processor sends the driving signals and feedback status signals of NMOS transistors Q3 and Q4 to the first processor according to a fixed communication cycle.

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