Globally reconfigurable analog-to-digital conversion method and circuit for storage and computing

Abstract

The present invention discloses a global reconfigurable analog-to-digital conversion method and circuit for storage and computing, which belongs to the field of integrated circuit technology. In order to solve the problem of the existing reconfigurable analog-to-digital converter being too large in area and to realize the reconfigurable function while reducing the area overhead, the reconfigurable analog-to-digital converter for storage and computing of the present invention includes: a reconfigurable global reference voltage generation circuit and a local analog-to-digital conversion circuit; in view of the array application characteristics of ADC in the storage and computing array, the reference voltage generation circuit for realizing the reconfigurable function is designed to be globally multiplexed. The analog-to-digital conversion is realized by a switched capacitor circuit, which avoids the area consumption caused by a large number of capacitors and improves the computing density of the storage and computing integrated chip. At the same time, combined with the successive approximation conversion strategy, a higher conversion speed is achieved to meet the demand for higher computing power of the storage and computing integrated technology.

Description

Technical Field

[0001] The present invention relates to a global reconfigurable analog-to-digital conversion method and circuit for storage and calculation, and belongs to the technical field of integrated circuits. Background Art

[0002] As deep learning is widely used in many cognitive tasks, such as image classification and speech recognition, the existing von Neumann computing architecture, due to its separation of compute and storage, significantly limits data bandwidth and fails to meet the application requirements of edge computing devices, such as low latency, high reliability, and efficient network bandwidth utilization. The compute-storage architecture significantly reduces data transfer between the compute engine and memory, breaking the storage and power consumption bottlenecks of the traditional von Neumann architecture and becoming widely used in the training and inference of various neural networks.

[0003] Most in-memory computing architectures require large-scale analog-to-digital converter (ADC) arrays to quantize analog computation results into digital codes for subsequent calculations (such as activation and pooling). As application requirements continue to increase, the bit widths of inputs, weights, and outputs in in-memory computing architectures continue to increase. A trade-off needs to be made between the accuracy requirements and power consumption of neural networks, and the input, weight, and output bit widths are typically adjusted. When the accuracy requirements of neural networks are high, selecting high-precision inputs, weights, and outputs combined with high-conversion-accuracy ADCs for data readout can ensure the accuracy of the entire neural network inference. When the requirements are lower, only a lower-conversion-accuracy ADC is required for readout, which improves the readout speed and saves power, achieving an optimized design suitable for the accuracy and speed requirements of in-memory computing.

[0004] Traditional ADC structures, such as flash ADCs and SAR ADCs, are most widely used in storage-computation readout architectures. Flash ADCs offer better performance for lower precision (3 bits or less), while SAR ADCs offer better performance for relatively higher precision. This single-source nature of traditional structures severely limits the flexibility of integrated storage-computation chip arrays and becomes a bottleneck in the energy efficiency and computational density of storage-computing chips.

[0005] The resolutions of existing in-memory computing neural networks vary, and even within the same neural network, the optimal output resolutions of different layers are not exactly the same. As the name suggests, a reconfigurable ADC is an ADC in which one or more parameters such as resolution and sampling frequency can be reconfigured. The reconfigurable ADC can operate in different conversion accuracy and speed performance combinations according to the output resolution requirements of different layers. When the output resolution requirement of the neural network is low, the ADC is reconfigured to a low-resolution mode, reducing overall power consumption while increasing overall computing speed. Compared to ordinary ADC structures with fixed resolution and sampling frequency, reconfigurable ADCs have greater flexibility and can achieve faster computing speeds while ensuring computing accuracy.

[0006] The ADC structures commonly used in the existing storage and computing fields basically have their own reconfigurable methods. The reconfigurable method of Flash ADC is usually to synchronously power on or off one or more sub-ADCs through a clock control module to achieve configurable resolution. The more sub-ADCs that are powered on, the higher the resolution, but the greater the overall power consumption of the circuit. The literature (Ali M, Chakraborty I, Saxena U, et al. A 35.5-127.2tops / w dynamic sparsity-awarereconfigurable-precision compute-in-memory sram macro for machine learning [J]. IEEE Solid-State Circuits Letters, 2021, 4: 129-132.) proposes a reconfigurable ADC structure for storage and computing. Through the combination of segmented capacitor arrays, 2 to 6 bit resolution can be reconfigured. The invention patent (CN104506195 B) combines the resolution configurable algorithm into the successive approximation algorithm to achieve 8 to 12 bit resolution configuration. The 3-8-bit reconfigurable ADC proposed in the literature (Fan W, Li Y, Du L, et al. A 3-8-bit reconfigurable hybrid ADC architecture with successive-approximation and single-slope stages for computing in memory [C] / / 2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2022: 3393-3397.) is based on a SAR / SS architecture. This architecture reconfigures the slope in the SS ADC into a reconfigurable slope to adjust resolution. Another reconfigurable solution uses a cyclic ADC structure, such as the invention patent (CN 103944569 B), which uses a two-stage cyclic structure to achieve 6-12-bit accuracy.

[0007] Although the above-mentioned existing reconfigurable analog-to-digital converter structure realizes the function of reconfigurable resolution, for the gradually expanding storage and computing array, the area consumption caused by the large number of capacitor arrays or multiple precise multiplication by 2 and redundant calibration circuits contained therein seriously limits the improvement of the overall computing density of the chip. Summary of the Invention

[0008] In order to solve the problem of excessive area of ​​existing reconfigurable analog-to-digital converters and realize reconfigurable functions while reducing area overhead, the present invention provides a storage-based reconfigurable analog-to-digital converter, comprising: a reconfigurable global reference voltage generation circuit and a local analog-to-digital conversion circuit;

[0009] The reconfigurable global reference voltage generating circuit includes: a global DAC and a resolution control logic circuit; the resolution control logic circuit generates a global reference voltage according to a resolution control signal CR <m:0>and clock signal CLKC output D <k:0>, and the value output in each cycle is half of the previous cycle; the global DAC outputs the data D of the resolution control logic circuit <k:0>Converted into a corresponding voltage signal and output to all local analog-to-digital conversion circuits in the entire array as a global reference voltage V REF_GDAC .

[0010] Optionally, the local analog-to-digital conversion circuit includes a switched capacitor circuit, an operational amplifier OPA, a comparator and a conversion logic circuit;

[0011] The switch capacitor circuit is connected to the operational amplifier OPA for sampling the input signal and comparing it with the global reference voltage value V REF_GDAC Perform addition and subtraction operations and transfer them to the positive input terminal of the comparator;

[0012] The comparator is used to compare the output value of the operational amplifier OPA with the reference voltage value V REF Compare and output the corresponding bit code value;

[0013] The conversion logic circuit is used to determine the subsequent addition / subtraction operation according to the binary code value output by the comparator, generate a corresponding switch control signal, and output a quantized digital code.

[0014] Optionally, the switch capacitor circuit includes: a sampling switch SAMPLE, a sampling capacitor C S , first switch S1, second switch S2, third switch S3, fourth switch S4, holding capacitor C H , initialization switch INT and reset switch RST;

[0015] One end of the sampling switch SAMPLE is connected to the input, and the other end is connected to the sampling capacitor C S , initialization switch INT and the negative input terminal of the operational amplifier OPA; one end of the first switching switch S1 and the second switching switch S2 is connected to the global reference voltage V REF_GDAC , and the other end is connected to the sampling capacitor C S The third switch S3 and the fourth switch S4 are connected to the positive input terminal of the operational amplifier OPA at one end, and the other end is connected to the sampling capacitor C S The holding capacitor C H It is connected in parallel with the reset switch RST, and both ends are connected to the negative input terminal and the output terminal of the operational amplifier OPA respectively.

[0016] Optionally, the global DAC is implemented using a segmented capacitor structure.

[0017] Optionally, the storage-computing oriented reconfigurable analog-to-digital converter is a 1-8 bit reconfigurable analog-to-digital converter.

[0018] Optionally, the control signal of the reset switch RST is valid at a high level.

[0019] Optionally, the control signal of the sampling switch SAMPLE is valid at a high level.

[0020] Optionally, the control signal of the initialization switch INT is valid at a high level.

[0021] Optionally, the control signals of the first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 are high level valid.

[0022] A second object of the present invention is to provide a storage-computing-oriented reconfigurable analog-to-digital conversion method, which is implemented based on the above-mentioned storage-computing-oriented reconfigurable analog-to-digital converter and includes:

[0023] The reconfigurable global reference voltage is used to generate a circuit global reference voltage; and the local analog-to-digital conversion circuit is used to implement analog-to-digital conversion and output a conversion result.

[0024] The beneficial effects of the present invention are:

[0025] This invention addresses the array-based application characteristics of ADCs in storage and computing arrays by designing a globally reusable reference voltage generation circuit that implements reconfigurable functionality. Analog-to-digital conversion is implemented using a switched-capacitor circuit, avoiding the area consumption associated with large capacitors and improving the computational density of the integrated storage and computing chip. Furthermore, combined with a successive approximation conversion strategy, it achieves a high conversion speed, meeting the demand for higher computing power in integrated storage and computing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 This is a block diagram of the overall architecture of the reconfigurable analog-to-digital converter of the present invention in array applications.

[0028] Figure 2 This is an overall structural diagram of the storage-computing-oriented reconfigurable analog-to-digital converter in the second embodiment of the present invention.

[0029] Figure 3 This is the overall working timing diagram of the 1-8 bit reconfigurable analog-to-digital converter in the second embodiment of the present invention.

[0030] Figure 4 This is a circuit diagram of a 1-8 bit reconfigurable global reference voltage generating circuit in the second embodiment of the present invention.

[0031] Figure 5 This is a diagram of the output signal spectrum of the 1-8 bit reconfigurable analog-to-digital converter in the second embodiment of the present invention operating in the 8-bit mode. DETAILED DESCRIPTION

[0032] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0033] Example 1:

[0034] This embodiment provides a reconfigurable analog-to-digital converter for storage and calculation. Figure 2 , including: a reconfigurable global reference voltage generation circuit and a local analog-to-digital conversion circuit;

[0035] The reconfigurable global reference voltage generating circuit includes: a global DAC and a resolution control logic circuit; the resolution control logic circuit generates a global reference voltage according to the resolution control signal CR. <m:0>and clock signal CLKC output D <k:0>, and the output value of each cycle is half of the previous cycle; the global DAC converts the data D output by the resolution control logic circuit <k:0>Converted into a corresponding voltage signal and output to all local analog-to-digital conversion circuits in the entire array as a global reference voltage V REF_GDAC .

[0036] Example 2:

[0037] This embodiment provides a reconfigurable analog-to-digital converter for storage and calculation. Figure 2 , including: a reconfigurable global reference voltage generation circuit and a local analog-to-digital conversion circuit;

[0038] The reconfigurable global reference voltage generating circuit includes: a global DAC and a resolution control logic circuit; the resolution control logic circuit generates a global reference voltage according to a resolution control signal CR. <m:0>and clock signal CLKC output D <k:0>, and the output value of each cycle is half of the previous cycle; the global DAC is implemented using a segmented capacitor structure, which converts the data D output by the resolution control logic circuit into <k:0>Converted into a corresponding voltage signal and output to all local analog-to-digital conversion circuits in the entire array as a global reference voltage V REF_GDAC .

[0039] The local analog-to-digital conversion circuit includes a switched capacitor circuit, an operational amplifier OPA, a comparator and a conversion logic circuit;

[0040] The switched capacitor circuit is connected to the operational amplifier OPA to sample the input signal and compare it with the global reference voltage value V REF_GDAC Perform addition and subtraction operations and transfer them to the positive input of the comparator;

[0041] The comparator is used to compare the output value of the operational amplifier OPA with the reference voltage value V REF Compare and output the corresponding bit code value;

[0042] The conversion logic circuit is used to determine the subsequent addition / subtraction operation according to the binary code value output by the comparator, generate the corresponding switch control signal, and output the quantized digital code.

[0043] The switched capacitor circuit includes: sampling switch SAMPLE, sampling capacitor C S , first switch S1, second switch S2, third switch S3, fourth switch S4, holding capacitor C H , initialization switch INT and reset switch RST;

[0044] One end of the sampling switch SAMPLE is connected to the input, and the other end is connected to the sampling capacitor C S , initialization switch INT and the negative input terminal of the operational amplifier OPA; one end of the first switch S1 and the second switch S2 is connected to the global reference voltage V REF_GDAC , and the other end is connected to the sampling capacitor C S One end of the third switch S3 and the fourth switch S4 are connected to the positive input terminal of the operational amplifier OPA, and the other end are connected to the sampling capacitor C S Both ends of the capacitor C H It is connected in parallel with the reset switch RST, and its two ends are respectively connected to the negative input and output of the operational amplifier OPA.

[0045] This embodiment takes 1 to 8 bits of reconfigurable memory as an example, and focuses on 8 bits to introduce the overall working sequence. Figure 3 shown.

[0046] The overall workflow is divided into three stages: reset stage, sampling stage, and conversion stage. RST is the reset switch control signal, which is valid at a high level; SAMPLE is the sampling switch control signal, which is valid at a high level; INT is the integral switch control signal of the switched capacitor amplifier, which is valid at a high level; CLKC is the clock signal of the comparator, COMP_P and COMP_N are the comparator's in-phase output signal and inverted output signal, and S1, S2, S3, and S4 are the switch control signals output by the conversion logic circuit (valid at a high level); V REF_GDAC is the global DAC output voltage, V REF It is the reference voltage for the local analog-to-digital conversion circuit and the global DAC. Figure 2 CR<2:0> is the ADC resolution control signal. The CR<2:0> output corresponding to 8-bit resolution is "111". D<9:0> is the resolution control logic output signal. The output range of D<9:0> corresponding to 8-bit resolution is "1000000000-0000000100". It is connected to the 10-bit global DAC input to control the DAC output voltage value. L is the ADC range starting voltage; C S is the sampling capacitor, C H To hold the capacitor.

[0047] 1) Reset phase. RST = "1", SAMPLE = "0", INT = "1", CLKC = "1". D<9:0> are all reset to "0". At this time, V REF_GDAC V L , switches S1 and S2 are disconnected, switches S3 and S4 are turned on, switch RST is turned on, C S and C H The left and right plates are reset to V L At the same time, ADC outputs B7 to B0 are all reset to "0".

[0048] 2) Sampling phase. RST = "1", SAMPLE = "1", INT and CLKC remain "1". The switched capacitor amplifier is in sampling mode, the sampling switch is turned on, switches S3 and S4 are turned off, and C S The left plate samples VIN. After the sampling is completed, the RST switch is disconnected first, and then the sampling switch is disconnected to complete the sampling process. The sampling capacitor C S The charge stored on the right plate is -V IN ×C S .

[0049] 3) Conversion phase. Assumption C S and C H When the capacitance values ​​are equal and CLKC is high, the comparator is in the reset stage, COMP_P and COMP_N are reset to high, and the comparator performs comparison on the falling edge of CLKC.

[0050] ① Sampling integration: After the sampling switch is disconnected, switch S3 is turned on, and the switched capacitor amplifier is in the integration mode. Since the node V INT Conservation of charge, C S and C H After charge redistribution, C S Left plate connected to V L After the circuit is stable, C S The voltage across the terminals is close to V L , the amount of charge it stores is also close to zero, so C H The charge stored on the left plate is -V IN ×C S , at this time the output voltage of the switched capacitor amplifier is V MAC Equal to V IN .

[0051] ② Comparison: Next, the first falling edge of the INT and CLKC signals arrives. At this time, the resolution control logic output signal D<9:0> is 10'b1000000000, and the global DAC output voltage is 1 / 2V REF , the integral switch INT is disconnected, and the node V MAC Keep V IN The voltage value remains unchanged, the comparator is IN and V REF For comparison, the comparator output has two states, and the corresponding conversion logic circuit has two control modes for switches S1, S2, S3, and S4.

[0052] a) When V IN >V REF When COMP_P = "1", COMP_N = "0", COMP_P and COMP_N are ANDed to obtain the VALID signal. The rising edge of the VALID signal triggers the conversion logic circuit to output signals S1 = "1", S2 = "0" S3 = "0" S4 = "1", and the ADC outputs the most significant bit (MSB) code value as "1". Switches S1 and S4 are turned on, and switches S2 and S3 are turned off. The switched capacitor amplifier is in sampling mode, and the 1 / 2V REF Sampling to C S Left plate, C S The right plate stores a charge of -1 / 2V REF ×C S .

[0053] b) When V IN <V REF When COMP_P = "0", COMP_N = "1", similarly, the rising edge of the VALID signal triggers the conversion logic circuit to output signals S1 = "0", S2 = "1", S3 = "1" S4 = "0", the ADC output MSB code value is "0", switches S2 and S3 are turned on, switches S1 and S2 are turned off, the switched capacitor amplifier is in sampling mode, and the 1 / 2V REF Sampling to C S Right plate, C S The right plate stores a charge of 1 / 2V REF ×C S .

[0054] ③ Conversion integration: When the rising edge of CLK arrives, it triggers the conversion logic circuit to output signals S1, S2, and S4, which are all "0". Switches S1, S2, and S4 are all disconnected, and switch S3 remains in the previous state. At this time, the sampling state ends; when the rising edge of INT arrives, its rising edge triggers the conversion logic circuit to output signal S3 to "1", and the switched capacitor amplifier enters the integration mode. If the output of the first comparator is state a), due to the node V INT Conservation of charge, C S and C H After charge redistribution, the switched capacitor amplifier outputs V MAC Will become V IN +1 / 2V REF If the output of the first comparator is state b), similarly, the output voltage V MAC Will become V IN -1 / 2V REF .

[0055] This embodiment provides a method and circuit for implementing a 1-8 bit reconfigurable global reference voltage generation circuit. Figure 4 As shown. The global DAC is realized by using a segmented capacitor structure, and the voltage V L The minimum value of the ADC input dynamic range, V REF It is half of the range. The resolution control logic table is shown in Table 1.

[0056] Table 1

[0057]

[0058] When the ADC resolution is 1 bit, the reconfigurable global reference voltage generation circuit is not required, and the conversion process ends after outputting 1 bit of data.

[0059] When the ADC resolution is ≥ 2 bits, in the first conversion phase state ②, the global DAC output is 1 / 2V REF ; In the second conversion phase state ②, the global DAC output is 1 / 4V REF …and so on.

[0060] Build circuits based on CMOS 55nm process and perform simulations. Figure 5 This is a graph showing the output signal spectrum of the reconfigurable ADC provided by an embodiment of the present invention in 8-bit resolution mode. The horizontal and vertical axes represent the input signal frequency and FFT spectrum power, respectively, in MHz and dB. As can be seen from the graph, while adhering to the Nyquist sampling theorem, the noise floor of the reconfigurable ADC provided by an embodiment of the present invention in 8-bit resolution mode is at a normal level, with an effective number of bits (ENOB) reaching 7.86 bits and a spurious-free dynamic range (SFDR) of 64.3 dBc.

[0061] This embodiment utilizes a globally reusable reference voltage generation circuit for reconfigurable functionality. Analog-to-digital conversion is implemented using a switched-capacitor circuit, avoiding the area consumption associated with a large number of capacitors and improving the computational density of the integrated storage and computing chip. Furthermore, a successive approximation conversion strategy achieves high conversion speeds, meeting the demand for higher computing power in integrated storage and computing technology.

[0062] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A reconfigurable analog-to-digital converter for storage and computing, characterized in that: The reconfigurable analog-to-digital converter for storage and computing includes: a reconfigurable global reference voltage generation circuit and a local analog-to-digital conversion circuit; The reconfigurable global reference voltage generating circuit includes: a global DAC and a resolution control logic circuit; the resolution control logic circuit generates a global reference voltage according to a resolution control signal CR <m:0>and clock signal CLKC output D <k:0>, and the value output in each cycle is half of the previous cycle; the global DAC outputs the data D of the resolution control logic circuit <k:0>Converted into a corresponding voltage signal and output to all local analog-to-digital conversion circuits in the entire array as a global reference voltage V REF_GDAC ; The local analog-to-digital conversion circuit includes a switched capacitor circuit, an operational amplifier OPA, a comparator and a conversion logic circuit; The switch capacitor circuit is connected to the operational amplifier OPA for sampling the input signal and comparing it with the global reference voltage value V REF_GDAC Perform addition and subtraction operations and transfer them to the positive input terminal of the comparator; The comparator is used to compare the output value of the operational amplifier OPA with the reference voltage value V REF Compare and output the corresponding bit code value; The conversion logic circuit is used to determine the subsequent addition / subtraction operation based on the binary code value output by the comparator, generate a corresponding switch control signal, and output a quantized digital code; The switch capacitor circuit includes: a sampling switch SAMPLE, a sampling capacitor C S , first switch S1, second switch S2, third switch S3, fourth switch S4, holding capacitor C H , initialization switch INT and reset switch RST; One end of the sampling switch SAMPLE is connected to the input, and the other end is connected to the sampling capacitor C S , initialization switch INT and the negative input terminal of the operational amplifier OPA; one end of the first switching switch S1 and the second switching switch S2 is connected to the global reference voltage V REF_GDAC , and the other end is connected to the sampling capacitor C S The third switch S3 and the fourth switch S4 are connected to the positive input terminal of the operational amplifier OPA at one end, and the other end is connected to the sampling capacitor C S The holding capacitor C H It is connected in parallel with the reset switch RST, and its two ends are respectively connected to the negative input terminal and the output terminal of the operational amplifier OPA.

2. The reconfigurable analog-to-digital converter for storage and computing according to claim 1, characterized in that: The global DAC is implemented using a segmented capacitor structure.

3. The reconfigurable analog-to-digital converter for storage and computing according to claim 1, characterized in that: The storage-computing-oriented reconfigurable analog-to-digital converter is a 1-8 bit reconfigurable analog-to-digital converter.

4. The reconfigurable analog-to-digital converter for storage and computing according to claim 1, wherein: The control signal of the reset switch RST is active high.

5. The storage-computing-oriented reconfigurable analog-to-digital converter according to claim 1, characterized in that: The control signal of the sampling switch SAMPLE is active at a high level.

6. The storage-computing-oriented reconfigurable analog-to-digital converter according to claim 1, characterized in that: The control signal of the initialization switch INT is active at a high level.

7. The storage-computing-oriented reconfigurable analog-to-digital converter according to claim 1, characterized in that: The control signals of the first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 are high level valid.

8. A reconfigurable analog-to-digital conversion method for storage and computing, characterized in that: The reconfigurable analog-to-digital conversion method is implemented based on the storage-computing-oriented reconfigurable analog-to-digital converter according to any one of claims 1 to 7, comprising: The reconfigurable global reference voltage is used to generate a circuit global reference voltage; and the local analog-to-digital conversion circuit is used to implement analog-to-digital conversion and output a conversion result.

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