HART io system and data acquisition method thereof

Abstract

A HART IO system and a data acquisition method thereof, comprising: an FPGA, at least two slave FPGAs, and an MCU corresponding to each slave FPGA; the MCU is configured to receive and parse a HART data acquisition request from a master station, and send the parsed HART data acquisition request to the corresponding slave FPGA; and further configured to send the corresponding HART data read by the MCU to the master station; the slave FPGA is configured to receive the HART data acquisition request sent by the corresponding MCU, and send the HART data acquisition request to the master FPGA; receive the corresponding HART data from the master FPGA and store the HART data for reading by the corresponding MCU; and the master FPGA is configured to acquire the corresponding HART data according to the HART data acquisition request, and send the HART data to the slave FPGA which sends the HART data acquisition request. The embodiment of the present disclosure can avoid the situation that one-way HART communication fails and cannot communicate with the HART instrument, and improve the disaster tolerance of the system.

Description

Technical Field

[0001] This disclosure relates to the field of electrical control technology, and in particular to an Open Communication Protocol (HART) Input / Output (IO) system for addressable remote sensor high-speed channels and its data acquisition method. Background Technology

[0002] HART is a communication protocol introduced by Rosement Systems in 1985 for communication between field smart instruments and control room equipment. The HART IO system is used for HART communication between the DP master station and HART instruments.

[0003] In existing technologies, HART IO systems only support one HART communication channel, which is implemented by FPGA and MCU.

[0004] However, since the existing HART IO system only supports one HART communication channel, there is no backup plan after a failure, and the field will be unable to communicate with the HART instrument. Summary of the Invention

[0005] This disclosure provides a HART IO system and its data acquisition method, which can avoid the situation where communication with HART instruments is impossible after one HART communication failure, thereby improving the system's disaster recovery capability.

[0006] On one hand, this disclosure provides a HART IO system, including: a master programmable gate array (FPGA), at least two slave FPGAs, and a microcontroller unit (MCU) configured one-to-one with each slave FPGA;

[0007] The MCU is configured to receive HART data acquisition requests from the master station, parse the HART data acquisition requests, and send the parsed HART data acquisition requests to the corresponding slave FPGA; it is also configured to send the read HART data corresponding to the HART data acquisition requests to the master station.

[0008] The slave FPGA is used to receive HART data acquisition requests sent by the corresponding MCU, send the HART data acquisition requests to the master FPGA, receive and store the HART data corresponding to the HART data acquisition requests from the master FPGA, and provide it to the corresponding MCU for reading.

[0009] The main FPGA is used to acquire the corresponding HART data according to the HART data acquisition request, and send the acquired HART data to the slave FPGA that sent the HART data acquisition request.

[0010] On the other hand, this disclosure also provides a data acquisition method applied to a HART IO system, the method comprising:

[0011] The MCU receives a HART data acquisition request from the master station, parses the HART data acquisition request, and sends the parsed HART data acquisition request to the corresponding slave FPGA.

[0012] Receive HART data acquisition requests from the corresponding MCU from the FPGA, and send the HART data acquisition requests to the main FPGA;

[0013] The main FPGA acquires the corresponding data according to the data acquisition request and sends the acquired data to the slave FPGA that sent the data acquisition request.

[0014] The process involves receiving and storing the HART data corresponding to the HART data acquisition request from the main FPGA, which is then read by the corresponding MCU.

[0015] The MCU will send the HART data it reads, corresponding to the HART data acquisition request, to the master station.

[0016] Compared with related technologies, the HART IO system provided in this disclosure can provide multiple HART communication channels, thereby avoiding the situation where communication with HART instruments cannot be carried out after one HART communication channel fails, and improving the disaster recovery capability of the system.

[0017] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0019] Figure 1 This is a schematic diagram of the structure of an existing HART IO system according to an embodiment of the present disclosure;

[0020] Figure 2 This is a schematic diagram of the structure of a HART IO system according to an embodiment of the present disclosure;

[0021] Figure 3 This is a schematic diagram of the structure of an FGPA according to an embodiment of the present disclosure;

[0022] Figure 4 This is a schematic diagram of the structure of a main FGPA according to an embodiment of the present disclosure;

[0023] Figure 5 This is a schematic diagram of another main FGPA structure according to an embodiment of this disclosure;

[0024] Figure 6 This is a schematic diagram of another main FGPA structure according to an embodiment of the present disclosure;

[0025] Figure 7 This is a schematic diagram of a signal modulation and demodulation process according to an embodiment of the present disclosure;

[0026] Figure 8 This is a circuit diagram of a HART IO system according to an embodiment of the present disclosure;

[0027] Figure 9 This is a flowchart illustrating a data acquisition method according to an embodiment of the present disclosure;

[0028] Figure 10 This is a flowchart illustrating another data acquisition method according to an embodiment of the present disclosure;

[0029] Figure 11 This is a flowchart illustrating a HART self-polling process according to an embodiment of the present disclosure;

[0030] Figure 12 This is a flowchart illustrating a HART self-polling state machine according to an embodiment of the present disclosure.

[0031] Figure 13 This is a schematic diagram of an AMS polling process according to an embodiment of the present disclosure;

[0032] Figure 14 This is a flowchart illustrating an AMS polling state machine according to an embodiment of the present disclosure. Detailed Implementation

[0033] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0034] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique solution as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other solutions to form another unique solution as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0035] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0036] The structure of existing HART IO systems is as follows: Figure 1 As shown, it includes: MCU 11 and FPGA 12. MCU 11 implements HART data packet processing, including HART data packet parsing and packet assembly. FPGA 12 implements the HART interface, and its main functions are First In First Out (FIFO) and Universal Asynchronous Receiver / Transmitter (UART) data transmission and reception.

[0037] This disclosure provides a HART IO system, such as... Figure 2 As shown, it includes: a master FPGA 21, at least two slave FPGAs 22, and an MCU 23 configured one-to-one with each slave FPGA;

[0038] The MCU 23 is configured to receive HART data acquisition requests from the master station, parse the HART data acquisition requests, and send the parsed HART data acquisition requests to the corresponding slave FPGA 22; it is also configured to send the read HART data corresponding to the HART data acquisition requests to the master station.

[0039] The FPGA 22 is used to receive HART data acquisition requests sent by the corresponding MCU 23, send the HART data acquisition requests to the main FPGA, receive and store the HART data corresponding to the HART data acquisition requests from the main FPGA, and provide it to the corresponding MCU 23 for reading.

[0040] The main FPGA 21 is used to obtain the corresponding HART data according to the HART data acquisition request, and send the obtained HART data to the slave FPGA 22 that sent the HART data acquisition request.

[0041] The HART IO system provided in this disclosure can provide multiple HART communication channels, thereby avoiding the situation where communication with HART instruments is impossible after one HART communication channel fails, and improving the system's disaster recovery capability.

[0042] In one exemplary instance, this disclosure provides a structural schematic diagram of an FGPA, such as... Figure 3 As shown, the FPGA 22 includes: an MCU interface module 221, a HART interaction module 222, and a first memory 223;

[0043] The HART interaction module 222 is used to receive the HART data acquisition request from the MCU 23 through the MCU interface module 221; it is also used to encapsulate the HART data acquisition request and send the encapsulated HART data acquisition request to the main FPGA 21, receive the HART data corresponding to the HART data acquisition request from the main FPGA 21, and store the obtained HART data in the first memory 223; it is also used to modify the first HART data acquisition status information in itself from the first information indicating that no HART data exists to the second information indicating that HART data exists after obtaining the HART data;

[0044] The MCU 23 is also used to periodically poll the first HART data in the HART interaction module 222 through the corresponding MCU interface module 221 in the FPGA 22 to obtain status information. When the status information obtained by polling the first HART data in the HART interaction module 222 is changed from the first information to the second information, the MCU interface module 221 in the FPGA 22 reads the HART data in the first memory 223 through the corresponding MCU interface module 221 in the FPGA 22.

[0045] For example, the first HART data acquisition status information can be represented by the value of a register in the HART interaction module, where 0 represents the first information and 1 represents the second information.

[0046] In one exemplary instance, the MCU 23 is further configured to, after reading the HART data in the first memory 223, modify the first HART data acquisition status information from the second information to the first information through the MCU interface module 221.

[0047] For example, the first memory includes random access memory (RAM).

[0048] In one exemplary instance, the MCU parses the HART data acquisition request and sends the parsed HART data acquisition request to the corresponding slave FPGA, including:

[0049] The MCU 23 parses the HART data acquisition request, determines that the HART data acquisition request is of the periodic HART data acquisition request type, and sends the HART data acquisition request containing the periodic HART data acquisition request type information to the HART interaction module 222 through the MCU interface module 221.

[0050] For example, a periodic HART data acquisition request can specifically be an AT periodic HART data acquisition request. AT (AutoThink) is a software programming tool and software platform independently developed by Hollysys.

[0051] In one exemplary instance, the HART interaction module encapsulates the HART data acquisition request, including:

[0052] When the HART data acquisition request contains the periodic HART data acquisition request type information, the HART interaction module 222 encapsulates the periodic HART data acquisition request according to a first preset format and sends the encapsulated periodic HART data acquisition request to the main FPGA 21. The encapsulation process includes setting the request type flag information in the first preset format to information indicating the periodic HART data acquisition request type, and setting other information in the first preset format to default information.

[0053] In one exemplary instance, the MCU parses the HART data acquisition request and sends the parsed HART data acquisition request to the corresponding slave FPGA, including:

[0054] The MCU 23 parses the HART data acquisition request, determines that the HART data acquisition request is information on the type of non-periodic HART data acquisition request of the Asset Management System (AMS) and the request channel information of the non-periodic HART data acquisition request of the AMS, and sends the HART data acquisition request containing the AMS non-periodic HART data acquisition request type information and request channel information to the HART interaction module 222 through the MCU interface module 221;

[0055] The HART interaction module encapsulates the HART data acquisition request, including:

[0056] When the HART data acquisition request contains information about the AMS aperiodic HART data acquisition request type, the HART interaction module 222 retrieves encapsulation information from the first memory 223, encapsulates the AMS aperiodic data acquisition request according to a first preset format and the encapsulation information, and sends the encapsulated AMS aperiodic HART data acquisition request to the main FPGA 21. The encapsulation process includes: setting the request type flag information in the first preset format to information indicating the AMS aperiodic HART data acquisition request type, filling the request channel information into the channel information of the first preset format, and filling the encapsulation information into the corresponding information of the first preset format.

[0057] For example, the first preset format can be specifically shown in Table 1.

[0058]

[0059] Table 1

[0060] Among them, FUNCTION: non-periodic read / write function code, 0x61 is used for AT periodic HART data acquisition, and 0x62 is used for AMS non-periodic HART data acquisition.

[0061] SLOT: Non-periodic read / write slot number;

[0062] INDEX: Represents the channel number, between 1 and 8;

[0063] LEN: AMS non-periodic read / write message length, the length of data following this field;

[0064] CTRL: Keep it, just write 0;

[0065] EXT_CTRL: The number of leading 0xFF characters in a HART message;

[0066] DATA: AMS requests data, but AT itself polls and finds no data.

[0067] In one exemplary instance, this disclosure provides a schematic diagram of the structure of a main FGPA, as shown below. Figure 4 As shown, the main FPGA 21 includes: a HART control module 211, a second memory 212, and a HART self-polling module 213;

[0068] The HART control module 211 is used to receive and parse the encapsulated HART data acquisition request from the HART interaction module 222. When the parsed request type flag information is information indicating a periodic HART data acquisition request type, it obtains the channel data status information corresponding to all channels from the HART self-polling module 213, reads the HART data of the channel whose channel data status information is represented by the second information from the second memory 212, and sends it to the HART interaction module 222.

[0069] In one exemplary embodiment, this disclosure also provides a schematic diagram of the structure of a main FGPA, such as... Figure 5 As shown, the main FPGA also includes: a HART transmitting module 214 and a HART receiving module 215;

[0070] The MCU 23 is also used to send a self-polling enable request to the HART interaction module 222 through the MCU interface module 221;

[0071] The HART interaction module 222 is further configured to encapsulate the self-polling enable request according to a second preset format, and send the encapsulated self-polling enable request to the HART control module 211;

[0072] The HART control module 211 is also used to receive and parse the encapsulated self-polling enable request from the HART interaction module 222, and enable the HART self-polling module 213.

[0073] The HART self-polling module 213 is used to periodically send HART data acquisition instructions for all channels to the HART transmitting module 214 after being enabled, and to receive HART data from the HART receiving module 215; it is also used to store the acquired HART data in the second memory 212, and to set the channel data status information corresponding to the channel from which the acquired HART data comes as the second information.

[0074] The HART transmitting module 214 is used to receive HART data acquisition instructions from all channels of the HART self-polling module 213, and acquire HART data from all channels according to the data acquisition instructions;

[0075] The HART receiving module 215 is used to receive HART data from all channels and send the obtained HART data to the HART polling module 213.

[0076] For example, the second preset format is shown in Table 2.

[0077] Write command HART channel enable 0x5A 1 byte

[0078] Table 2

[0079] In one exemplary embodiment, this disclosure also provides a schematic diagram of the structure of a main FGPA, such as... Figure 6 As shown, the main FPGA also includes: an AMS polling module 216;

[0080] The HART control module 211 is further configured to send a HART data acquisition instruction containing the parsed specified channel information to the AMS polling module 216 when the parsed request type flag information is information indicating an AMS non-periodic data acquisition request type; it is also configured to periodically poll the second HART data acquisition status information in the AMS polling module 216, and when the polling shows that the second HART data acquisition status information has changed from the first information to the second information, read HART data from the second memory and send the obtained HART data to the HART interaction module 222 that sent the data acquisition request;

[0081] The AMS polling module 216 is used to send a HART data acquisition instruction for a specified channel to the HART sending module 214, and is also used to receive HART data from the HART receiving module 215 and store it in the second memory 212. It is also used to set the second HART data acquisition status information in itself to be modified from the first information to the second information.

[0082] The HART transmitting module 214 is used to receive a HART data acquisition instruction for a specified channel from the AMS polling module 216, and acquire the HART data of the specified channel.

[0083] The HART receiving module 215 is used to receive HART data and send the obtained HART data to the AMS polling module 216.

[0084] For example, the second HART data acquisition status information can be specifically represented by the value of a register in the AMS polling module.

[0085] In one exemplary instance, the HART control module 211 is further configured to, after reading the HART data in the second memory, modify the second data acquisition status identifier information in the AMS polling module 216 from the second information to the first information.

[0086] This disclosure also provides a HART IO system, such as... Figure 7 As shown, it includes: the modulation and demodulation link section (represented as HART Modem in the figure), the FPGA section (consisting of two parts, one is the master FPGA and the other is the slave FPGA), and the MCU section;

[0087] The FPGA section handles HART polling and data acquisition, while the MCU section handles data forwarding. The modulation and demodulation section is primarily handled by the AD5700 HART modem chip, enabling modulation of TTL (Transistor Transistor Logic, TTL) signals to 1.2K and 2.2K signals, and demodulation in the reverse direction. The HART physical layer uses Frequency-Shift Keying (FSK) signals at a baud rate of 1200bps. The signal modulation and demodulation process is as follows... Figure 8 As shown;

[0088] The main FPGA performs HART data polling, including AT self-polling and AMS polling. The polled data is stored in the HART dual-port RAM.

[0089] For periodic HART data requests from the AT, the slave FPGA reads the data from the corresponding port of the HART dual-port RAM in the master FPGA. After obtaining the data, it sets the enable response data flag (corresponding to the first HART data acquisition status information in the above embodiment being modified from the first information to the second information). After reading the data, the MCU clears the enable response data flag. For non-periodic HART data requests from the AMS, the slave FPGA sends a request to the master FPGA. After obtaining the HART data, the master FPGA forwards it to the slave FPGA. The slave FPGA sets the enable response data flag, and after reading the data, the MCU clears the enable response data flag.

[0090] The MCU completes the forwarding of HART data, receives and parses the data acquisition request from the DP master station, determines whether it is an AT periodic HART data request or an AMS non-periodic HART data request, and sends it to the different data interfaces of the FPGA; after waiting for the FPGA to set the enable response data flag, the MCU reads the data from the HART dual-port RAM and forwards it to the DP dual-port RAM of the FPGA.

[0091] For example, PROFIBUS-DP is currently the most widely used bus system globally. PROFIBUS-DP is a bus system consisting of master and slave stations, with the master station's functions implemented by the master controller in the control system. While performing its own functions, the master station communicates with each slave station in the control system through cyclic and acyclic messages.

[0092] This disclosure also provides a circuit for a HART IO system, such as... Figure 9 As shown, the HART IO system includes three slave FPGAs.

[0093] The HART interaction module (HART_INTERACTIVE) enables HART data interaction between the slave FPGA and the master FPGA.

[0094] The MCU interface module (MCU_HART_INTERFACE) allows the MCU to read and write data from the HART module.

[0095] The HART control module (HART_CTRL) interacts with three FPGA slaves via HART data to achieve HART communication control.

[0096] The HART self-polling module (HART_SELF_COM) implements the HART self-polling transmit and receive control function;

[0097] The AMS polling module (HART_AMS_COM) implements the AMS polling send / receive control function;

[0098] The HART transmit module (HART_SEND) implements the sending of HART data acquisition commands.

[0099] The HART receiver module (HART_RECV) is used to receive HART data.

[0100] When the MCU reads the AT self-polling HART response data, the three slave FPGAs send read commands, and the master FPGA sends the response data of the corresponding channel in the dual-port RAM to the three slave FPGAs sequentially via UART; when the MCU reads the AMS polling HART response data, the FPGA sends a read command, the master FPGA starts AMS polling, and after the AMS polling ends, it sends the HART response data to the corresponding slave FPGA (the controller voting ensures that only one slave FPGA sends an AMS non-periodic HART data acquisition request at a time).

[0101] This disclosure also provides a data acquisition method, applicable to the HARTIO system described in any of the above embodiments, such as... Figure 10 As shown, it includes:

[0102] Step 301: The MCU receives a HART data acquisition request from the master station, parses the HART data acquisition request, and sends the parsed HART data acquisition request to the corresponding slave FPGA.

[0103] Step 302: Receive the HART data acquisition request from the corresponding MCU from the FPGA, and send the HART data acquisition request to the main FPGA;

[0104] Step 303: The main FPGA obtains the corresponding data according to the data acquisition request, and sends the obtained data to the slave FPGA that sent the data acquisition request;

[0105] Step 304: Receive and store the HART data corresponding to the HART data acquisition request from the main FPGA, and then store it for the corresponding MCU to read.

[0106] Step 305: The MCU sends the HART data read corresponding to the HART data acquisition request to the master station.

[0107] The data acquisition method provided in this disclosure can acquire data through multiple HART communications, thereby avoiding the situation where HART instrument data cannot be acquired after one HART communication fails, and improving the success rate of HART data acquisition.

[0108] In one exemplary instance, the FPGA includes: an MCU interface module, a HART interaction module, and a first memory.

[0109] In one exemplary instance, the data acquisition method provided in this disclosure further includes:

[0110] First, the HART interaction module receives the HART data acquisition request from the MCU through the MCU interface module, encapsulates the HART data acquisition request, and sends the encapsulated HART data acquisition request to the main FPGA.

[0111] Secondly, the HART interaction module receives HART data from the main FPGA corresponding to the HART data acquisition request, stores the acquired HART data in the first memory, and after acquiring the HART data, modifies its own first HART data acquisition status information from the first information indicating that no HART data exists to the second information indicating that HART data exists.

[0112] Finally, the MCU periodically polls the first HART data in the HART interaction module through the corresponding MCU interface module in the FPGA to obtain status information. When the status information obtained from the first HART data in the HART interaction module is changed from the first information to the second information, the MCU reads the HART data in the first memory through the corresponding MCU interface module in the FPGA.

[0113] In one exemplary instance, after the MCU reads HART data from the first memory via a corresponding MCU interface module in the FPGA, the method further includes:

[0114] After the MCU finishes reading the HART data from the first memory, it modifies the first HART data acquisition status information from the second information to the first information through the MCU interface module.

[0115] In one exemplary instance, the MCU parses the HART data acquisition request and sends the parsed HART data acquisition request to the corresponding slave FPGA, including:

[0116] The MCU parses the HART data acquisition request, determines that the HART data acquisition request is of the periodic HART data acquisition request type, and sends the HART data acquisition request containing the periodic HART data acquisition request type information to the HART interaction module through the MCU interface module.

[0117] In one exemplary instance, the HART interaction module encapsulates the HART data acquisition request, including:

[0118] When the HART data acquisition request contains the periodic HART data acquisition request type information, the HART interaction module encapsulates the periodic HART data acquisition request according to a first preset format and sends the encapsulated periodic HART data acquisition request to the main FPGA. The encapsulation process includes setting the request type flag information in the first preset format to information indicating the periodic HART data acquisition request type, and setting other information in the first preset format to default information.

[0119] In one exemplary instance, the MCU parses the HART data acquisition request and sends the parsed HART data acquisition request to the corresponding slave FPGA, including:

[0120] The MCU parses the HART data acquisition request, determines that the HART data acquisition request is of type AMS aperiodic HART data acquisition request and the request channel information of the AMS aperiodic HART data acquisition request, and sends the HART data acquisition request containing the AMS aperiodic HART data acquisition request type information and request channel information to the HART interaction module through the MCU interface module.

[0121] In one exemplary instance, the HART interaction module encapsulates the HART data acquisition request, including:

[0122] When the HART data acquisition request contains information about the AMS aperiodic HART data acquisition request type, the HART interaction module retrieves encapsulation information from the first memory, encapsulates the AMS aperiodic data acquisition request according to a first preset format and the encapsulation information, and sends the encapsulated AMS aperiodic HART data acquisition request to the main FPGA. The encapsulation process includes: setting the request type flag information in the first preset format to indicate the AMS aperiodic HART data acquisition request type; filling the request channel information into the channel information of the first preset format; and filling the encapsulation information into the corresponding information of the first preset format.

[0123] In one exemplary instance, the main FPGA includes: a HART control module, a second memory, and a HART self-polling module.

[0124] In one exemplary instance, the master FPGA acquires corresponding data according to the data acquisition request and sends the acquired data to the slave FPGA that sent the data acquisition request, including:

[0125] The HART control module receives and parses the encapsulated HART data acquisition request from the HART interaction module. When the parsed request type flag information indicates a periodic HART data acquisition request type, it obtains the channel data status information corresponding to all channels from the HART self-polling module, reads the HART data of the channel whose channel data status information is represented by the second information from the second memory, and sends it to the HART interaction module.

[0126] In one exemplary instance, the main FPGA further includes a HART transmitting module and a HART receiving module.

[0127] In one exemplary instance, the data acquisition method provided in this disclosure further includes:

[0128] First, the MCU sends a self-polling enable request to the HART interaction module through the MCU interface module;

[0129] Secondly, the HART interaction module encapsulates the self-polling enable request according to the second preset format and sends the encapsulated self-polling enable request to the HART control module;

[0130] Next, the HART control module receives and parses the encapsulated self-polling enable request from the HART interaction module, and enables the HART self-polling module.

[0131] Next, after being enabled, the HART self-polling module periodically sends HART data acquisition instructions for all channels to the HART transmitting module;

[0132] Next, the HART transmitting module receives HART data acquisition instructions from all channels of the HART self-polling module, and acquires HART data from all channels according to the data acquisition instructions;

[0133] Next, the HART receiving module receives HART data from all channels and sends the obtained HART data to the HART self-polling module;

[0134] Finally, the HART self-polling module receives HART data from the HART receiving module; it is also used to store the obtained HART data in the second memory, and set the channel data status information corresponding to the channel from which the obtained HART data comes as the second information.

[0135] In one exemplary instance, the main FPGA further includes an AMS polling module.

[0136] In one exemplary instance, the master FPGA acquires corresponding data according to the data acquisition request and sends the acquired data to the slave FPGA that sent the data acquisition request, including:

[0137] When the HART control module parses the request type flag information and finds that it indicates an AMS non-periodic data acquisition request type, it sends a HART data acquisition instruction containing the parsed specified channel information to the AMS polling module.

[0138] The AMS polling module sends a HART data acquisition command for the specified channel information to the HART sending module.

[0139] The HART transmitting module receives a HART data acquisition instruction for a specified channel from the AMS polling module, and acquires the HART data for the specified channel.

[0140] The HART receiving module receives HART data and sends the obtained HART data to the AMS polling module.

[0141] The AMS polling module receives HART data from the HART receiving module and stores it in the second memory, and sets the second HART data acquisition status information in itself to be modified from the first information to the second information;

[0142] The AMS polling module periodically polls the second HART data acquisition status information in the AMS polling module. When the polling shows that the second HART data acquisition status information has changed from the first information to the second information, it reads the HART data from the second memory and sends the obtained HART data to the HART interaction module that sent the data acquisition request.

[0143] In one exemplary instance, after the HART control module reads HART data from the second memory, it further includes:

[0144] After reading the HART data in the second memory, the HART control module modifies the second data acquisition status identifier information in the AMS polling module from the second information to the first information.

[0145] This disclosure also provides a data acquisition method, such as... Figure 11 As shown, it includes:

[0146] Step 401: The DP master station initiates a data retrieval request (DP data);

[0147] Step 402: Parse the DU data from the DP data from the FPGA and send it to the MCU;

[0148] Step 403: The MCU parses the DU data and determines the request type. If it is a periodic HART data acquisition request, proceed to step 404. If it is an AMS non-periodic HART data acquisition request, proceed to step 406.

[0149] Step 404: Directly encapsulate the data acquisition request from the FPGA and send it to the main FPGA;

[0150] Step 405: The master FPGA obtains the corresponding data and sends it to the slave FPGA, then executes step 412;

[0151] Step 406: Read the package information and package data acquisition request from the FPGA's own dual-port RAM and send it to the main FPGA;

[0152] Step 407: The main FPGA initiates AMS polling;

[0153] Step 408: Determine if the polling was successful. If successful, proceed to step 410. If unsuccessful, proceed to step 409.

[0154] Step 409: Determine if the number of polling attempts is greater than the preset number. If it is greater than the preset number, proceed to step 410. If it is not greater than the preset number, return to step 407.

[0155] Step 410: The main FGPA writes polling data or error flags into its own dual-port RAM;

[0156] Step 411: The master FPGA sends the corresponding data to the slave FPGA;

[0157] Step 412: Obtain the data post-set enable response data flag bit from the FPGA;

[0158] Step 414: The MCU reads data from the dual-port RAM of the FPGA and stores it in the DP dual-port RAM of the FPGA;

[0159] Step 414: Forward the data from the DP dual-port RAM from the FPGA to the DP master station.

[0160] When the DP slave enters the data exchange state, HART communication begins. The HART self-polling flowchart is as follows: Figure 12 As shown.

[0161] 1) The IO HART system itself sequentially sends command #0 (used to identify field devices) and command #3 (used to read measurement variables in different forms) to the HART devices on each channel (CH1~CH16, HART enabled). The IO HART system first sends command #0 to the current channel. After receiving a response, it continues to send command #3. If no response is received, it waits for 1.5 seconds before sending command #3 again. Sending command #3 is similar; if no response is received, it waits for 1.5 seconds before sending command #0 to the next channel (HART enabled), and this cycle continues.

[0162] 2) The DP master card will sequentially send the #3 read request command to each channel of the IO HART system: When the IO HART system polls, if it receives a response from the device, it will place the response data in the corresponding HART data buffer and set the data ready flag. When the DP master card polls this channel, it will respond with the buffer data. If the device does not respond under the IO HART system, the IO HART system will only send a short response to the DP master station.

[0163] A flowchart of the HART self-polling state machine is shown below. Figure 13 As shown,

[0164] IDLE: Initializes the state and the timer.

[0165] CH_SEL: Channel selection state. When entering its own polling mode from AMS polling, it starts after 1 minute; during normal looping, it polls once every 1.5 seconds, with HART-enabled channels polling commands 0# and 3# sequentially; in tooling mode, the host computer configures the HART polling channels. While executing AMS polling, it maintains the current state; when the delay arrives, it jumps to the CH_VALID state.

[0166] CH_VALID: Channel validity status. Determines whether the currently selected HART channel is enabled. If HART is enabled or in tooling mode, jumps to SW_CTRL state; otherwise, jumps to CH_SEL to select the next channel.

[0167] SW_CTRL: Channel analog switch control status, controls the switching of the channel switch.

[0168] SEND_WAIT: Sending wait state, delayed for 10ms, then jumps to SEND_DATA state.

[0169] SEND_DATA: Data transmission status. Send command 0# or 3# according to the HART command to clear HART_RX_FIFO and jump to the SEND_COMPLETE state.

[0170] SEND_COMPLETE: The sending is complete. Waiting for the HART request data to be sent to complete before transitioning to the RECV_DATA state.

[0171] RECV_DATA: Data reception status. After sending is completed, HART data reception begins, and a reception timeout (1s) check is performed. When reception is completed normally, it jumps to the RES_OK_PACKET state. If reception times out, it jumps to the CH_SEL state and polls for the next channel or command code. If the current polling channel times out receiving command code #3 twice in a row, it jumps to the RES_ERR_PACKET state.

[0172] RES_OK_PACKET: Normal response packet status. Set the normal response packet flag and jump to the COMPLETE_RES status.

[0173] RES_ERR_PACKET: Response timeout packet state. Setting the response timeout packet flag will jump to the COMPLETE_RES state.

[0174] COMPLETE_RES: Data reception completion status. When the response data packet is assembled, it jumps to the CH_SEL status.

[0175] A flowchart of AMS polling is shown below. Figure 13 As shown, when the DP master card and the IO HART system are polling for HART data, if the AMS sends a write request to the DP master, the DP master will forward the write request to the IO HART. The DP master will then enter a polling state, waiting for the IO HART to respond to the write request. Upon receiving this command, the IO HART immediately forwards it to the device, resets the timeout timer, and enters a timeout judgment branch. Each timeout is 1.5 seconds; if the timeout judgment is performed twice (3 seconds), the response timeout will occur. If the device responds within this time, the actual device data is reported.

[0176] For example, the master station and the slave station communicate in a question-and-answer (with polling) manner. The master station sends a HART request packet. If the slave station has the data ready, it replies with response data. If the data is not ready, it replies with a short response (0x5E). When the master station receives the short response, it will continuously send polling messages and wait for the slave station to reply with the correct response data.

[0177] A flowchart of the AMS polling state machine is shown below. Figure 14 As shown.

[0178] IDLE: Initialization state, initializes the timer, and jumps to the SEND_JUDGE state when the HART channel is currently polled for enable; otherwise, it jumps to the COMPLETE_RES state and acknowledges an error packet.

[0179] SEND_JUDGE: Sends the status check, waits for the HART itself to finish polling, and then jumps to the SW_CTRL state;

[0180] SW_CTRL: Channel analog switch control status, sends the channel switch control register;

[0181] SEND_WAIT: Send waiting state, delay 10ms, then jumps to SEND_DATA state;

[0182] SEND_DATA: Send data status, sends HART data to the instrument, clears HART_RX_FIFO, and jumps to the SEND_COMPLETE status;

[0183] SEND_COMPLETE: Sending completed. Waiting for the HART request data to be sent to complete before transitioning to the RECV_DATA state.

[0184] RECV_DATA: Data reception status. After sending is completed, HART data reception begins, and a reception timeout check is performed. When normal reception is completed, a normal acknowledgment data packet is assembled, and the system jumps to the COMPLETE_RES state. When reception times out, the system jumps to the SEND_DATA state and retransmits the data. When reception times out twice consecutively, an error acknowledgment data packet is assembled, and the system jumps to the COMPLETE_RES state.

[0185] COMPLETE_RES: Data reception completion status, sets the AMS polling completion flag.

[0186] It should be understood that a processor can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor, etc.

[0187] Memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, memory may also store information about the device type.

[0188] In implementation, the processing performed by the terminal device can be accomplished through integrated logic circuits in the processor's hardware or through software instructions. That is, the steps of the method disclosed in this embodiment can be executed by a hardware processor, or by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other storage media. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0189] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0190] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0191] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

Claims

1. An open communication protocol input / output HART IO system for addressable remote sensor high-speed channels, characterized in that, Includes: a master programmable array logic FPGA, at least two slave FPGAs, and a microcontroller unit (MCU) corresponding to each slave FPGA; The MCU is configured to receive HART data acquisition requests from the master station, parse the HART data acquisition requests, and send the parsed HART data acquisition requests to the corresponding slave FPGA; it is also configured to send the read HART data corresponding to the HART data acquisition requests to the master station. The slave FPGA is used to receive HART data acquisition requests sent by the corresponding MCU, send the HART data acquisition requests to the master FPGA, receive and store the HART data corresponding to the HART data acquisition requests from the master FPGA, and provide it to the corresponding MCU for reading. The main FPGA is used to obtain the corresponding HART data according to the HART data acquisition request, and send the obtained HART data to the slave FPGA that sent the HART data acquisition request. The FPGA includes: an MCU interface module, a HART interaction module, and a first memory; The HART interaction module is used to receive the HART data acquisition request from the MCU through the MCU interface module, encapsulate the HART data acquisition request, and send the encapsulated HART data acquisition request to the main FPGA; receive HART data corresponding to the HART data acquisition request from the main FPGA; and store the obtained HART data in the first memory; it is also used to modify its own first HART data acquisition status information from a first information indicating that no HART data exists to a second information indicating that HART data exists after obtaining the HART data. The MCU is also used to periodically poll the first HART data in the HART interaction module through the corresponding MCU interface module in the FPGA to obtain status information. When the polled status information of the first HART data in the HART interaction module is changed from the first information to the second information, the MCU reads the HART data in the first memory through the corresponding MCU interface module in the FPGA.

2. The system according to claim 1, characterized in that, The MCU is also used to modify the first HART data acquisition status information from the second information to the first information through the MCU interface module after reading the HART data in the first memory.

3. The system according to claim 2, characterized in that, The MCU parses the HART data acquisition request and sends the parsed HART data acquisition request to the corresponding slave FPGA, including: The MCU parses the HART data acquisition request, determines that the HART data acquisition request is of the periodic HART data acquisition request type, and sends the HART data acquisition request containing the periodic HART data acquisition request type information to the HART interaction module through the MCU interface module. The HART interaction module encapsulates the HART data acquisition request, including: When the HART data acquisition request contains the periodic HART data acquisition request type information, the HART interaction module encapsulates the periodic HART data acquisition request according to a first preset format and sends the encapsulated periodic HART data acquisition request to the main FPGA. The encapsulation process includes setting the request type flag information in the first preset format to information indicating the periodic HART data acquisition request type, and setting other information in the first preset format to default information.

4. The system according to claim 1, characterized in that, The MCU parses the HART data acquisition request and sends the parsed HART data acquisition request to the corresponding slave FPGA, including: The MCU parses the HART data acquisition request, determines that the HART data acquisition request is of type AMS non-periodic HART data acquisition request and the request channel information of the AMS non-periodic HART data acquisition request, and sends the HART data acquisition request containing the AMS non-periodic HART data acquisition request type information and request channel information to the HART interaction module through the MCU interface module. The HART interaction module encapsulates the HART data acquisition request, including: When the HART data acquisition request contains information about the AMS aperiodic HART data acquisition request type, the HART interaction module retrieves encapsulation information from the first memory, encapsulates the AMS aperiodic data acquisition request according to a first preset format and the encapsulation information, and sends the encapsulated AMS aperiodic HART data acquisition request to the main FPGA. The encapsulation process includes: setting the request type flag information in the first preset format to indicate the AMS aperiodic HART data acquisition request type; filling the request channel information into the channel information of the first preset format; and filling the encapsulation information into the corresponding information of the first preset format.

5. The system according to claim 1, characterized in that, The main FPGA includes: a HART control module, a second memory, and a HART self-polling module; The HART control module is used to receive and parse the encapsulated HART data acquisition request from the HART interaction module. When the parsed request type flag information is information indicating a periodic HART data acquisition request type, the module obtains the channel data status information corresponding to all channels from the HART self-polling module, reads the HART data of the channel whose channel data status information is represented by the second information from the second memory, and sends it to the HART interaction module.

6. The system according to claim 5, characterized in that, The main FPGA also includes: a HART transmitting module and a HART receiving module; The MCU is also used to send a self-polling enable request to the HART interaction module through the MCU interface module; The HART interaction module is further configured to encapsulate the self-polling enable request according to a second preset format, and send the encapsulated self-polling enable request to the HART control module. The HART control module is also used to receive and parse the encapsulated self-polling enable request from the HART interaction module, and enable the HART self-polling module. The HART self-polling module is used to periodically send HART data acquisition instructions for all channels to the HART transmitting module after being enabled, and to receive HART data from the HART receiving module; it is also used to store the acquired HART data in the second memory, and to set the channel data status information corresponding to the channel from which the acquired HART data comes as the second information. The HART transmitting module is used to receive HART data acquisition instructions from all channels of the HART self-polling module, and acquire HART data from all channels according to the data acquisition instructions; The HART receiving module is used to receive HART data from all channels and send the obtained HART data to the HART self-polling module.

7. The system according to claim 6, characterized in that, The main FPGA also includes: an AMS polling module; The HART control module is further configured to send a HART data acquisition instruction containing the parsed specified channel information to the AMS polling module when the parsed request type flag information indicates an AMS non-periodic data acquisition request type; it is also configured to periodically poll the second HART data acquisition status information in the AMS polling module, and when the polling shows that the second HART data acquisition status information has changed from the first information to the second information, read HART data from the second memory and send the obtained HART data to the HART interaction module that sent the data acquisition request; The AMS polling module is used to send a HART data acquisition instruction for a specified channel to the HART sending module, receive HART data from the HART receiving module and store it in the second memory, and set the second HART data acquisition status information in itself to be modified from the first information to the second information; The HART transmission module is used to receive a HART data acquisition instruction for a specified channel from the AMS polling module, and to acquire the HART data for the specified channel. The HART receiving module is used to receive HART data and send the obtained HART data to the AMS polling module.

8. The system according to claim 7, characterized in that, The HART control module is also used to modify the second data acquisition status identifier information in the AMS polling module from the second information to the first information after reading the HART data in the second memory.

9. A data acquisition method, characterized in that, Applied to the HART IO system according to any one of claims 1-8, comprising: The MCU receives a HART data acquisition request from the master station, parses the HART data acquisition request, and sends the parsed HART data acquisition request to the corresponding slave FPGA. Receive HART data acquisition requests from the corresponding MCU from the FPGA, and send the HART data acquisition requests to the main FPGA; The main FPGA acquires the corresponding data according to the data acquisition request and sends the acquired data to the slave FPGA that sent the data acquisition request. The process involves receiving and storing the HART data corresponding to the HART data acquisition request from the main FPGA, which is then read by the corresponding MCU. The MCU will send the HART data corresponding to the HART data acquisition request to the master station; The FPGA includes: an MCU interface module, a HART interaction module, and a first memory; the method further includes: The HART interaction module receives the HART data acquisition request from the MCU through the MCU interface module, encapsulates the HART data acquisition request, and sends the encapsulated HART data acquisition request to the main FPGA; The HART interaction module receives HART data from the main FPGA corresponding to the HART data acquisition request, stores the acquired HART data in the first memory, and after acquiring the HART data, modifies its own first HART data acquisition status information from the first information indicating that no HART data exists to the second information indicating that HART data exists. The MCU periodically polls the first HART data in the HART interaction module through the corresponding MCU interface module in the FPGA to obtain status information. When the polled status information of the first HART data in the HART interaction module is changed from the first information to the second information, the MCU reads the HART data in the first memory through the corresponding MCU interface module in the FPGA.

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