Multifunctional image sensor circuit

Abstract

A multi-function image sensor circuit is involved. A photodiode array circuit includes a plurality of photodiode circuits, a staging circuit system, and a plurality of output circuits. Each of the plurality of photodiode circuits is coupled to receive a different one of the plurality of transfer control signals as an adjacent photodiode circuit adjacent in a first direction. The staging circuit system is coupled to electrically connect the plurality of photodiode circuits into a group of photodiode circuit sense nodes in response to a staging control signal. Each of the plurality of output circuits is coupled to one of the group of photodiode circuit sense nodes. Each of the plurality of output circuits is coupled to receive the output charge from the photodiode circuits in the one of the group of photodiode circuit sense nodes and to output an output signal to a bit line in response to the output charge and a row select signal.

Description

Multifunctional image sensor circuit

[0001] Information related to divisional application

[0002] This application is a divisional application, the parent application of which is the invention patent application filed on August 26, 2020, with application number 202010869105.6 and invention title "Multifunctional Image Sensor Circuit". Technical Field

[0003] This invention generally relates to image sensor circuits, and more specifically to image sensor circuits having various image capture modes. Background Technology

[0004] Image sensors are used in a variety of devices, including cameras, sensors, and consumer electronics. As image sensors have become more advanced, the circuitry within them has become increasingly complex. Summary of the Invention

[0005] On one hand, this application relates to a photodiode array circuit comprising: a plurality of photodiode circuits arranged in a grid, wherein each of the photodiode circuits is coupled to receive one of a plurality of transfer control signals and outputs an output charge to a sensing node of the photodiode circuit in response to the transfer control signal, wherein each of the plurality of photodiode circuits is coupled to receive a different one of the plurality of transfer control signals as adjacent photodiode circuits in a first direction, wherein a first of the plurality of photodiode circuits and a second of the plurality of photodiode circuits adjacent to the first of the plurality of photodiode circuits in a second direction perpendicular to the first direction are coupled to receive a first portion of the plurality of transfer control signals, wherein a third of the plurality of photodiode circuits is in The first direction is adjacent to the first of the plurality of photodiodes, wherein the third and fourth photodiode circuits adjacent to the third photodiode circuit in the direction opposite to the second direction are coupled to receive the second portion of the plurality of transfer control signals; a hierarchical circuit system is coupled to selectively electrically connect the sensing nodes of the plurality of photodiode circuits into a photodiode circuit sensing node group in response to the hierarchical control signals; and a plurality of output circuits, wherein each of the plurality of output circuits is coupled to one of the photodiode circuit sensing node groups, wherein each of the plurality of output circuits is coupled to receive the output charge from the photodiode circuit in the one of the photodiode circuit sensing node groups and outputs an output signal to a bit line in response to the output charge and a row selection signal.

[0006] On the other hand, this application relates to a photodiode array circuit comprising: a plurality of photodiode circuits, each of the plurality of photodiode circuits being coupled to selectively collect output charge from the plurality of photodiodes to a sensing node in the photodiode circuit in response to a transfer control signal; a hierarchical circuit system being coupled to electrically connect the sensing nodes of the plurality of photodiode circuits into a photodiode circuit sensing node group in response to a hierarchical control signal; a plurality of output circuits, each coupled to two of the plurality of photodiode circuits and two bit lines, wherein the plurality of output circuits are coupled to receive the output charge from the two of the plurality of photodiode circuits, wherein the plurality of output circuits are coupled to output an output signal to one of the two bit lines in response to a row selection signal, the output charge, and the photodiode circuit sensing node group; and a control circuit being coupled to provide the transfer control signal, the row selection signal, and the hierarchical control signal.

[0007] On the other hand, this application relates to a photodiode array circuit comprising: a plurality of photodiode circuits, each of the plurality of photodiode circuits being coupled to selectively collect output charge from at least one photodiode at a sensing node of the photodiode circuit; a plurality of output circuits, each coupled to two of the plurality of photodiode circuits, wherein the plurality of output circuits are coupled to receive the output charge from the two of the plurality of photodiode circuits, wherein the plurality of output circuits are coupled to output an output signal; and a hierarchical circuit system that electrically connects the sensing nodes of the plurality of photodiode circuits into a photodiode circuit sensing node group in response to a hierarchical control signal, wherein, in response to the hierarchical control signal, the number of photodiode circuit sensing nodes included in the photodiode circuit sensing node group is any one of one, two, four, or six photodiode circuits, wherein different portions of the hierarchical control signal are transmitted on each of four hierarchical control lines, wherein the hierarchical circuit system comprises a plurality of hierarchical connection circuits, wherein each of the plurality of hierarchical connection circuits is connected to two of the plurality of photodiode circuits adjacent to each other in a first direction, wherein each of the hierarchical connection circuits is coupled to only one of the four hierarchical control lines. Attached Figure Description

[0008] The invention is described in a non-limiting and non-exhaustive manner with reference to the following figures, wherein similar reference numerals refer to similar parts throughout the various views unless otherwise specified.

[0009] Figures 1A to C illustrate an example image sensor circuit according to the teachings of the present invention.

[0010] Figure 2 illustrates an example of an apparatus incorporating an image sensor circuit according to the teachings of the present invention.

[0011] Figure 3 illustrates an example connection of a photodiode circuit according to the teachings of the present invention.

[0012] Corresponding reference characters throughout the various views of the accompanying drawings indicate corresponding components. Those skilled in the art will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate easier observation of these various embodiments of the invention. Detailed Implementation

[0013] This document discloses examples of image sensor circuits and apparatuses and methods for utilizing image sensor circuits. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or in conjunction with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid confusion.

[0014] Throughout this specification, the reference to "an example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in an example" or "in an embodiment" throughout this specification does not necessarily refer to the same example. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples in any suitable manner.

[0015] Throughout this specification, several technical terms are used. These terms should have the general meaning of their respective fields, unless explicitly defined herein or otherwise clearly implied in the context of their use. It should be noted that component names and symbols may be used interchangeably throughout this document (e.g., Si and silicon); however, both have the same meaning.

[0016] Image sensors sometimes include circuitry that combines inputs from photodiodes in different combinations depending on the capture mode. This ability to combine inputs from photodiodes in different combinations comes at the cost of greater complexity in the circuitry and a larger number of control signal lines.

[0017] The exemplary image sensor circuit disclosed in this paper has an architecture that allows for greater versatility than other image sensor circuits while incorporating fewer wires. This architecture allows for the addition of photodiode outputs in groups, as well as the addition of capacitors.

[0018] Figures 1A and 1B illustrate an example image sensor circuit according to the teachings of the present invention. The image sensor circuit includes photodiodes 110 to 113, transfer transistors 120 to 123, amplifying transistors 141 and 142, row selection transistors 143 and 144, hierarchical transistors 133 and 134, reset transistors 131 and 132, a reset line 151, a hierarchical control line 153, a select line 155, a transfer line 157, and a bit line 159. Each set of hierarchical control lines 153 can be grouped with a set of select lines 155 and a set of transfer lines 157. The transfer transistors 120 to 123 can be organized into four groups of four transfer transistors having a zigzag pattern 100.

[0019] The reset line 151, the grade control line 153, the select line 155, the transfer line 157, and the bit line 159 can all be wires made of conductors such as aluminum or another metal.

[0020] Each of the transfer transistors 120 to 123 can be connected via sensing node 125 as a switch between the gate of a corresponding one of the photodiodes 110 to 113 and the gate of a corresponding one of the amplifying transistors 141, 142. The photodiodes 110 to 113 and the transfer transistors 120 to 123 can be grouped into a group of four. Each first transfer transistor 120 has its gate connected to the corresponding gate of the second transfer transistor 121 and one of the transfer lines 157. Similarly, each of the third transfer transistors 122 has its gate connected to the corresponding gate of the fourth transfer transistor 123 and one of the transfer lines 157. Therefore, the transfer transistors 120 to 123 can be turned on or off based on a transfer control signal transmitted via the transfer lines 157. The first and second transfer transistors 120 and 121 can be connected to transfer lines 157 in a different group than the third and fourth transfer transistors 122 and 123. The gate of the second transfer transistor 121 can be coupled to the corresponding gate of the first transfer transistor 120 adjacent to the second transfer transistor 121 in the vertical direction. Similarly, the gate of the fourth transfer transistor 123 may be coupled to the corresponding gate of the third transfer transistor 122, which is adjacent to the fourth transfer transistor 123 in the opposite direction.

[0021] The transfer lines 157 can be organized into groups of four lines. Each of the transfer transistors 120 to 123 in the group of transfer transistors 120 to 123 has its gate connected to a different one of the four transfer lines 157 in the group of transfer lines 157. Accordingly, the transfer transistors can operate as switches based on a transfer control signal transmitted through the transfer lines 157. Each group of transfer lines 157 can receive a portion of the transfer control signal. Furthermore, each transfer line can receive a smaller portion of the transfer control signal. Therefore, each transfer transistor 120 to 123 can be controlled by a portion of the transfer control signal.

[0022] Each photodiode 110 to 113 can represent a different color set. For example, the first photodiode 110 can be a red photodiode, the second photodiode 111 can be green, the third photodiode 112 can also be green, and the fourth photodiode 113 can be blue. Each transfer transistor 120 to 123 can collect output charge from the photodiode of the different color at the sensing node 125. For example, the first transfer transistor 120 can be used to collect output charge from the red photodiode, the second transfer transistor 121 can be used to collect from the green photodiode, the third transfer transistor 122 can also be used to collect from the green photodiode, and the fourth transfer transistor 123 can be used to collect from the blue photodiode. Each transfer transistor 120 to 123 collects charge from the corresponding photodiode 110 to 113 connected to the source of the transfer transistor. The charge collected from the photodiodes 110 to 113 can be collected at the sensing node 125 between the drain of the transfer transistors 120 to 123 and the gate of the amplifying transistors 141, 142.

[0023] In a standard Bayer filter, a red, a blue, and two green filters are grouped together in a square. In the depicted example, a pattern of a red and a blue group of two green photodiodes is grouped together, but arranged in a zigzag pattern 100, wherein the first red diode 110, the second green photodiode 111, and the first and second transfer transistors 120, 121 are not connected to the same set of transfer lines 157 as the third green photodiode 112, the fourth blue photodiode 113, and the third and fourth transfer transistors 122, 123. This allows the transfer transistors 120 to 123 to be arranged in a zigzag pattern 100 instead of a square, as illustrated in Figure 1 in the teaching example according to the invention. This zigzag arrangement allows for greater versatility while reducing the number of required transfer lines 157. The group of transfer transistors 120 to 123 and the corresponding photodiodes 110 to 113 can also be referred to as a photodiode circuit.

[0024] The groups of transfer transistors 120 to 123 can be arranged in a grid such that, in both the vertical and horizontal directions (the circuit can be oriented in any direction relative to the illustration in FIG1A), the groups of transfer transistors 120 to 123 alternate between two different groups of transfer transistors 120 to 123.

[0025] As illustrated, in the first column, groups of transfer transistors 120 to 123 may alternate between a group of first transfer transistors 120 and a group of second transfer transistors 121. In the second column, groups of transfer transistors 120 to 123 may alternate between a group of third transfer transistors 122 and a group of fourth transfer transistors 123. Similarly, in the first row, groups of transfer transistors 120 to 123 may alternate between a group of first transfer transistors 120 and a group of third transfer transistors 122. In the second row, groups of transfer transistors 120 to 123 may alternate between a group of second transfer transistors 121 and a group of fourth transfer transistors 123. The image sensor circuit may alternate between the first and second rows vertically and between the first and second columns horizontally. Although three rows and eight columns are depicted in Figure 1A, the image sensor circuit can be of any size.

[0026] As stated above, each of amplifying transistors 141 and 142 can be connected to a sensing node 125 of a set of transfer transistors 120 to 123. The first amplifying transistor 141 can be connected to a sensing node 125 of either a set of first transfer transistors 120 or a set of fourth transfer transistors 123. The second amplifying transistor 142 can be connected to a sensing node 125 of either a set of second transfer transistors 121 or a set of third transfer transistors 122. Amplifying transistors 141 and 142 can be connected to a pair of sensing nodes 125 of a set of transfer transistors 120 to 123 in the same column. The drains of amplifying transistors 141 and 142 can be connected to a voltage rail (not shown) or other voltage source. The sources of amplifying transistors 141 and 142 can be connected to the drains of row select transistors 143 and 144, respectively. The sources of row select transistors 143 and 144 can be connected to the corresponding bit lines 159. Row selection transistors 143 and 144 can be paired with the gate of the first row selection transistor 143, which is connected to either the gate of the second row selection transistor 144 or the select line. Each of the row selection transistors 143 and 144 in the pair can be connected to a different bit line. Therefore, the row selection signal transmitted via select line 155 can control which row selection transistors 143 and 144 output to bit line 159. Each set of amplifying transistors 141 and 142 and row selection transistors 143 and 144 can be referred to as an output circuit.

[0027] Each pair of row select transistors 143, 144 connects the gates of the first and second row select transistors 143, 144 to one of the select lines 155. The pairs of row select transistors 143, 144 can be connected to different select lines 155. The select lines 155 can be organized into groups of four lines. Each group of select lines 155 can receive a portion of the row select signal. Each row select transistor can receive a smaller portion of the row select signal. Therefore, each row select transistor 143, 144 can be controlled by a portion of the row select signal.

[0028] The output circuits can be organized in rows between the groups of transfer transistors 120 to 123. Each output circuit in a row of output circuits can be connected to one of the select lines 155 in a group of select lines 155. For example, as illustrated in Figure 1A, a first pair of row select transistors 143, 144 can be connected to a first select line 155, a second pair of row select transistors 143, 144 can be connected to a second select line 155 in the same group of select lines 155 as the first select line 155, a third pair of row select transistors 143, 144 can be connected to a third select line 155 in the same group of select lines 155 as the first select line 155, and a fourth pair of row select transistors 143, 144 can be connected to a fourth select line 155 in the same group of select lines 155 as the first select line 155. This pattern can be repeated and continued in the horizontal direction. Other sizes and connection patterns of the groups of select lines 155 are also possible.

[0029] To reiterate, the output circuitry, comprising amplifying transistors 141 and 142 and row selection transistors 143 and 144, is each coupled to two sets of transfer transistors 120 to 123 and two bit lines. The output circuitry is coupled to receive collected charge from the sensing node 125 of the two sets of transfer transistors 120 to 123. Furthermore, the output circuitry is coupled to output an output signal to one or both of the two bit lines in response to a row selection signal. The output signal is based on the row selection signal, the collected charge at sensing node 125, and the connection group of the sets of transfer transistors 120 to 123.

[0030] The groups of transfer transistors 120 to 123 can be horizontally connected via hierarchical transistors 133 and 134. Hierarchical transistors 133 and 134 act as switches between the groups of transfer transistors 120 to 123 in each column and the sensing nodes 125 connected to the groups of transfer transistors 120 to 123. Therefore, hierarchical transistors 133 and 134 can also be used as hierarchical connection circuits connecting the sensing nodes 125 of two groups of transfer transistors 120 to 123 that are horizontally adjacent to each other. Hierarchical transistors 133 and 134 can be arranged in pairs with first hierarchical transistor 133 and second hierarchical transistor 134. The gate of each hierarchical transistor 133 and 134 in the pair is connected to the same hierarchical control line 153. Therefore, the connection of the groups of transfer transistors 120 to 123 can be controlled by hierarchical control signals transmitted through hierarchical control lines 153. The reset transistors (or reset switches) 131 and 132 and the group of hierarchical transistors 133 and 134 can be referred to as a hierarchical circuit.

[0031] The hierarchical control lines 153 can be organized into groups of four hierarchical control lines. The hierarchical circuitry can be organized into rows corresponding to the groups of transfer transistors 120 to 123. Each group of hierarchical transistors 133, 134 in a given row can be connected to one of the four hierarchical control lines 153 in a group of hierarchical control lines 153. As will be described in further detail below, the groups of hierarchical transistors 133, 134 can be connected to the hierarchical control lines 153 based on how the hierarchical arrangement of the groups of transfer transistors 120 to 123 is executed. Each group of hierarchical control lines 153 can receive a portion of the hierarchical control signal. Furthermore, each hierarchical control line can receive a smaller portion of the hierarchical control signal. Therefore, each hierarchical transistor 133, 134 can be controlled by a portion of the hierarchical control signal.

[0032] Each reset transistor 131, 132 may connect its source between the first and second stage transistors 133, 134. The gates of reset transistors 131, 132 may be connected to a reset line and receive a reset signal through the reset line. The drains of reset transistors 131, 132 may be connected to the reset voltage or charge at sensing node 125. When reset transistors 131, 132 and stage transistors 133, 134 are turned on, the reset voltage is transferred to sensing node 125. The charge from photodiodes 110 to 113 will reduce the voltage at sensing node 125, and therefore the voltage at the gates of amplifying transistors 141, 142 during collection. Therefore, the reset voltage is a voltage higher than ground.

[0033] Figure 1B illustrates a cross-section of Figure 1A as an example of the zigzag pattern 100, where the reset line 151, hierarchical control line 153, select line 155, transfer line 157, and bit line 159 are not shown. The gate of the first set of transfer transistors 120 is connected to the gate of the second set of transfer transistors 121, which is adjacent to the first set of transfer transistors 120 in the vertical direction. The fourth set of transfer transistors 123 is adjacent to the second set of transfer transistors 121 in the horizontal direction. When the hierarchical transistors are turned on, the third set of transfer transistors is connected to the first set of transfer transistors via hierarchical transistors 133 and 134. The gate of the third set of transfer transistors is connected to the gate of the fourth set of transfer transistors in the opposite direction to the vertical direction. The first set of transfer transistors 120 and the second set of transfer transistors 121 transfer charge to the same output circuit (including amplifying transistors 141, 142 and row select transistors 143 and 144). The third set of transfer transistors 122 and the fourth set of transfer transistors 123 transfer charge to different output circuits (including amplifying transistors 141, 142 and row select transistors 143 and 144).

[0034] To reiterate, the second and fourth groups of transfer transistors 121 and 123 are in the same row. The first group of transfer transistors 120 is in the row above the second and fourth groups of transfer transistors 121 and 123. The third group of transfer transistors 122 is in the row below the second and fourth groups of transfer transistors 121 and 123. The first and second groups of transfer transistors 120 and 121 are vertically aligned in the first column. The third and fourth groups of transfer transistors 122 and 123 are vertically aligned in the second column adjacent to the first column in the horizontal direction.

[0035] Figure 1C illustrates the connection of output circuit 145 to line 159. For simplicity, the reset line 151, BCL line 153, hierarchical circuit (including hierarchical transistors 133, 134 and reset transistors 131, 132), select line 155, and transfer line 157 are not shown. Figure 1C uses boxes to illustrate: output circuit 145, first photodiode circuit 126, second photodiode circuit 127, third photodiode circuit 128, and fourth photodiode circuit 129. Output circuit 145 includes amplifying transistors 141, 142 and output transistors 143, 144. The first to fourth photodiode circuits 126 to 129 respectively include first to fourth photodiodes 110 to 113 and first to fourth transfer transistors 120 to 123.

[0036] Bit lines 159 can be paired, each pair for one column of photodiode circuits 126 to 129 and output circuit 145. The output circuit 145 in the first column outputs an output signal based on the charge collected at the sensing nodes 125 of the first photodiode circuit 126 and the second photodiode circuit 127 to the bit line 159 of the first column. An output signal based on the charge collected at the sensing nodes 125 of the first photodiode circuit 126 in the first column is output to the first bit line 159 for the first column, and an output signal based on the charge collected at the sensing nodes 125 of the second photodiode circuit 127 in the first column is output to the second bit line 159 for the first column. Similarly, the output circuit 145 in the second column outputs an output signal based on the charge collected at the sensing nodes 125 of the third photodiode circuit 128 and the fourth photodiode circuit 129 to the bit line 159 of the second column. The output signal based on the charge collected at the sensing node 125 of the third photodiode circuit 128 in the second column is output to the first bit line 159 for the second column, and the output signal based on the charge collected at the sensing node 125 of the fourth photodiode circuit 129 in the second column is output to the second bit line 159 for the second column.

[0037] As will be explained in more detail below, multiple output signals from multiple output circuits 145 can be simultaneously output to a single bit line 159. The effect of outputting multiple output signals to a single bit line at once is to sum the output signals. Therefore, multiple output signals can be summed on bit line 159. Furthermore, as described with respect to the hierarchical circuit, a plurality of sensing nodes 125 can be connected, and the collected charges connected to the plurality of sensing nodes 125 can be hierarchically classified. Therefore, the output signals can be summed based on the hierarchically collected charges on bit line 159. Thus, hierarchical schemes such as 2×2 hierarchical and 3×3 hierarchical schemes can be implemented.

[0038] Figure 2 illustrates an example of an apparatus 200 including an image sensor circuit 220 according to the teachings of the present invention. The apparatus 200 may include an input controller (controller) 210, an image sensor circuit 220, an output processing circuit 230, and a memory 240.

[0039] The input controller 210 can be coupled to the control input of the image sensor circuit 220. The input may include a reset signal transferred via reset line 151, a hierarchical control signal transferred via hierarchical control line 153, a row selection signal transferred via selection line 155, and a transfer control signal transferred via transfer line 157.

[0040] Image sensor circuit 220 can receive control input and light 250 from input controller 210. Image sensor can output image to output processing circuit 230 via bit lines in response to control input and light 250.

[0041] Output processing circuitry 230 can receive and process image output. Output processing circuitry 230 can also communicate with input controller 210 to adjust control input. Output processing circuitry 230 can process images output to image and video files and store the image or video files in memory 240. Memory 240 may also contain computer-readable instructions for operating device 200. Output processing circuitry 230 can retrieve computer-readable instructions for operating device 200 from memory and control device 200 in response to said computer-readable instructions.

[0042] The input controller 210 can control the image sensor circuit 220 in various ways. One way the input controller 210 can control the image sensor circuit 220 is by controlling the number of pixels whose output charge is collected. This can be accomplished by transmitting control signals through a set of transfer lines 157, some of which do not have a voltage high enough to turn on the transfer transistors 120 to 123 connected to the transfer lines. Any voltage sufficient to turn on the transfer transistors 120 to 123 connected to the transfer lines can be referred to as the "on voltage," and any voltage insufficient to turn on the transfer transistors 120 to 123 can be referred to as the "off voltage." This convention can also refer to voltages sufficient to turn on other transistors. In one example, the transfer control signal may contain only the on voltage for one of the transfer lines 157, such that the output charge of only one of the photodiodes 110 to 113 is collected at the sensing node 125. Any combination of on and off voltages can be transmitted to the transfer lines 157 via the input controller 210.

[0043] The input controller 210 can control the image sensor circuit 220 in a second way by controlling the hierarchical arrangement of groups of transfer transistors 120 to 123. For example, the groups of transfer transistors can be grouped into one, two, four, or six groups by transmitting a hierarchical control signal via hierarchical control line 153. This will be explained in more detail below.

[0044] A third way the input controller 210 can control the image sensor circuit 220 is by controlling the row selection signal transmitted via the select line 155. This controls which bit lines receive the output signal (or output voltage) and from which row selection transistors 143, 144 transmit the output signal to the bit lines. Because multiple output circuits can output to the same bit lines, the row selection signal can quickly cycle through multiple groups of select lines 155 to capture images or video.

[0045] The input controller 210 also controls the reset signal transmitted via the reset line 151. When the reset signal and the grading control signal associated with the line connected to the grading circuit are both on, the voltage at the gates of the amplifying transistors 141 and 142 connected to the grading circuit is reset. Therefore, the input controller 210 can control the image sensor circuit 220 in a fourth way by controlling the reset signal and the grading control signal together to reset the voltage at the amplifier gates 141 and 142.

[0046] The input controller 210 can control the image sensor circuit 220 in various ways, which can be combined to sense images based on various modes of light 250, as will be explained in further detail below.

[0047] As an example, the input controller 210 can control the image sensor circuit 220 to output the content sensed by a photodiode 110 to 113 for each group of transfer transistors 120 to 123. This can be achieved by the following steps: (1) transmitting a transfer control signal containing only one turn-on voltage for each group of transfer lines 157; (2) transmitting a row selection signal, wherein each group of selection lines 155 is sequentially provided with a turn-on voltage in the two groups of selection lines 155; and (3) transmitting only the turn-off voltage in the hierarchical control signal. This process can then be performed for each of the other photodiodes 110 to 113 for each group of transfer transistors 120 to 123 by resetting the voltage of the gates of the amplifying transistors 141, 142 and then repeating the control of the transfer control signal, the row selection signal, and the hierarchical control signal, except that a different one of the groups of transfer lines 157 receives a turn-on voltage each time the control process is repeated. Therefore, in response to the transfer control signal, the group of transfer transistors 120 to 123 can be coupled to selectively sum the output charge from photodiodes 110 to 113. This process provides a great deal of detail, but takes more time than other processes.

[0048] As a second example, the input controller 210 controls the image sensor circuit 220 to output a hierarchical output of six groups of transfer transistors 120 to 123. Since every other transfer transistor in a group of 120 to 123 is the same color, and the others are different colors, the output charges of all six transistors in each group of 120 to 123 should not be summed together. This is achieved by transmitting a transfer control signal with a conduction voltage only at any given time through transfer lines 157 connected to one of the colors in each group of 120 to 123. The group of transfer transistors 120 to 123 that does not receive the transfer control signal with a conduction voltage will provide capacitance for the set of charges of the group of transfer transistors 120 to 123 that receives the transfer control signal with a conduction voltage. For example, in a row of transfer transistors 120 to 123 that includes the first and third transfer transistors 120 and 122, at any given time, neither the transfer line 157 connected to the group of first transfer transistors 120 nor the transfer line 157 connected to the group of third transfer transistors 122 is provided with a transfer control signal containing a turn-on voltage.

[0049] The hierarchical grouping of six groups of transfer transistors can be achieved by the following steps: (1) transmitting a transfer control signal containing an on-state voltage for the first group of transfer lines 157; (2) transmitting a row selection signal to a group of selection lines 155 grouped with the first group of transfer lines 157, wherein the row selection signal contains an on-state voltage for each of the selection lines 155 in the group; (3) transmitting a hierarchical control signal to a hierarchical control line 153 grouped with the first group of transfer lines 157, wherein the hierarchical control signal contains an on-state voltage for three of the hierarchical control lines 153; and (4) repeating (1) to (3) for each of the other groups of transfer lines 157. Therefore, the hierarchical circuit including hierarchical transistors 133 and 134 can be coupled to electrically connect groups of transfer transistors 120 to 123 into a group of groups of transfer transistors 120 to 123 in response to the hierarchical control signal.

[0050] This process will output an output voltage on the bit line for each group of transfer transistors 120 to 123 connected to the first group of transfer lines 157. For example, the group of first and second transfer transistors 120 and 121, or the group of third and fourth transfer transistors 120 and 123.

[0051] The source follower grading process (where the output is graded at the bit line, associated with the voltage from the source follower row select transistor) can also be performed by the input controller 210 by providing a transfer control signal with an on-state voltage and a row select signal to multiple groups of transfer lines 157 and select lines 155. For example, as described above, a 3×3 grading process can also be performed by grading the six groups of transfer transistors into three groups of transfer lines 157 and select lines 155 each time (the groups of transfer lines 157 and select lines 155 are every other group in the vertical direction, such that the output charge is used only for the three in the first row or the three in the second row). Any other number of grading schemes, such as 2×1, 2×2, 3×1, can also be performed by the input controller 210.

[0052] The time required to execute a 3×3 hierarchical output may be significantly faster than the time required to execute an output from a 1×1 output (approximately 36 times faster); however, the amount of detail in the final image or video will be less (approximately 1 / 9).

[0053] Figure 3 illustrates an example connection of a photodiode circuit according to the teachings of the present invention. First and second photodiode circuits 301 and 303 can be connected via a hierarchical switch 302, both from the first photodiode circuit 301 to the second photodiode circuit 303 and from the second photodiode circuit 303 to the first photodiode circuit 301. The first and second photodiode circuits 301 and 303 may represent transfer transistors 120 to 123 in the first or second row of the image sensor circuit 220 and corresponding groups connected to photodiodes 110 to 113. For example, the first photodiode circuit 301 may be a group of first transfer transistors 120, and the second photodiode circuit 303 may be a group of third transfer transistors 122. Alternatively, the first photodiode circuit 301 may be a group of second transfer transistors 121, and the second photodiode circuit 303 may be a group of fourth transfer transistors 123. The hierarchical switch 302 may be a hierarchical circuit, each comprising a pair of reset transistors 131 and 132 and hierarchical transistors 133 and 134.

[0054] Figure 3 illustrates how the pattern of connecting the hierarchical control lines 153 using the hierarchical switch 302 partially illustrated in Figure 1A (Figure 1A shows the first eight hierarchical circuits of the twelve hierarchical circuit patterns described below). The pattern repeats after every 12 photodiode circuits 301, 303. Every other hierarchical switch 302, starting with the first hierarchical switch 302, can be connected to the first hierarchical control line BCL1. The second and tenth hierarchical switches 302 can be connected to the second hierarchical control line BCL2. The fourth and eighth hierarchical switches 302 can be connected to the third hierarchical control line BCL3. The sixth hierarchical switch 302 can be connected to the fourth hierarchical control line BCL4. The twelfth hierarchical switch 302 can always be off during output readout and can be left unconnected to one of the hierarchical control lines 153. The twelfth hierarchical switch 302 can be omitted (it can correspond to a gap in the connection between two photodiode circuits instead of a hierarchical circuit). Alternatively, the twelfth hierarchical switch 302 can be connected to the reset line so that it is used only to reset the voltage at the gates of the amplifying transistors 141 and 142. The connection pattern can be repeated for any number of photodiode circuits.

[0055] Figure 3 illustrates the transmission of an on-state voltage through one of the graded control lines 153 by showing a closed graded switch 302 in a graded graphical representation or a number "1" in a table. Similarly, an open graded switch 302 in a graded graphical representation or a number "0" in a table illustrates the off-state voltage. The table contains an indication of which graded control line each graded switch 302 is connected to in this example embodiment. Other configurations of the graded switch 302 are also possible.

[0056] The input controller 210 can control the grading switch using four different floating diffusion grading modes: High Normal Gain (HCG) mode, Low Normal Gain (LCG) mode, bin2 mode, and bin3 mode. In each of these modes, the line selection signal, transfer control signal, grading control signal, and reset control signal can be sent at different rates regarding the frequency at which these signals will be effective in controlling the image sensor circuitry. The rate of change of the input signal depends on the mode and the source follower grading at the bit line. For example, when the grading control signal is the first signal for HCG mode, the input controller 210 can change the line selection signal at a first rate; when the grading control signal is the second signal for LCG mode, the input controller 210 can change the line selection signal at a second rate; when the grading control signal is the third signal for Bin2 mode, the input controller 210 can change the line selection signal at a third rate; and when the grading control signal is the fourth signal for Bin3 mode, the input controller 210 can change the line selection signal at a fourth rate.

[0057] In HCG mode, all grading control lines 153 receive a shutdown voltage, and photodiode circuits 301 and 303 are not graded via grading switch 302. HCG mode provides the highest resolution to output processing circuit 230, and is the slowest. As described above, HCG mode can be paired with selection of photodiode output via transfer control signals to provide even more detailed images or videos. This mode can be used for still photography, where a large amount of information will be collected, and there is not much movement in the image; the image may become blurry due to the time required to capture a detailed image.

[0058] In LCG mode, the first grade control line (BCL) BCL1 receives the turn-on voltage, while the other grade control lines 153 receive the turn-off voltage. Therefore, LCG mode groups the photodiode circuits 301 and 303 into two groups of photodiode circuits 301 and 303. As described above, because the group of two photodiode circuits 301 and 303 will contain two photodiode circuits 301 and 303 of different colors, only one of the photodiode circuits will receive the transfer control signal to output the graded photodiode charge. The other photodiode circuits 301 and 303 will provide capacitance for collecting the photodiode charge.

[0059] In Bin2 mode, the first, second, and fourth hierarchical control lines 153BCL1, BCL2, and BCL4 receive the turn-on voltage, while the third hierarchical control line BCL3 receives the turn-off voltage. Therefore, Bin2 mode groups the photodiode circuits 301 and 303 into groups of four photodiode circuits 301 and 303. As described above, because the groups of four photodiode circuits 301 and 303 will contain photodiode circuits 301 and 303 of different colors (two photodiode circuits 301 and 303 for each color), only one color of the photodiode circuit will receive the transfer control signal to output the hierarchical photodiode charge. The other photodiode circuits 301 and 303 will provide capacitors for collecting the photodiode output charge. Bin2 mode is faster than HCG or LCG modes, especially when paired with source followers at bit lines, for example, in a 2×2 hierarchical scheme. Therefore, Bin2 mode can be used for higher frame rate video with lower image quality.

[0060] In Bin3 mode, the first, second, and third hierarchical control lines 153BCL1, BCL2, and BCL3 receive the turn-on voltage, and the fourth hierarchical control line BCL4 receives the turn-off voltage. Therefore, Bin3 mode groups the photodiode circuits 301 and 303 into groups of six photodiode circuits 301 and 303. As described above, because the groups of six photodiode circuits 301 and 303 will contain photodiode circuits 301 and 303 of two different colors (three photodiode circuits 301 and 303 for each color), only one color of the photodiode circuit will receive the transfer control signal to output the hierarchical photodiode charge. The other photodiode circuits 301 and 303 will provide capacitors for collecting the photodiode output charge. Bin3 mode is faster than HCG, LCG, or Bin2 modes, especially when hierarchical pairing with the source follower is completed at the bit line level, for example, in a 3×3 hierarchical scheme. Therefore, Bin3 mode can be used for fast video modes with higher frame rates but lower image quality. Bin3 mode can also be used for low-light photography.

[0061] In the mode described above, the hierarchical circuit including hierarchical transistors 133 and 134 can be coupled to electrically connect groups of transfer transistors 120 to 123 into a group of groups of transfer transistors 120 to 123; said group includes any one, two, four or six groups of transfer transistors 120 to 123.

[0062] As can be understood from the above description of the circuit system and the operating modes for controlling the circuit system, the present invention provides an image sensor circuit 220 that is highly versatile and has a small amount of space required for control lines for transmitting control signals for the circuit system.

[0063] The above description of the illustrative examples of the present invention (including those described in the abstract) is not intended to be exhaustive or limited to the specific forms disclosed. Although specific embodiments and examples of the invention have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the invention. Indeed, it should be understood that specific examples of voltage, current, frequency, power range values, time, etc., are provided for illustrative purposes, and other values ​​may be used in other embodiments and examples according to the teachings of the present invention.

[0064] These modifications can be made to the embodiments of the invention based on the above detailed description. The terminology used in the appended claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope should be fully defined by the appended claims, which should be interpreted according to the established principles of claim interpretation. Therefore, this specification and drawings are to be considered illustrative rather than restrictive.

Claims

1. A photodiode array circuit, comprising: A plurality of photodiode circuits, each of which is coupled to selectively collect output charge from the plurality of photodiodes to a sensing node in the photodiode circuit in response to a transfer control signal; A hierarchical circuit system, coupled to electrically connect the plurality of photodiode circuit sensing nodes into a photodiode circuit sensing node group in response to a hierarchical control signal; a plurality of output circuits, each coupled to two of the plurality of photodiode circuits and two bit lines, wherein the plurality of output circuits are coupled to receive the output charge from the two of the plurality of photodiode circuits, wherein the plurality of output circuits are coupled to output an output signal to one of the two bit lines in response to a row selection signal, the output charge and the photodiode circuit sensing node group; and control circuitry, which is coupled to provide the transfer control signal, the row selection signal and the hierarchical control signal.

2. The photodiode array circuit of claim 1, wherein the plurality of photodiode circuits are arranged in a grid, wherein two of the plurality of photodiode circuits coupled to each of the plurality of output circuits are adjacent to each other in a first direction, and wherein the hierarchical circuit system electrically connects the photodiode circuit sensing nodes into a group in a second direction perpendicular to the first direction.

3. The photodiode array circuit according to claim 2, wherein a first of the plurality of photodiode circuits and a second of the plurality of photodiode circuits adjacent to the first of the plurality of photodiode circuits in the first direction are coupled to the same of the plurality of output circuits, and wherein a third of the plurality of photodiode circuits adjacent to the first of the plurality of photodiode circuits in the second direction and a fourth of the plurality of photodiode circuits adjacent to the third of the plurality of photodiode circuits in a direction opposite to the first direction are coupled to the same of the plurality of output circuits.

4. The photodiode array circuit of claim 1, wherein the hierarchical circuit system includes a reset switch coupled to reset the output charge at the sensing node in response to a reset signal.

5. The photodiode array circuit of claim 1, wherein the control circuit is configured to change the row selection signal at each of the following rates: a first rate when the row selection signal is a first signal, a second rate when the row selection signal is a second signal, a third rate when the row selection signal is a third signal, and a fourth rate when the row selection signal is a fourth signal.

6. The photodiode array circuit of claim 1, wherein the plurality of output circuits are organized into columns, wherein each column output circuit is coupled to output the output signal of the column output circuit to the two bit lines, wherein the control circuit is coupled to provide the row selection signal such that the output signals from the plurality of output circuits in a column output circuit are summed on one of the two bit lines for the column output circuit.

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