Reference voltage and current generation circuit

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a reference voltage and current generation circuit. A reference voltage and current generation circuit includes: a startup circuit having a startup terminal; a generation circuit connected to the startup terminal, and the generation circuit is started by the startup circuit; the generation circuit can generate a reference voltage and a reference current simultaneously. The present invention can realize a reference voltage and a reference current by using one circuit, which can greatly save the chip area and reduce the power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a reference voltage and current generation circuit. Background Art

[0002] Reference voltage and reference current are two basic modules of integrated circuits. Currently, the common practice is to use two separate module designs. There are many design methods for reference voltage. Using MOS transistors in the subthreshold region has the advantages of low power consumption and small area. Figure 1 The gate-source voltage of an NMOS transistor operating in the subthreshold region generates a voltage V with a negative temperature coefficient CTAT , and the difference between the gate-source voltages of two NMOS transistors operating in the subthreshold region generates a voltage V with a positive temperature coefficient PTAT , the voltage V CTAT and the voltage V PTAT are weighted to obtain the bandgap reference voltage VREF. Figure 2 It is a method of weighted addition of a current I1 with a positive temperature coefficient and a current I2 with a negative temperature coefficient to obtain a reference current IREF with a low temperature coefficient.

[0003] To implement the reference voltage and reference current, usually Figure 1 and Figure 2 two types of circuits are required. Therefore, it is necessary to use one circuit to generate the reference voltage and current, effectively reducing power consumption and reducing area. Summary of the Invention (

[0004] Aiming at the technical problem that when it is necessary to implement the reference voltage and reference current, two types of circuits are required respectively, resulting in high power consumption and large occupied area, the purpose of the present invention is to provide a reference voltage and current generation circuit.

[0005] A reference voltage and current generation circuit includes:

[0006] A startup circuit with a startup terminal;

[0007] A generation circuit connected to the startup terminal, and the generation circuit is started by the startup circuit;

[0008] The generation circuit includes:

[0009] A first resistor, one end of which is connected to the startup terminal of the startup circuit;

[0010] A second resistor, one end of which is connected to the startup terminal of the startup circuit and the other end is grounded;

[0011] A first MOS transistor, the gate of which is connected to the startup terminal of the startup circuit, the drain is connected to the other end of the first resistor, and the source is grounded;

[0012] A second MOS transistor, with its gate connected to the startup terminal of the startup circuit and its source grounded;

[0013] A third MOS transistor, with its gate connected to the other end of the first resistor and its source grounded;

[0014] A fourth MOS transistor, with its gate connected to the startup terminal of the startup circuit and its source connected to the drain of the second MOS transistor;

[0015] A fifth MOS transistor, with its gate connected to the gate of the fourth MOS transistor and its source connected to the drain of the third MOS transistor;

[0016] A sixth MOS transistor, with its gate connected to its drain, its drain connected to the drain of the fourth MOS transistor, and its source connected to the power input terminal;

[0017] A seventh MOS transistor, with its gate connected to the gate of the sixth MOS transistor, its drain connected to the drain of the fifth MOS transistor, and its source connected to the power input terminal;

[0018] An eighth MOS transistor, with its gate connected to the common terminal between the drain of the fifth MOS transistor and the drain of the seventh MOS transistor, its drain respectively connected to the gate of the fourth MOS transistor and the gate of the fifth MOS transistor, and its source connected to the power input terminal;

[0019] A ninth MOS transistor, with its gate connected to the gate of the eighth MOS transistor, its drain serving as the reference current output terminal, and its source connected to the power input terminal;

[0020] A tenth MOS transistor, with its gate connected to the gate of the eighth MOS transistor, its drain serving as the reference voltage output terminal, and its source connected to the power input terminal;

[0021] A third resistor, with one end connected to the drain of the tenth MOS transistor;

[0022] A fourth resistor, with one end connected to the other end of the third resistor and the other end grounded.

[0023] As a preferred solution, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are all NMOS transistors;

[0024] The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are all PMOS transistors.

[0025] As a preferred solution, the width-to-length ratio of the conductive channel of the first MOS transistor is equal to the width-to-length ratio of the conductive channel of the second MOS transistor;

[0026] The width-to-length ratio of the conductive channel of the third MOS transistor is N times that of the conductive channel of the first MOS transistor, where N is a preset constant.

[0027] As a preferred solution, the width-to-length ratio of the conductive channel of the fourth MOS transistor is equal to that of the conductive channel of the fifth MOS transistor;

[0028] The width-to-length ratio of the conductive channel of the sixth MOS transistor is equal to that of the conductive channel of the seventh MOS transistor.

[0029] As a preferred solution, after the first MOS transistor, the second MOS transistor, and the third MOS transistor are started by the startup circuit, they all operate in the subthreshold region.

[0030] As a preferred solution, the first resistor and the second resistor are of the same type.

[0031] As a preferred solution, the third resistor is of the same type as the first resistor.

[0032] As a preferred solution, the fourth resistor has a temperature coefficient opposite to that of the third resistor.

[0033] As a preferred solution, the startup circuit includes:

[0034] A startup resistor with one end connected to the power input terminal;

[0035] An eleventh MOS transistor with its drain connected to the other end of the startup resistor and its source grounded;

[0036] A twelfth MOS transistor with its gate connected to the other end of the startup resistor, its drain connected to the power input terminal, and its source connected to the gate of the eleventh MOS transistor;

[0037] The common terminal between the gate of the eleventh MOS transistor and the source of the twelfth MOS transistor serves as the startup terminal of the startup circuit.

[0038] As a preferred solution, the eleventh MOS transistor and the twelfth MOS transistor are NMOS transistors.

[0039] The positive and progressive effects of the present invention are as follows: The present invention adopts a reference voltage and current generation circuit, which has the following advantages:

[0040] 1. A single circuit can be used to implement both the reference voltage and the reference current, which can greatly save chip area and reduce power consumption.

[0041] 2. The introduction of the first resistor and the second resistor, especially the second resistor, effectively generates a current with a negative temperature coefficient in a circuit with a positive temperature coefficient.

[0042] 3. The introduction of the eighth MOS transistor simply realizes the addition of two currents with different temperature coefficients.

[0043] 4. The third resistor and the fourth resistor are made of resistors with different temperature coefficients, and it is very simple to realize a reference voltage with a low temperature coefficient. Description of the Drawings

[0044] Figure 1 is a conventional reference voltage generation circuit;

[0045] Figure 2 is a conventional reference current generation circuit;

[0046] Figure 3 is a schematic circuit diagram of the present invention;

[0047] Figure 4 is a curve of the reference current of the present invention varying with temperature;

[0048] Figure 5 is a curve of the reference voltage of the present invention varying with temperature. Detailed Embodiment

[0049] In order to make the technical means, creative features, achieved purposes and effects of the present invention easy to understand, the present invention will be further described below with reference to specific drawings.

[0050] Referring to Figure 3 , the present invention provides a reference voltage and current generation circuit, including a startup circuit 1 and a generation circuit 2 for generating a reference voltage and a reference current. The startup circuit 1 has a startup terminal. As shown in Figure 3 , point A is the startup terminal, and this startup terminal is connected to the generation circuit 2. The startup circuit 1 starts the generation circuit 2 to generate a reference voltage and a reference current simultaneously.

[0051] Referring to Figure 3 , the generation circuit 2 of the present invention includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10.

[0052] One end of the first resistor R1 is connected to the startup terminal of the startup circuit 1, and the other end of the first resistor R1 is respectively connected to the drain of the first MOS transistor M1 and the gate of the third MOS transistor M3.

[0053] One end of the second resistor R2 is connected to the startup terminal of the startup circuit 1, and the other end of the second resistor R2 is grounded.

[0054] The gate of the first MOS transistor M1 is connected to the startup terminal of the startup circuit 1. The drain of the first MOS transistor M1 is connected to the other end of the first resistor R1. The source of the first MOS transistor M1 is grounded.

[0055] The gate of the second MOS transistor M2 is connected to the startup terminal of the startup circuit 1. The drain of the second MOS transistor M2 is connected to the source of the fourth MOS transistor M4. The source of the second MOS transistor M2 is grounded.

[0056] The gate of the third MOS transistor M3 is connected to the other end of the first resistor R1. The drain of the third MOS transistor M3 is connected to the source of the fifth MOS transistor M5. The source of the third MOS transistor M3 is grounded.

[0057] The gate of the fourth MOS transistor M4 is connected to the startup terminal of the startup circuit 1. The drain of the fourth MOS transistor M4 is connected to the drain of the sixth MOS transistor M6. The source of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2.

[0058] The gate of the fifth MOS transistor M5 is connected to the gate of the fourth MOS transistor M4. The drain of the fifth MOS transistor M5 is connected to the drain of the seventh MOS transistor M7. The source of the fifth MOS transistor M5 is connected to the drain of the third MOS transistor M3.

[0059] The gate of the sixth MOS transistor M6 is connected to its drain. The drain of the sixth MOS transistor M6 is connected to the drain of the fourth MOS transistor M4. The source of the sixth MOS transistor M6 is connected to the power input terminal VDD.

[0060] The gate of the seventh MOS transistor M7 is connected to the gate of the sixth MOS transistor M6. The drain of the seventh MOS transistor M7 is connected to the drain of the fifth MOS transistor M5. The source of the seventh MOS transistor M7 is connected to the power input terminal VDD.

[0061] The gate of the eighth MOS transistor M8 is connected to the common terminal between the drains of the fifth MOS transistor M5 and the seventh MOS transistor M7. The drain of the eighth MOS transistor M8 is connected to the gates of the fourth MOS transistor M4 and the fifth MOS transistor M5 respectively. The source of the eighth MOS transistor M8 is connected to the power input terminal VDD.

[0062] The gate of the ninth MOS transistor M9 is connected to the gate of the eighth MOS transistor M8. The drain of the ninth MOS transistor M9 serves as the reference current output terminal IREF. The source of the ninth MOS transistor M9 is connected to the power input terminal VDD.

[0063] The gate of the tenth MOS transistor M10 is connected to the gate of the eighth MOS transistor M8. The drain of the tenth MOS transistor M10 serves as the reference voltage output terminal VREF. The source of the tenth MOS transistor M10 is connected to the power input terminal VDD.

[0064] One end of the third resistor R3 is connected to the drain of the tenth MOS transistor M10, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4.

[0065] One end of the fourth resistor R4 is connected to the other end of the third resistor R3, and the other end of the fourth resistor R4 is grounded.

[0066] In some embodiments, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 are all NMOS transistors. The sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all PMOS transistors.

[0067] In some embodiments, the aspect ratio of the conductive channel of the first MOS transistor M1 is equal to the aspect ratio of the conductive channel of the second MOS transistor M2, and the aspect ratio of the conductive channel of the third MOS transistor M3 is N times the aspect ratio of the conductive channel of the first MOS transistor M1, where N is a preset constant.

[0068] In some embodiments, the aspect ratio of the conductive channel of the fourth MOS transistor M4 is equal to the aspect ratio of the conductive channel of the fifth MOS transistor M5. The aspect ratio of the conductive channel of the sixth MOS transistor M6 is equal to the aspect ratio of the conductive channel of the seventh MOS transistor M7. As a result, the source-drain currents of the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are equal.

[0069] In some embodiments, after the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are activated by the activation circuit 1, they all operate in the subthreshold region.

[0070] In some embodiments, the first resistor R1 and the second resistor R2 are of the same type.

[0071] In some embodiments, the third resistor R3 is of the same type as the first resistor R1.

[0072] In some embodiments, the fourth resistor R4 is a resistor with a temperature coefficient opposite to that of the third resistor R3.

[0073] In some embodiments, referring to Figure 3 , the activation circuit 1 includes an activation resistor R0, an eleventh MOS transistor M11, and a twelfth MOS transistor M12.

[0074] One end of the activation resistor R0 is connected to the power input terminal VDD, and the other end of the activation resistor R0 is respectively connected to the drain of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12.

[0075] The drain of the eleventh MOS transistor M11 is connected to the other end of the startup resistor R0, and the source of the eleventh MOS transistor M11 is grounded.

[0076] The gate of the twelfth MOS transistor M12 is connected to the other end of the startup resistor R0, the drain of the twelfth MOS transistor M12 is connected to the power input terminal VDD, and the source of the twelfth MOS transistor M12 is connected to the gate of the eleventh MOS transistor M11.

[0077] The common terminal between the gate of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12 serves as the startup terminal of the startup circuit 1, that is, as Figure 3 point A in

[0078] Specifically, when there is no current in the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3, there is also no current in the eleventh MOS transistor M11. In this way, the gate of the twelfth MOS transistor M12 is pulled to the voltage input terminal VDD, raising the potential of point A, causing the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 to start conducting, starting the reference current IREF. At the same time, the eleventh MOS transistor M11 also starts conducting, causing the potential of the twelfth MOS transistor M12 to start decreasing. When the current in the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 reaches a certain level, the potential of the twelfth MOS transistor M12 is pulled to a low level, the twelfth MOS transistor M12 is turned off, and the startup circuit 1 stops working.

[0079] In some embodiments, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are NMOS transistors.

[0080] In some embodiments, referring to Figure 3 , when the width-to-length ratios of the conductive channels of the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are such that they all operate in the subthreshold region, the drain-source current operating in the subthreshold region can be expressed as:

[0081]

[0082] where μ represents the carrier mobility of the MOS transistor; C ox represents the gate oxide capacitance per unit area; m is the subthreshold slope factor, and the specific value is process-related; V T represents the thermal voltage; W and L respectively represent the width and length of the conductive channel; V GS represents the gate-source voltage of the MOS transistor; V TH represents the threshold voltage.

[0083] Equation (1) can be simplified to:

[0084]

[0085] where β = μC ox (m - 1)V T 2

[0086] From (2), it can be obtained that:

[0087]

[0088] Then, the current I flowing through the first resistor R1 R1 is:

[0089]

[0090] where

[0091] Therefore, the current flowing through the first resistor R1 increases as the temperature increases.

[0092] The current I flowing through the second resistor R2 R2 is:

[0093]

[0094] Since V TH has a negative temperature coefficient, the magnitude of I R2 decreases as the temperature increases.

[0095] The current I flowing through the eighth MOS transistor M8 M8 is: I M8 = I R1 + I R2 , when the first resistor R1 and the second resistor R2 are of the same type, by reasonably selecting the resistance ratio of the first resistor R1 and the second resistor R2, a low temperature coefficient current can be obtained for the eighth MOS transistor M8.

[0096] The ninth MOS transistor M9 and the eighth MOS transistor M8 are current mirrors. By selecting the aspect ratio of the conductive channel of the ninth MOS transistor M9, a reference current IREF with a low temperature coefficient can be obtained, as shown in Figure 4 .

[0097] Similarly, the tenth MOS transistor M10 and the eighth MOS transistor M8 form a current mirror. The current of the tenth MOS transistor M10 also has a low temperature coefficient. The reference voltage VREF can be expressed as VREF = IREF(R3 + R4). Since the resistor itself has a certain temperature coefficient, if the third resistor R3 and the fourth resistor R4 are of the same type as the first resistor R1 and the second resistor R2, the reference voltage VREF will have a high temperature coefficient. In the present invention, the first resistor R1, the second resistor R2, and the third resistor R3 are preferably of the same type of resistor, and the fourth resistor R4 is preferably a resistor with a temperature coefficient opposite to that of the third resistor R3. By selecting a reasonable resistance ratio of the third resistor R3 and the fourth resistor R4, a reference voltage VREF with a low temperature coefficient can be obtained, as Figure 5 shown in

[0098] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification are only used to illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A reference voltage and current generation circuit, characterized in that Comprising: A startup circuit having a startup terminal; A generating circuit connected to the startup terminal, and the generating circuit is started by the startup circuit; The generating circuit includes: A first resistor, one end of which is connected to the startup terminal of the startup circuit; A second resistor, one end of which is connected to the startup terminal of the startup circuit and the other end is grounded; A first MOS transistor, the gate of which is connected to the startup terminal of the startup circuit, the drain of which is connected to the other end of the first resistor, and the source of which is grounded; A second MOS transistor, the gate of which is connected to the startup terminal of the startup circuit and the source of which is grounded; A third MOS transistor, the gate of which is connected to the other end of the first resistor and the source of which is grounded; A fourth MOS transistor, the gate of which is connected to the startup terminal of the startup circuit and the source of which is connected to the drain of the second MOS transistor; A fifth MOS transistor, the gate of which is connected to the gate of the fourth MOS transistor and the source of which is connected to the drain of the third MOS transistor; A sixth MOS transistor, the gate of which is connected to the drain, the drain of which is connected to the drain of the fourth MOS transistor, and the source of which is connected to the power input terminal; A seventh MOS transistor, the gate of which is connected to the gate of the sixth MOS transistor, the drain of which is connected to the drain of the fifth MOS transistor, and the source of which is connected to the power input terminal; An eighth MOS transistor, the gate of which is connected to the common terminal between the drain of the fifth MOS transistor and the drain of the seventh MOS transistor, the drain of which is respectively connected to the gate of the fourth MOS transistor and the gate of the fifth MOS transistor, and the source of which is connected to the power input terminal; A ninth MOS transistor, the gate of which is connected to the gate of the eighth MOS transistor, the drain of which is used as the reference current output terminal, and the source of which is connected to the power input terminal; A tenth MOS transistor, the gate of which is connected to the gate of the eighth MOS transistor, the drain of which is used as the reference voltage output terminal, and the source of which is connected to the power input terminal; A third resistor, one end of which is connected to the drain of the tenth MOS transistor; 2. The reference voltage and current generation circuit according to claim 1, wherein A fourth resistor, one end of which is connected to the other end of the third resistor and the other end is grounded. The first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all NMOS transistors; 3. The reference voltage and current generation circuit according to claim 1, characterized in that, The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor are all PMOS transistors. The width-to-length ratio of the conductive channel of the first MOS transistor is equal to the width-to-length ratio of the conductive channel of the second MOS transistor; 4. The reference voltage and current generation circuit according to claim 3, characterized in that, The width-to-length ratio of the conductive channel of the third MOS transistor is N times the width-to-length ratio of the conductive channel of the first MOS transistor, where N is a preset constant; The width-to-length ratio of the conductive channel of the fourth MOS transistor is equal to the width-to-length ratio of the conductive channel of the fifth MOS transistor; 5. The reference voltage and current generating circuit according to claim 1, characterized in that The width-to-length ratio of the conductive channel of the sixth MOS transistor is equal to the width-to-length ratio of the conductive channel of the seventh MOS transistor.

6. The reference voltage and current generation circuit according to claim 1, wherein After being started by the startup circuit, the first MOS transistor, the second MOS transistor and the third MOS transistor all operate in the subthreshold region; 7. The reference voltage and current generating circuit according to claim 6, wherein The first resistor and the second resistor are of the same type of resistor; 8. The reference voltage and current generation circuit according to claim 7, wherein The third resistor is of the same type of resistor as the first resistor; 9. The reference voltage current generation circuit according to any one of claims 1 to 8, characterized in that, The fourth resistor is a resistor with a temperature coefficient opposite to that of the third resistor; The startup circuit includes: A starting resistor, one end of which is connected to the power input terminal; An eleventh MOS transistor, the drain of which is connected to the other end of the starting resistor, and the source is grounded; A twelfth MOS transistor, the gate of which is connected to the other end of the starting resistor, the drain is connected to the power input terminal, and the source is connected to the gate of the eleventh MOS transistor; The common terminal between the gate of the eleventh MOS transistor and the source of the twelfth MOS transistor serves as the starting terminal of the starting circuit.

10. The reference voltage and current generating circuit according to claim 9, characterized in that, The eleventh MOS transistor and the twelfth MOS transistor are NMOS transistors.

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