Quantifiable Instruction Scheduling Method and System for SIMD and VLIW Architectures

Abstract

The present invention discloses a quantifiable instruction scheduling method and system for SIMD and VLIW architectures. The present invention includes performing instruction parsing on the source code of a program; traversing the source code of the program to determine the scale of basic blocks; when the scale of a basic block is greater than a preset threshold k, executing an instruction scheduling strategy with functional unit pressure awareness to obtain a scheduling scheme; when the scale of a basic block is less than or equal to k, executing an instruction scheduling strategy based on functional unit pressure awareness and obtaining a scheduling scheme; calculating the lower bound of the scheduling length of the current basic block, and calculating the scheduling efficiency of the current basic block according to its actual scheduling length. The present invention can provide a suitable scheduling strategy for instruction scheduling problems of a specific scale, combine the allocation problems of time slots and functional units from a global perspective, improve the instruction scheduling efficiency, and solve the problem that the heuristic scheduling algorithms commonly used in existing mainstream compilers cannot perform quantitative analysis and the results are difficult to achieve optimality.

Description

Technical Field

[0001] The present invention relates to the technical field of compiler optimization of DSP (Digital Signal Processor), and particularly relates to a quantifiable instruction scheduling method and system for SIMD and VLIW architectures. Background Art

[0002] DSP (Digital Signal Processor) usually includes VLIW (Very Long Instruction Word) and SIMD (Single Instruction Multiple Data) architectures, which bring computing performance, real-time processing, and power efficiency to various embedded applications. The performance of a SIMD+VLIW architecture processor depends to a large extent on instruction-level parallelism, and the exploitation of instruction-level parallelism relies on the instruction scheduling efficiency of the compiler. Therefore, the choice of the instruction scheduling algorithm is crucial for the performance of the processor.

[0003] In the field of compilation, current mainstream industrial compilers (such as LLVM) widely adopt heuristic algorithms as instruction scheduling algorithms, mainly due to their advantages of simple implementation and small time cost. Instruction scheduling is actually a two-dimensional integer linear programming problem, which needs to allocate appropriate time slots and functional units for instructions. The current heuristic algorithm first allocates time slots for instructions and then allocates functional units for them. When it encounters the situation that the functional unit allocated for the current instruction has been occupied, it needs to reduce the priority of this instruction until an available functional unit is found for it. Therefore, the heuristic adopts a local optimization strategy, selecting any feasible solution from the solution space as the final solution, which also results in the final scheduling result being difficult to reach the optimal or even sub-optimal level and the scheduling efficiency being difficult to predict. To improve the instruction scheduling efficiency and thus generate higher-quality code, optimization algorithms (such as the branch and bound method) can be used to provide the optimal solution for the instruction scheduling problem, but such algorithms often have the problem of excessive computational complexity and are only applicable to small-scale problems. For compilers, compilation time is also an important consideration, so optimization algorithms are often not adopted in practical applications. Summary of the Invention

[0004] The technical problem to be solved by the present invention: Aiming at the above problems of the prior art, a quantifiable instruction scheduling method and system for SIMD and VLIW architectures are provided. The present invention can realize providing a suitable scheduling strategy for a specific scale of instruction scheduling problems, combining the allocation problems of time slots and functional units from a global perspective, improving the instruction scheduling efficiency, and solving the problem that the heuristic scheduling algorithms commonly adopted by existing mainstream compilers cannot perform quantitative analysis and the results are difficult to reach the optimal level.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0006] A quantifiable instruction scheduling method for SIMD and VLIW architectures, comprising:

[0007] S101. Parse the instructions in the source code of the program to determine the dependency relationship and execution cycle between instructions;

[0008] S102. Traverse the basic blocks in the source code of the program to determine the scale of the basic blocks;

[0009] S103. When the scale of the basic block is greater than the preset threshold k, perform instruction scheduling for functional unit pressure perception according to the dependency relationship and execution cycle between instructions to obtain a scheduling plan;

[0010] S104. Calculate the actual scheduling length of the current basic block and determine the lower bound of the scheduling length of the current basic block;

[0011] S105. Divide the lower bound of the scheduling length by the actual scheduling length to obtain the scheduling efficiency of the current basic block.

[0012] Optionally, the instruction scheduling for functional unit pressure perception in step S103 includes:

[0013] S201. Calculate the functional unit pressure of each instruction in the current basic block according to the execution cycle of the instruction;

[0014] S202. Determine the priority of each instruction according to the functional unit pressure and construct an instruction list according to the priority;

[0015] S203. Traverse and take out the instruction with the highest priority from the instruction list of the current basic block as the current instruction;

[0016] S204. Allocate a time slot and a functional unit for the current instruction and pop the current instruction from the instruction list of the current basic block;

[0017] S205. Determine whether the instruction list of the current basic block is empty. If it is, determine the instruction scheduling and jump to S106; otherwise, jump to S203 to continue traversing the instructions in the instruction list of the current basic block.

[0018] Optionally, the function expression for calculating the functional unit pressure of each instruction in step S201 is:

[0019] ,

[0020] In the above formula, represents the functional unit pressure of the i th instruction in the instruction list , represents the execution cycle of the i th instruction in the instruction list , Indicates the i th instruction in the instruction list, and the number of available functional units.

[0021] Optionally, step S202 includes:

[0022] S301. Determine the status value of each instruction in the instruction list according to the dependency relationship between instructions;

[0023] S302. Determine the priority of each instruction according to the functional unit pressure and status value of each instruction, and the calculation function expression of the priority of each instruction is:

[0024] ,

[0025] In the above formula, represents the priority of the i th instruction in the instruction list, represents the status value of the i th instruction in the instruction list, ω represents the weight value, represents the i th instruction in the instruction list, and

[0026] represents the functional unit pressure of the instruction.

[0027] Optionally, step S301 includes:

[0028] S401. Construct a dependency graph according to the dependency relationship between instructions. The nodes in the dependency graph are the instructions in the source code, the dependency edges represent the dependency relationship between instructions, and the size of the dependency edge is the minimum startup interval between two instructions;

[0029] S402. Traverse the nodes in the dependency graph. For each currently traversed node: if the current node has child nodes, the status value of the instruction corresponding to the current node is the maximum value among the status value of its child nodes and the sum of its dependency edges with the child nodes; otherwise, the status value of the instruction corresponding to the current node is the execution cycle of the instruction corresponding to the current node.

[0030] ,

[0031] In the above formula, represents the actual scheduling length of the current basic block, max represents taking the maximum value, represents the i th instruction in the instruction list, and

[0032] , ,

[0033] Among them, represents the earliest start time of the i-th instruction in the instruction list , represents the execution cycle of the i-th instruction in the instruction list , is the sum of the execution cycles of all instructions in the instruction list; is a binary decision variable used to represent whether the i-th instruction occupies a functional unit and a time slot . If the i-th instruction occupies the functional unit in the time slot , then , otherwise .

[0034] Optionally, determining the lower bound of the scheduling length of the current basic block in step S104 includes:

[0035] S501, establishing the objective function of the total execution cycle of the current basic block shown in the following formula:

[0036] ,

[0037] In the above formula, T represents the total execution cycle of the current basic block, is the lower bound of the scheduling length of the current basic block, represents taking the minimum value, represents taking the maximum value, is the sum of the execution cycles of all instructions in the instruction list, is a binary decision variable used to represent whether the i-th instruction occupies a functional unit and a time slot . If the i-th instruction occupies the functional unit in the time slot , then , otherwise ; represents the execution cycle of the i-th instruction in the instruction list;

[0038] S502, setting the following constraint conditions for the objective function:

[0039] ,

[0040] ,

[0041] ,

[0042] ,

[0043] In the above formula, is the total number of functional units, is the instruction set of the current basic block, is a binary decision variable coefficient of, coefficient is a binary decision variable: if the functional unit is assigned to the instruction , then , otherwise ; is the set of time slots, represents the set of functional units, respectively represent the i-th and the l -th instructions in the instruction list, represents the instruction with a dependency relationship and instruction dependency edge between, the value of which represents the instruction and instruction minimum start interval between;

[0044] S503. For the objective function and its constraint conditions, a solver is used to find the optimal solution to obtain the lower bound of the scheduling length of the current basic block.

[0045] Optionally, step S103 further includes obtaining a scheduling scheme based on dynamic programming instruction scheduling when the scale of the basic block is less than or equal to the preset threshold k:

[0046] S601. Establish the state transition equation shown below:

[0047] ,

[0048] In the above formula, represents the start time of the i-th instruction in the instruction list when occupying the -th functional unit , and the start time starts from 0; represents the -th functional unit of the instruction , and its value range is [0, m - 1], where m is the number of functional units; represents taking the minimum value, represents taking the maximum value; represents the k-th successor instruction of the instruction ​ The start time when occupying the th functional unit; Indicates that the instruction occupies the th functional unit; n is the total number of successor instructions of the instruction ; Indicates the dependency edge between the instruction with a dependency relationship and its successor instruction , and its value represents the minimum start interval between the instruction and its successor instruction ; is the number of successor instructions of the instruction , is the number of functional units of the instruction ; The boundary condition of the state transition equation is: when the instruction has no successor instruction, its start time is 0; and the state transition equation satisfies the following constraint condition: the instruction with a dependency relationship and the instruction do not occupy the same functional unit in any time slot;

[0049] S602, traverse all basic blocks of the program, and for each currently obtained basic block, traverse all instructions in the current basic block, allocate time slots and functional units for the currently obtained instruction based on the state transition equation until the instruction scheduling of all instructions in the current basic block is completed, and finally complete the instruction scheduling of all basic blocks.

[0050] In addition, the present invention also provides a quantifiable instruction scheduling system for SIMD and VLIW architectures, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the quantifiable instruction scheduling method for SIMD and VLIW architectures.

[0051] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is used to be programmed or configured by a microprocessor to execute the quantifiable instruction scheduling method for SIMD and VLIW architectures.

[0052] Compared with the prior art, the present invention mainly has the following advantages:

[0053] ​1. In view of the strategy of the traditional heuristic scheduling in the industry to separately handle the time slot and functional unit allocation problems, in order to further improve the instruction scheduling efficiency and quantitatively evaluate the scheduling efficiency, the present invention includes parsing the source code of the program to determine the dependency relationship and execution cycle between instructions; traversing the source code of the program to determine the scale of the basic block; when the scale of the basic block is greater than the preset threshold k, performing instruction scheduling with functional unit pressure perception according to the dependency relationship and execution cycle between instructions to obtain a scheduling scheme. The present invention can provide a suitable scheduling strategy for instruction scheduling problems of a specific scale, combine the allocation problems of time slots and functional units from a global perspective during the scheduling process, improve the instruction scheduling efficiency, and solve the problem that the heuristic scheduling algorithms commonly used by existing mainstream compilers cannot perform quantitative analysis and the results are difficult to reach the optimal.

[0054] 2. The present invention includes calculating the scheduling length of the scheduling scheme, determining the lower bound of the scheduling length of the current basic block and calculating the scheduling efficiency of the current basic block, which can realize the quantitative calculation of the scheduling efficiency for SIMD and VLIW architecture instruction scheduling, so as to facilitate the comparison and selection of different scheduling schemes, further improve the instruction scheduling efficiency on the basis of traditional heuristic scheduling, and at the same time provide accurate efficiency values for users. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the basic process of the method in the embodiment of the present invention.

[0056] Figure 2 It is a schematic diagram of instruction scheduling with functional unit pressure perception in the embodiment of the present invention.

[0057] Figure 3 It is a schematic diagram of instruction scheduling based on dynamic programming in the embodiment of the present invention.

[0058] Figure 4 It is a schematic diagram of the dependency relationship graph in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] The core of the quantifiable instruction scheduling method for SIMD and VLIW architectures of the present invention is to provide a quantifiable instruction scheduling mathematical model and an improved instruction scheduling method, which can further improve the scheduling efficiency on the basis of the mainstream heuristic algorithm, and at the same time can calculate the lower bound of the scheduling length of the target program according to the mathematical model, so as to further analyze the accurate efficiency of the scheduling algorithm. In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0060] See Figure 1 , the quantifiable instruction scheduling method for SIMD and VLIW architectures in this embodiment includes:

[0061] S101, Parse the instructions for the source code of the program (see Figure 1 , named source_code.sa in this embodiment), determine the dependency relationship and execution cycle between instructions;

[0062] S102, Traverse the basic blocks in the source code of the program to determine the scale (number of instructions) of the basic blocks;

[0063] S103, When the scale of the basic block is greater than the preset threshold k, perform instruction scheduling for function unit pressure perception according to the dependency relationship and execution cycle between instructions to obtain a scheduling plan (see Figure 1 , named scheduling_plan.sa in this embodiment);

[0064] S104, Calculate the actual scheduling length of the current basic block scheduling plan and determine the lower bound of the scheduling length of the current basic block;

[0065] S105, Divide the lower bound of the scheduling length by the actual scheduling length to obtain the scheduling efficiency of the current basic block.

[0066] It should be noted that the preset threshold k and the comparison method can select the required values according to actual needs. For example, in this embodiment, the preset threshold k = 500 is selected, and the comparison method is "greater than", that is: the basic blocks with a scale greater than 500 in the basic block are regarded as large-scale problems, otherwise they are regarded as small-scale problems. For large-scale problems, perform instruction scheduling for function unit pressure perception according to the dependency relationship and execution cycle between instructions to obtain a scheduling plan.

[0067] As Figure 2 shown, the instruction scheduling for function unit pressure perception in step S103 includes:

[0068] S201, Calculate the function unit pressure of each instruction in the current basic block according to the execution cycle of the instruction;

[0069] S202, Determine the priority of each instruction according to the function unit pressure and construct an instruction list according to the priority;

[0070] S203, Traverse and take out the instruction with the highest priority from the instruction list of the current basic block as the current instruction;

[0071] S204, Allocate a time slot and a function unit for the current instruction and pop the current instruction from the instruction list of the current basic block;

[0072] S205, Judge the instruction list of the current basic block ( Figure 2Determine whether the instruction list (abbreviated as list in Chinese) is empty. If it is, determine the instruction scheduling and jump to S106; otherwise, jump to S203 to continue traversing the instructions in the instruction list of the current basic block.

[0073] In this embodiment, the function expression for calculating the functional unit pressure of each instruction in the current basic block in step S201 is:

[0074] ,

[0075] In the above formula, represents the functional unit pressure of the i th instruction in the instruction list, represents the execution cycle of the i th instruction in the instruction list, represents the number of available functional units of the i th instruction in the instruction list.

[0076] In this embodiment, step S202 includes:

[0077] S301, determine the status value of each instruction in the instruction list according to the dependency relationship between instructions;

[0078] S302, determine the priority of each instruction according to the functional unit pressure and status value of each instruction, and the calculation function expression of the priority of each instruction is:

[0079] ,

[0080] In the above formula, represents the priority of the i th instruction in the instruction list, represents the status value of the i th instruction in the instruction list, ω represents the weight value, represents the functional unit pressure of the i th instruction in the instruction list.

[0081] In this embodiment, step S301 includes:

[0082] S401, construct a dependency graph according to the dependency relationship between instructions. The nodes in the dependency graph are the instructions in the source code, the dependency edges represent the dependency relationship between instructions, and the size of the dependency edge is the minimum start interval between two instructions; Figure 4 The following shows an example of the dependency graph constructed according to the dependency relationship between instructions in this embodiment, where , , respectively represent the dependency edges between instructions to , , . There are two cases for calculating the status values of each instruction: If the instruction has child nodes, taking as an example, the priority status value of this instruction is the maximum value among the sum of its dependency edge with the child node and the status value of the child node, that is , where and respectively represent the status values of instructions and ; If the instruction has no child nodes, taking as an example, the priority status value of this instruction is its execution cycle, that is .

[0083] S402. Traverse the nodes in the dependency graph. For each currently traversed node: If the current node has child nodes, the status value of the instruction corresponding to the current node is the maximum value among the status value of its child node and the sum of its dependency edge with the child node; otherwise, the status value of the instruction corresponding to the current node is the execution cycle of the instruction corresponding to the current node.

[0084] In this embodiment, the functional expression for calculating the actual scheduling length of the scheduling scheme in step S104 is:

[0085] ,

[0086] In the above formula, represents the actual scheduling length of the current basic block, max represents taking the maximum value, represents the effective time of the i th instruction in the instruction list, and there is:

[0087] , ,

[0088] where represents the earliest start time of the th instruction in the instruction list, represents the execution cycle of the th instruction is the sum of the execution cycles of all instructions in the instruction list; is a binary decision variable, used to represent the situation where the th instruction occupies the functional unit and the time slot Occupies a functional unit , then , otherwise . Among them, the sum of the execution cycles of all instructions in the instruction list The calculation function expression is:[[]]

[0089] ,

[0090] In the above formula, Is the execution cycle set of the instruction list.[[]]

[0091] In this embodiment, determining the lower bound of the scheduling length of the current basic block in step S104 includes:[[]]

[0092] S501, establish the objective function of the total execution cycle of the current basic block shown in the following formula:[[]]

[0093] ,

[0094] In the above formula, T Represents the total execution cycle of the current basic block, Is the lower bound of the scheduling length of the current basic block, Represents taking the minimum value, Represents taking the maximum value, Is the sum of the execution cycles of all instructions in the instruction list, Is a binary decision variable used to represent the i-th instruction Occupying the functional unit And time slot If the i-th instruction Occupies the functional unit in the time slot , then , otherwise ; ; Represents the i-th instruction in the instruction list Execution cycle of;

[0095] S502, set the following constraint conditions for the objective function:[[]]

[0096] ,

[0097] ,

[0098] ,

[0099] ,

[0100] In the above formula, Is the total number of functional units, is the instruction set of the current basic block, is the coefficient of the binary decision variable . The coefficient is the binary decision variable: if the functional unit is assigned to the instruction , then , otherwise ; is the set of time slots, represents the set of functional units, respectively represent the i-th and the l -th instructions in the instruction list, represents the instruction and the instruction with a dependency edge between them, and its value represents the minimum start interval between the instruction and the instruction ;

[0101] There are hardware resource limitations in the DSP chip: the number of registers is limited, different instructions need to be executed on specific functional units, etc. Therefore, corresponding constraint conditions need to be set for the objective function. The first constraint condition is used to ensure that each instruction in the program is completed and executed to ensure the complete operation of the entire program; since each instruction has a corresponding executable functional unit, the second constraint condition is used to ensure that the instruction is executed on the correct functional unit; the third constraint condition is used to ensure that at most one instruction can be allocated to the corresponding position of each time slot and functional unit, so as to avoid conflicts in the use of hardware resources; for the instructions with dependency relationships in the program, the fourth constraint condition is used to ensure that the instruction on the child node takes effect after the instruction on the parent node, so as to meet the logical correctness in the program execution process;

[0102] S503. For the objective function and its constraint conditions, a solver is used to find the optimal solution to obtain the lower bound of the scheduling length of the basic block. For example, in this embodiment, the GUROBI solver is used to calculate the optimal solution, that is, the lower bound of the scheduling length of the current basic block.

[0103] To determine the lower bound of the scheduling length of the current basic block, this embodiment provides a mathematical model (the objective function of the total execution cycle) that can be used for quantitative analysis of the scheduling scheme. The scheduling scheme is actually a re-arranged instruction sequence. An important criterion for evaluating the scheduling performance of the compiler is the scheduling length, and the scheduling length is the total length of the time slots occupied by the instructions. Therefore, integer linear programming can be used to mathematically model the instruction scheduling problem. Assume that there are instructions in the target basic block of the source program, and all instructions are represented by the set ; the total number of functional units of the processor is , and all functional units are represented by the set Indicates that the current basic block has a total length of On the time series, the time series is represented by a set Indicates; related to the specific instruction set architecture, Each instruction has its own fixed execution cycle, and the execution cycles corresponding to all instructions are represented by a set Indicates; for instructions , which gives its earliest start time during the compiler's parsing phase and effective time The earliest start time provides the starting point for instruction time slot allocation, reflecting the dependencies between instructions and hardware resource limitations. VLIW architecture processors execute programs according to the order in which instruction packets are issued. Due to instruction parallelism, the instruction issuance order of the assembler and the source program may differ. However, to ensure program correctness, the instruction execution order of the assembler must remain consistent with that of the source program. The instruction execution time can be used to determine whether the instruction and program have been executed.

[0104] See also Figure 1 As an optional implementation, step S103 further includes obtaining a scheduling solution based on instruction scheduling using dynamic programming when the size of the basic block is less than or equal to a preset threshold k (small-scale program):

[0105] S601, establish the state transition equation shown below:

[0106] ,

[0107] In the above formula, Indicates the i-th instruction in the instruction list In the occupation Functional units The startup time starts from 0; Indicates instructions No. Functional units, the value range is [0,m-1], m is the number of functional units; Indicates taking the minimum value, Indicates taking the maximum value; Indicates instructions The kth successor instruction of Occupy The startup time of the functional unit; Indicates instructions Occupy functional units; n is the instruction The total number of subsequent instructions; Instructions that indicate dependencies and its subsequent instructions The dependency edge between them, whose value represents the instruction The minimum startup interval with its successor instruction ; For the instruction the number of successor instructions, For the instruction the number of functional units; the boundary condition of the state transition equation is: when the instruction has no successor instruction, its startup time is 0; and the state transition equation satisfies the following constraint conditions: instructions with a dependency relationship and the instruction do not occupy the same functional unit in any time slot;

[0108] Among them, the boundary condition of the state transition equation can be expressed as:

[0109] ,

[0110] That is, when the instruction has no successor instruction, its startup time when occupying the th functional unit is 0. is 0.

[0111] Among them, the constraint condition of the state transition equation can be expressed as:

[0112] ,

[0113] In the above formula, represents the functional unit occupied by the instruction in the time slot t, represents the functional unit occupied by the instruction in the time slot t, that is, the instructions with a dependency relationship and the instruction do not occupy the same functional unit in any time slot.

[0114] S602, traverse all basic blocks of the program, and for each currently traversed basic block, traverse all instructions in the current basic block, allocate time slots and functional units for the currently traversed instruction based on the state transition equation until the instruction scheduling of all instructions in the current basic block is completed, and finally complete the instruction scheduling of all basic blocks. The state transition equation directly allocates time slots and functional units for instructions using the dependency relationship between instructions and the hardware resource constraint conditions. When the situation of all instructions in the instruction list occupying time slots and functional units has been determined, the instruction scheduling work of the current basic block is completed, thereby determining the final scheduling scheme.

[0115] Finally, divide the lower bound of the scheduling length by the actual scheduling length through step S105 to obtain the scheduling efficiency of the current basic block, which can be expressed in the form of a function expression as:

[0116] ,

[0117] In summary, current mainstream compilers (such as LLVM) widely adopt heuristic algorithms for instruction scheduling. In this process, time slot allocation and functional unit allocation are separately carried out from a local perspective. Traditional heuristic algorithms are difficult to achieve optimality and cannot accurately calculate the scheduling efficiency. To further improve the efficiency of instruction scheduling, the method of this embodiment draws on the ideas of traditional heuristic algorithms and dynamic programming respectively, provides corresponding scheduling strategies for scheduling problems of different scales, aiming to further improve the instruction scheduling efficiency and ensure that the time cost is within an acceptable range. In addition, this method also solves the problem of quantitative analysis of instruction scheduling algorithms. Compared with traditional heuristic algorithms, the method of this embodiment can further improve the scheduling efficiency.

[0118] In addition, this embodiment also provides a quantifiable instruction scheduling system for SIMD and VLIW architectures, including a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the quantifiable instruction scheduling method for SIMD and VLIW architectures. In addition, this embodiment also provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be programmed or configured by a microprocessor to execute the quantifiable instruction scheduling method for SIMD and VLIW architectures.

[0119] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for realizing in the process Figure 1 one process or multiple processes and / or blocks Figure 1Apparatus for the functions specified in one or more boxes. These computer program instructions can also be stored in a computer-readable memory capable of guiding a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction apparatus, and the instruction apparatus implements the process Figure 1 One process or a plurality of processes and / or boxes Figure 1 Apparatus for the functions specified in one or more boxes. These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide for implementing the process Figure 1 One process or a plurality of processes and / or boxes Figure 1 Steps for the functions specified in one or more boxes.

[0120] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A quantifiable instruction scheduling method for SIMD and VLIW architectures, characterized in that Including: S101, Parse the instructions in the source code of the program to determine the dependency relationship and execution cycle between instructions; S102, Traverse the basic blocks in the source code of the program to determine the scale of the basic blocks; S103, When the scale of the basic block is greater than the preset threshold k, perform instruction scheduling for functional unit pressure perception according to the dependency relationship and execution cycle between instructions to obtain a scheduling scheme; S104, Calculate the actual scheduling length of the current basic block scheduling scheme and determine the lower bound of the scheduling length of the current basic block; S105, Divide the lower bound of the scheduling length by the actual scheduling length to obtain the scheduling efficiency of the current basic block; The instruction scheduling for functional unit pressure perception in step S103 includes: S201, Calculate the functional unit pressure of each instruction in the current basic block according to the execution cycle of the instruction; S202, Determine the priority of each instruction according to the functional unit pressure and construct an instruction list according to the priority; S203, Traverse and take out the instruction with the highest priority from the instruction list of the current basic block as the current instruction; S204, Allocate a time slot and a functional unit for the current instruction and pop the current instruction from the instruction list of the current basic block; S205, Determine whether the instruction list of the current basic block is empty. If it is established, it is determined that the instruction scheduling is completed and jump to S106; otherwise, jump to S203 to continue traversing the instructions in the instruction list of the current basic block; The function expression for calculating the functional unit pressure of each instruction in the current basic block in step S201 is: ， In the above formula, represents the functional unit pressure of the i th instruction in the instruction list, represents the execution cycle of the i th instruction in the instruction list, represents the number of available functional units of the i th instruction in the instruction list.

2. The instruction scheduling method quantifiable for SIMD and VLIW architectures according to claim 1, wherein Step S202 includes: S301, Determine the status value of each instruction in the instruction list according to the dependency relationship between instructions; S302, Determine the priority of each instruction according to the functional unit pressure and status value of each instruction, and the function expression for calculating the priority of each instruction is: ， In the above formula, represents the priority of the i th instruction in the instruction list. represents the status value of the i th instruction in the instruction list. ω represents the weight value. represents the functional unit pressure of the i th instruction in the instruction list.

3. The instruction scheduling method quantifiable for SIMD and VLIW architectures according to claim 2, wherein Step S301 includes: S401, Construct a dependency graph according to the dependency relationship between instructions. The nodes in the dependency graph are the instructions in the source code, the dependency edges represent the dependency relationship between instructions, and the size of the dependency edge is the minimum start interval between two instructions; S402, Traverse the nodes in the dependency graph. For each traversed current node: if the current node has child nodes, the status value of the instruction corresponding to the current node is the maximum value among the status value of its child nodes and the sum of its dependency edges with the child nodes; otherwise, the status value of the instruction corresponding to the current node is the execution cycle of the instruction corresponding to the current node.

4. The instruction scheduling method quantifiable for SIMD and VLIW architectures according to claim 1, wherein The function expression for calculating the actual scheduling length of the scheduling scheme in step S104 is: ， In the above formula, T represents the actual scheduling length of the current basic block, and max represents taking the maximum value. represents the i th instruction in the instruction list, and there is: ， ， Among them, represents the earliest start time of the i-th instruction in the instruction list, and represents the execution cycle of the i-th instruction in the instruction list, where is the sum of the execution cycles of all instructions in the instruction list; is a binary decision variable used to represent whether the i-th instruction occupies a functional unit and a time slot . If the i-th instruction occupies the functional unit in the time slot , then otherwise .

5. The instruction scheduling method quantifiable for SIMD and VLIW architectures according to claim 1, characterized in that Determining the lower bound of the scheduling length of the current basic block in step S104 includes: S501, Establish the objective function of the total execution cycle of the current basic block shown in the following formula: ， In the above formula, T represents the total execution cycles of the current basic block, is the lower bound of the scheduling length of the current basic block, represents taking the minimum value, represents taking the maximum value, is the sum of the execution cycles of all instructions in the instruction list, is a binary decision variable used to represent whether the i-th instruction occupies a functional unit and a time slot . If the i-th instruction occupies the functional unit in the time slot , then , otherwise ; represents the execution cycle of the i-th instruction in the instruction list; S502, Set the following constraint conditions for the objective function: ， ， ， ， In the above formula, is the total number of functional units, is the instruction set of the current basic block, is the binary decision variable 's coefficient. The coefficient is the binary decision variable: if the functional unit is assigned to the instruction , then , otherwise ; is the set of time slots, represents the set of functional units, respectively represent the i-th and the l -th instructions in the instruction list, represents the dependency edge between the instructions and the instruction . Its value represents the minimum start interval between the instructions [[ID=...]]and the instruction ; S503, For the objective function and its constraint conditions, use a solver to find the optimal solution to obtain the lower bound of the scheduling length of the current basic block.

6. The instruction scheduling method quantifiable for SIMD and VLIW architectures according to claim 1, wherein Step S103 also includes that when the scale of the basic block is less than or equal to the preset threshold k, an instruction scheduling based on dynamic programming is used to obtain a scheduling scheme: S601, Establish the state transition equation shown in the following formula: ， In the above formula, represents the i-th instruction in the instruction list at the start time when occupying the th functional unit The start time starts from 0; represents the th functional unit of the instruction, and its value range is [0, m - 1], where m is the number of functional units; represents taking the minimum value, represents taking the maximum value; represents the k-th successor instruction of the instruction at the start time when occupying the th functional unit; represents the instruction occupying the th functional unit; n is the total number of successor instructions of the instruction; represents the dependency edge between the instruction with a dependency relationship and its successor instruction The value represents the minimum start interval between the instruction and its successor instruction ; is the number of successor instructions of the instruction, is the number of functional units of the instruction; The boundary condition of the state transition equation is: when the instruction has no successor instruction, its start time is 0; and the state transition equation satisfies the following constraint condition: the instruction with a dependency relationship and the instruction do not occupy the same functional unit in any time slot; S602, traverse all basic blocks of the program. For each currently obtained basic block during traversal, traverse all instructions in the current basic block, and allocate time slots and functional units for the currently obtained instruction based on the state transition equation until the instruction scheduling of all instructions in the current basic block is completed, and finally complete the instruction scheduling of all basic blocks.

7. A quantifiable instruction scheduling system for SIMD and VLIW architectures, comprising a microprocessor and a memory connected to each other, characterized in that, The microprocessor is programmed or configured to execute the instruction scheduling method quantifiable for SIMD and VLIW architectures according to any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to be programmed or configured by a microprocessor to execute the instruction scheduling method quantifiable for SIMD and VLIW architectures according to any one of claims 1 to 6.

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