Power supply circuit and display device comprising a power supply circuit

Abstract

The present disclosure relates to a power supply circuit and a display device including the same. The power supply circuit includes a gate driving circuit configured to supply a gate signal to a plurality of gate lines, a first power supply circuit configured to supply a first initialization voltage having a voltage level between a first voltage level and a second voltage level to a plurality of first initialization power supply lines, the first initialization voltage having the first voltage level in a first period, a third voltage level between the first voltage level and the second voltage level in a second period, and the second voltage level in a third period, and a second power supply circuit configured to supply a driving voltage to a plurality of pixel driving power supply lines among a plurality of power supply lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0169468, filed on November 30, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to power supply circuits and display devices including power supply circuits. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is constantly increasing. To meet this demand, various types of display devices, such as liquid crystal displays (LCDs) and electroluminescent displays (ELDs), have been developed and are in use.

[0005] ELD devices include quantum dot (QD) light-emitting display devices, inorganic light-emitting display devices, and organic light-emitting display devices.

[0006] Among these display devices, ELD devices are characterized by short response time, wide viewing angle, and excellent color gamut. Furthermore, ELD devices have the advantage of being able to be implemented in thin packages or with thin structures.

[0007] Furthermore, since ELD devices display images by using light emitted from a driving current, the amount of driving current is small, or the driving current does not flow at low grayscale or black-grayscale levels. Therefore, ELD devices have advantages such as high contrast at low brightness and excellent image quality.

[0008] In an ELD device, a driving current can be made to flow through the pixels included in the LED device by the voltage applied to the driving transistor, and the amount of driving current can be determined to correspond to the data signal. If the voltage applied to the pixel is higher than a predefined value, the amount of driving current flowing through the pixel may not correspond to the data signal. In particular, this problem may increasingly occur when displaying images at low grayscale through pixels, and therefore, ELD devices may have the disadvantage of producing degraded image quality.

[0009] In addition, challenges have recently emerged in reducing the power consumption of electronic devices or equipment due to issues such as environmental protection and resource consumption. Summary of the Invention

[0010] To address this problem, embodiments of this disclosure provide a power supply circuit or apparatus capable of reducing or preventing image quality degradation, and a display device including the power supply circuit or apparatus.

[0011] Embodiments of this disclosure provide a power supply circuit or device capable of reducing power consumption, and a display device including the power supply circuit or device.

[0012] In one embodiment, a display device includes: a display panel including a plurality of gate lines, a plurality of data lines, a plurality of first initialization power lines, a plurality of power lines, and a plurality of pixels connected to the plurality of gate lines, the plurality of data lines, the plurality of first initialization power lines, and the plurality of power lines, the plurality of pixels being configured to emit light during a light-emitting period of the display device; a data driving circuit configured to supply data signals to the plurality of data lines; a gate driving circuit configured to supply gate signals to the plurality of gate lines; a first power supply circuit configured to supply a first initialization voltage having a voltage level varying between a first voltage level and a second voltage level to the plurality of first initialization power lines; and a second power supply circuit configured to drive the plurality of pixels among the plurality of power lines. A power line supplies a pixel driving voltage, wherein at least one of the plurality of pixels includes: a driving transistor for causing a driving current to flow from a second node to a third node in response to a voltage applied to a first node corresponding to a voltage of a data signal; and a light-emitting element for emitting light in response to the driving current, wherein a voltage corresponding to a data signal is applied to the first node when the light-emitting element does not emit light before an emitting period, and then the second node and the third node are initialized using a first initialization voltage, the first initialization voltage having a first voltage level in a first period, a third voltage level between the first voltage level and the second voltage level in a second period after the first period, and a second voltage level in the third period after the second period.

[0013] In one embodiment, a power supply device includes: a plurality of stages configured to generate a first initialization voltage and a carry signal sequentially output by each of the plurality of stages, wherein the first initialization voltage output from each of the plurality of stages has a voltage level between a first voltage level and a second voltage level, and has a first voltage level in a first time period, a third voltage level between the first voltage level and the second voltage level in a second time period after the first time period, and a second voltage level in a third time period after the second time period.

[0014] In one embodiment, a pixel includes: a driving transistor including a first node, a second node, and a third node, the second node being configured to be electrically connected between a data line to which a data signal is applied and a pixel driving power line to which a pixel driving voltage is applied, the driving transistor being configured to cause a driving current to flow from the second node to the third node in response to a data signal applied to the first node; and a light-emitting element electrically connected to the third node of the driving transistor, the light-emitting element being configured to emit light in response to the driving current, wherein after a data signal is applied to the first node of the driving transistor, a first initialization voltage is applied to the second and third nodes of the driving transistor to initialize the second and third nodes, while the light-emitting element does not emit light before a period of pixel emission, the first initialization voltage having a first voltage level in the first period, a third voltage level between the first and second voltage levels in the second period after the first period, and a second voltage level in the third period after the second period.

[0015] According to embodiments of this disclosure, a power supply circuit or apparatus capable of reducing image quality degradation and a display device including the power supply circuit or apparatus are provided.

[0016] According to embodiments of this disclosure, a power supply circuit or device capable of reducing power consumption is provided, as well as a display device including the power supply circuit or device. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0018] Figure 1A , Figure 1B and Figure 1C This is a plan view showing a display device according to an embodiment of the present disclosure;

[0019] Figure 2 A system configuration of a display device according to an embodiment of the present disclosure is shown;

[0020] Figure 3 The equivalent circuit of a pixel in a display panel according to an embodiment of the present disclosure is shown;

[0021] Figure 4 The arrangement of pixels in three regions included in the display area of ​​a display panel according to an embodiment of the present disclosure is shown;

[0022] Figure 5AThe arrangement of signal lines in each of the first optical region and the normal region of a display panel according to an embodiment of the present disclosure is shown;

[0023] Figure 5B The arrangement of signal lines in each of the second optical region and the normal region of a display panel according to an embodiment of the present disclosure is shown;

[0024] Figure 6 and Figure 7 It is a cross-sectional view of each of the first optical region, the second optical region, and the normal region included in the display area of ​​a display panel according to various aspects of the embodiments of the present disclosure;

[0025] Figure 8 This is a cross-sectional view of the edge of a display panel according to an embodiment of the present disclosure;

[0026] Figure 9 A system configuration of a display device according to an embodiment of the present disclosure is shown;

[0027] Figure 10 The settings according to embodiments of this disclosure are shown. Figure 9 The gate drive circuit and the first power supply circuit in the display panel shown;

[0028] Figure 11 The embodiments according to this disclosure are shown. Figure 9 The circuit diagram of the pixels used in the display device shown;

[0029] Figure 12 This illustrates an implementation method according to the present disclosure. Figure 11 The timing diagram shows the operation of the pixels shown.

[0030] Figure 13 The embodiments according to this disclosure are shown. Figure 9 The configuration of the first power supply circuit shown;

[0031] Figure 14 and Figure 15 This is an implementation method based on the content of this disclosure. Figure 13 The circuit diagram of the nth level shown; and

[0032] Figure 16 This illustrates an implementation method according to the present disclosure. Figure 14 or Figure 15 The timing diagram of the operations of the stage shown is shown. Detailed Implementation

[0033] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar components even when the same or similar components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such description may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components unless used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0034] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0035] When referring to a first element as "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be understood that not only can the first element be "directly connected or coupled to" or "directly in contact with or overlap" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other via a fourth element. Here, a second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0036] When time-related terms such as “after,” “follow,” “next,” “before,” etc., are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation, unless the terms “directly” or “immediately after” are used together.

[0037] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of an element or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0038] Figure 1A , Figure 1Band Figure 1C This is a plan view illustrating an example display device according to an embodiment of the present disclosure.

[0039] Reference Figure 1A , Figure 1B and Figure 1C The display device 100 according to the embodiments of the present disclosure may include a display panel 110 for displaying images and one or more optical electronic devices (11, 12).

[0040] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images.

[0041] Multiple pixels can be arranged in the display area DA, and several types of signal lines for driving the multiple pixels can be arranged in the display area DA.

[0042] The non-display area NDA can refer to the area outside the display area DA. Various types of signal lines can be arranged in the non-display area NDA, and various types of drive circuits can be connected to these signal lines. At least a portion of the non-display area NDA can be bent so that it is not visible from the front of the display panel, or it can be covered by a cover (not shown) of the display panel 110 or the display device 100. The non-display area NDA can also be referred to as a border or border area.

[0043] Reference Figure 1A , Figure 1B and Figure 1C In the display device 100 according to the embodiments of the present disclosure, one or more optical electronic devices (11, 12) may be located below or in the lower part of the display panel 110 (opposite to the viewing surface of the display panel 110).

[0044] Light can enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optical electronic devices (11, 12) located below or on the lower part of the display panel 110 (opposite side of the viewing surface).

[0045] One or more optical electronic devices (11, 12) can receive or detect light transmitted through the display panel 110 and perform predefined functions based on the received light. For example, one or more optical electronic devices (11, 12) may include an image capturing device such as a camera (image sensor) and / or one or more sensors such as a proximity sensor, an illuminance sensor, etc.

[0046] Reference Figure 1A , Figure 1B and Figure 1CIn some embodiments, the display area DA of the display panel 110 may include one or more optical areas (OA1, OA2) and a normal area NA. The normal area NA is an area that does not overlap with one or more optoelectronic devices (11, 12) and may also be referred to as a non-optical area.

[0047] Reference Figure 1A , Figure 1B and Figure 1C One or more optical regions (OA1, OA2) may be one or more regions that overlap with one or more optoelectronic devices (11, 12).

[0048] according to Figure 1A For example, the display area DA may include a first optical area OA1 and a normal area NA. In some embodiments, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11. Hereinafter, the normal area NA is an area that does not overlap with one or more optoelectronic devices (11, 12) and may also be referred to as a non-optical area or a typical display area.

[0049] according to Figure 1B For example, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA. Figure 1B In the example, at least a portion of the normal region NA may exist between the first optical region OA1 and the second optical region OA2. In some embodiments, at least a portion of the first optical region OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical region OA2 may overlap with the second optoelectronic device 12.

[0050] according to Figure 1C For example, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA. Figure 1C In some examples, a normal region NA may not exist between the first optical region OA1 and the second optical region OA2. For example, the first optical region OA1 and the second optical region OA2 may be in contact with each other. In some embodiments, at least a portion of the first optical region OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical region OA2 may overlap with the second optoelectronic device 12.

[0051] Both image display structures and light transmission structures need to be formed in one or more optical regions (OA1, OA2). In some embodiments, since one or more optical regions (OA1, OA2) are one or more parts of the display area DA, pixels for displaying images need to be provided in one or more optical regions (OA1 and OA2). Furthermore, in order for light to be able to pass through one or more optoelectronic devices (11, 12), light transmission structures need to be formed in one or more optical regions (OA1, OA2).

[0052] According to the above embodiments, although one or more optical electronic devices (11, 12) are required to receive or detect light, one or more optical electronic devices are sometimes located on the back side of the display panel 110 (below or in the lower part of the display panel 110, i.e., on the opposite side of the viewing surface), and thus can receive light transmitted through the display panel 110.

[0053] For example, one or more optoelectronic devices (11, 12) may not be exposed on the front surface (viewing surface) of the display panel 110. Therefore, one or more optoelectronic devices (11, 12) are not visible to the user when the user is looking at the front of the display device 110.

[0054] In one embodiment, the first optical electronic device 11 may be a camera, and the second optical electronic device 12 may be a sensor such as a proximity sensor or an illuminance sensor. For example, the sensor may be an infrared sensor capable of detecting infrared light.

[0055] In another embodiment, the first optical electronic device 11 may be a sensor, and the second optical electronic device 12 may be a camera.

[0056] In the following description, for ease of description, embodiments in which the first optical electronic device 11 is a camera and the second optical electronic device 12 is a sensor such as a proximity sensor, an illumination sensor, an infrared sensor, etc. will be discussed. For example, the camera may be a camera lens, an image sensor, or a unit that includes at least one of a camera lens and an image sensor.

[0057] In an example where the first optical electronic device 11 is a camera, the camera may be located on the back (below or in the lower part) of the display panel 110, and may be a front-facing camera capable of capturing objects or images in the front direction of the display panel 110. Therefore, a user can capture images or objects using a camera that is not visible on the viewing surface when the user views the viewing surface of the display panel 110.

[0058] Although Figures 1A to 1CEach of the display areas DA includes a normal area NA and one or more optical areas (OA1, OA2) that are areas where images can be displayed. However, the normal area NA is an area without light transmission structures, while the one or more optical areas (OA1, OA2) are areas that include light transmission structures.

[0059] Therefore, one or more optical regions (OA1, OA2) may have a transmittance greater than or equal to a predetermined level (e.g., relatively high transmittance), while the normal region NA may have no transmittance or a transmittance less than the predetermined level (e.g., relatively low transmittance).

[0060] For example, one or more optical regions (OA1, OA2) and normal region NA can have different resolutions, pixel arrangements, number of pixels per unit area, electrode structures, line structures, electrode arrangements, line arrangements, etc.

[0061] In one implementation, the number of pixels per unit area in one or more optical regions (OA1, OA2) may be less than the number of pixels per unit area in the normal region NA. For example, the resolution of one or more optical regions (OA1, OA2) may be less than the resolution of the normal region NA. Here, the number of pixels per unit area can be measured using pixels per inch (PPI), which represents the number of pixels per inch, as the unit for measuring resolution.

[0062] In one implementation, Figures 1A to 1C In each of the regions, the number of pixels per unit area in the first optical region OA1 can be less than the number of pixels per unit area in the normal region NA. In one embodiment, in Figure 1B and Figure 1C In each of the first optical regions, the number of pixels per unit area in the second optical region OA2 can be greater than or equal to the number of pixels per unit area in the first optical region OA1.

[0063] exist Figures 1A to 1C In each of these, the first optical region OA1 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. Figures 1B to 1C In each of these regions, the second optical region OA2 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. The first optical region OA1 and the second optical region OA2 can have the same shape or different shapes.

[0064] Reference Figure 1CIn the example where the first optical region OA1 and the second optical region OA2 are in contact with each other, the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes, such as circles, ellipses, quadrilaterals, hexagons, octagons, etc.

[0065] In the following discussion, for ease of description, an embodiment based on each of the first optical region OA1 and the second optical region OA2 having a circular shape will be provided.

[0066] In the text, in an example where a display device 100 according to an embodiment of the present disclosure has a structure in which a first optical electronic device 11, positioned as a camera and covered under or in the lower portion of the display panel 100 rather than exposed to the outside, is a camera, the display device 100 may be referred to as a display (or display device) implementing under-display camera (UDC) technology.

[0067] Since it is not necessary to form a notch or camera hole in the display panel 110 for exposing the camera, the display device 100 according to this configuration can have the advantage of preventing the size of the display area DA from decreasing.

[0068] Since it is not necessary to form a notch or camera hole in the display panel 110 for camera exposure, the display device 100 also has the advantages of reducing the size of the bezel area and increasing design freedom, thereby eliminating such restrictions on design.

[0069] Although in the display device 100 according to the embodiments of the present disclosure, one or more optical electronic devices (11, 12) are covered on the back side (below or in the lower part) of the display panel 110, i.e., hidden from the outside, one or more optical electronic devices (11, 12) need to receive or detect light in order to perform a predefined function properly.

[0070] Furthermore, in the display device 100 according to the embodiments of the present disclosure, although one or more optical electronic devices (11, 12) are covered on the back side (below or in the lower part) of the display panel 110 and positioned to overlap with the display area DA, it is necessary to perform image display normally in one or more optical areas (OA1, OA2) overlapping with one or more optical electronic devices (11, 12) in the display area DA.

[0071] Figure 2 The system configuration of a display device 100 according to an embodiment of the present disclosure is shown.

[0072] Reference Figure 2 The display device 100 may include a display panel 110 and a display driving circuit as a component for displaying images.

[0073] The display driving circuit is a circuit used to drive the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, etc.

[0074] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The non-display area NDA may be an area outside the display area DA and may also be referred to as an edge area or border area. All or part of the non-display area NDA may be an area visible from the front surface of the display device 100, or a bent area that is not visible from the front surface of the display device 100.

[0075] The display panel 110 may include a substrate SUB and a plurality of pixels SP disposed on the substrate SUB. The display panel 110 may also include various types of signal lines for driving the plurality of pixels SP.

[0076] In some embodiments, the display device 100 herein may be a liquid crystal display device or the like, or a self-emissive display device in which light is emitted from the display panel 110 itself. In an example where the display device 100 according to an aspect of this disclosure is a self-emissive display device, each of the plurality of pixels SP may include a light-emitting element.

[0077] In some embodiments, the display device 100 may be an organic light-emitting display device in which an organic light-emitting diode (OLED) is used to realize the light-emitting element. In some embodiments, the display device 100 may be an inorganic light-emitting display device in which an inorganic light-emitting diode based on an inorganic material is used to realize the light-emitting element. In some embodiments, the display device 100 may be a quantum dot display device in which a quantum dot, as a self-emissive semiconductor crystal, is used to realize the light-emitting element.

[0078] The structure of each of the plurality of pixels SP can vary depending on the type of display device 100. In an example where the display device 100 is a self-emissive display device including self-emissive pixels SP, each pixel SP may include a self-emissive light-emitting element, one or more transistors and one or more capacitors.

[0079] The various types of signal lines arranged in the display device 100 may include, for example, multiple data lines DL for carrying data signals (also known as data voltages or image signals), multiple gate lines GL for carrying gate signals (also known as scan signals), etc.

[0080] Multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may extend in a first direction. Each of the multiple gate lines GL may extend in a second direction.

[0081] For example, the first direction can be a column or a vertical direction, and the second direction can be a row or a horizontal direction. In another example, the first direction can be a row direction, and the second direction can be a column direction.

[0082] The data driving circuit 220 is used to drive multiple data lines DL and can supply data signals to the multiple data lines DL. The gate driving circuit 230 is used to drive multiple gate lines GL and can supply gate signals to the multiple gate lines GL.

[0083] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing of multiple data lines DL and multiple gate lines GL.

[0084] The display controller 240 can supply the data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and supply the gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0085] The display controller 240 can receive input image data from the host system 250 and supply image data Data to the data drive circuit 220 based on the input image data.

[0086] The data drive circuit 220 can supply data signals to multiple data lines DL according to the drive timing control of the display controller 240.

[0087] The data drive circuit 220 can receive digital image data Data from the display controller 240, convert the received image data Data into an analog data signal, and supply the obtained analog data signal to multiple data lines DL.

[0088] The gate driving circuit 230 can supply gate signals to multiple gate lines GL according to the timing control of the display controller 240. The gate driving circuit 230 can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage, as well as various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to multiple gate lines GL.

[0089] In some implementations, the data drive circuit 220 may be connected to the display panel 110 in a tape-on-absence (TAB) type, or to a conductive pad such as a bonding pad of the display panel 110 in a chip-on-glass (COG) type or chip-on-panel (COP) type, or to the display panel 110 in a chip-on-film (COF) type.

[0090] In some embodiments, the gate drive circuit 230 may be connected to the display panel 110 in a tape-on-absence (TAB) type, or to conductive pads such as bonding pads of the display panel 110 in a chip-on-glass (COG) or chip-on-panel (COP) type, or to the display panel 110 in a chip-on-film (COF) type. In another embodiment, the gate drive circuit 230 may be disposed in the non-display area NDA of the display panel 110 in a gate-in-panel (GIP) type. The gate drive circuit 230 may be disposed on or above the substrate, or connected to the substrate. That is, in the case of the GIP type, the gate drive circuit 230 may be disposed in the non-display area NDA of the substrate. In the cases of chip-on-glass (COG), chip-on-film (COF), etc., the gate drive circuit 230 may be connected to the substrate.

[0091] At least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be configured not to overlap with the pixel SP, or configured to overlap with one or more or all of the pixel SP.

[0092] The data driving circuit 220 may also be located on only one side or a portion (e.g., the top edge or the bottom edge) of the display panel 110. In some embodiments, depending on the driving scheme, panel design, etc., the data driving circuit 220 may be located in both sides or two portions (e.g., the top edge and the bottom edge) of the display panel 110, or in at least two of the four sides or four portions (e.g., the top edge, the bottom edge, the left edge, and the right edge) of the display panel 110.

[0093] The gate driving circuit 230 may be located in only one side or one portion (e.g., the left edge or the right edge) of the display panel 110. In some embodiments, depending on the driving scheme, panel design, etc., the gate driving circuit 230 may be connected to both sides or two portions (e.g., the left edge and the right edge) of the panel 110, or connected to at least two of the four sides or four portions of the panel 110 (e.g., the top edge, the bottom edge, the left edge, and the right edge).

[0094] The display controller 240 can be implemented in a component separate from the data drive circuit 220, or it can be integrated with the data drive circuit 220 and thus implemented in an integrated circuit.

[0095] The display controller 240 may be a timing controller used in typical display technologies, or a controller or control device capable of additionally performing control functions beyond those of a typical timing controller. In some embodiments, the display controller 240 may be a controller or control device different from the timing controller, or may be a circuit or component included in a controller or control device. The display controller 240 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0096] The display controller 240 can be mounted on a printed circuit board, flexible printed circuit, etc., and is electrically connected to the gate drive circuit 220 and the data drive circuit 230 through the printed circuit board, flexible printed circuit, etc.

[0097] The display controller 240 can transmit signals to and receive signals from the data driver circuit 220 via one or more predefined interfaces. In some embodiments, such interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, a Serial Peripheral Interface (SPI), etc.

[0098] In some embodiments, to further provide touch sensing and image display functions, the display device 100 may include at least one touch sensor and a touch sensing circuit, which can detect whether a touch event occurs by a touch object such as a finger or pen, or can detect the corresponding touch position by sensing the touch sensor.

[0099] The touch sensing circuit may include a touch driver circuit 260 that can generate and provide touch sensing data by driving and sensing a touch sensor, a touch controller 270 that can detect the occurrence of a touch event or detect the touch position using touch sensing data, etc.

[0100] The touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to the touch driving circuit 260.

[0101] The touch sensor can be implemented in the touch panel, or in the form of the touch panel, or external to the display panel 110, or internal to the display panel 110. In the example where the touch sensor is implemented in the touch panel or external to the display panel 110 in the form of a touch panel, this type of touch sensor is referred to as an additional type. In the example where an additional type of touch sensor is provided, the touch panel and the display panel 110 can be manufactured and coupled separately during the assembly process. The additional type of touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0102] In an example where the touch sensor is implemented inside the display panel 110, the touch sensor may be positioned above the substrate SUB along with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0103] The touch driving circuit 260 can supply a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0104] Touch sensing circuits can perform touch sensing using self-capacitance sensing or mutual capacitance sensing methods.

[0105] In an example where the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.).

[0106] According to the self-capacitance sensing method, each of the plurality of touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or one or more of the plurality of touch electrodes and sense all or one or more of the plurality of touch electrodes.

[0107] In an example where the touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0108] According to the mutual capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0109] The touch driver circuit 260 and touch controller 270 included in the touch sensing circuit can be implemented in a separate device or a single device. Furthermore, the touch driver circuit 260 and data driver circuit 220 can be implemented in a separate device or a single device.

[0110] The display device 100 may also include a power supply circuit for supplying various types of power to the display driving circuit and / or touch sensing circuit.

[0111] In some embodiments, the display device 100 may be a mobile terminal such as a smartphone, tablet computer, etc., or a monitor, television (TV), etc. Such a device may have various types, sizes, and shapes. The display device 100 according to embodiments of this disclosure is not limited thereto, and includes displays of various types, sizes, and shapes for displaying information or images.

[0112] As mentioned above, for example, Figures 1A to 1C As shown, the display area DA of the display panel 110 may include a normal area NA and one or more optical areas (OA1, OA2).

[0113] The normal region NA and one or more optical regions (OA1, OA2) are areas where images can be displayed. However, the non-optical region is the region where a light transmission structure is not required, and one or more optical regions OA1, OA2 are the regions where a light transmission structure is required.

[0114] As mentioned above Figures 1A to 1C As discussed in the examples, although the display area DA of the display panel 110 may include one or more optical areas (OA1, OA2) in addition to the normal area NA, for ease of description, in the following discussion, it is assumed that the display area DA includes a first optical area, a second optical area (OA1, OA2), and the normal area NA; and the normal area NA of the display area DA includes... Figures 1A to 1C The normal region NA in the display area DA includes the first optical region and the second optical region (OA1, OA2) of the display area DA, respectively. Figures 1A to 1C The first optical region OA1 and Figures 1B to 1C The second optical region OA2 in the image, unless otherwise explicitly stated.

[0115] Figure 3 The equivalent circuit of a pixel SP in a display panel 110 according to an embodiment of the present disclosure is shown.

[0116] Each of the pixels SP in the normal area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA of the display panel 110 may include a light-emitting element ED, a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT for transmitting the data voltage Vdata to the first node N1 of the driving transistor DRT, and a storage capacitor Cst for maintaining the voltage at an approximately constant level during a frame, etc.

[0117] The driving transistor DRT may include a first node N1 to which the data voltage is applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which the pixel driving voltage ELVDD is applied through the driving voltage line DVL. In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0118] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​may be a pixel electrode disposed in each pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each pixel SP. The cathode electrode CE may be a common electrode disposed in multiple pixels SP, and a base voltage ELVSS, such as a low-level voltage, may be applied to the cathode electrode CE.

[0119] For example, the anode electrode AE ​​can be a pixel electrode, and the cathode electrode CE can be a common electrode. In another example, the anode electrode AE ​​can be a common electrode, and the cathode electrode CE can be a pixel electrode. For ease of description, in the following discussion, it is assumed that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode, unless otherwise explicitly stated.

[0120] The light-emitting element (ED) can be, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting element, etc. In an example using an organic light-emitting diode as the light-emitting element (ED), the light-emitting layer (EL) included in the light-emitting element (ED) can include an organic light-emitting layer, which comprises an organic material.

[0121] The scanning transistor SCT can be turned on and off by the scanning signal SCAN, which is applied to the gate signal through the gate line GL, and is electrically connected between the first node N1 of the driving transistor DRT and the data line DL.

[0122] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0123] like Figure 3 As shown, each pixel SP may include two transistors (2T: DRT and SCT) and a capacitor (1C: Cst) (referred to as "2T1C structure"), and in some cases may include one or more transistors or one or more capacitors.

[0124] The storage capacitor Cst can be an external capacitor, rather than an internal capacitor, intentionally designed to be located outside the driving transistor DRT, such as a parasitic capacitor (e.g., Cgs, Cgd), and the storage capacitor Cst can exist between the first node N1 and the second node N2 of the driving transistor DRT.

[0125] Each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or a p-type transistor.

[0126] Since the circuit elements (especially the light-emitting elements ED) in each pixel SP are susceptible to external moisture or oxygen, an encapsulation layer ENCAP can be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit elements (especially the light-emitting elements ED). The encapsulation layer ENCAP can be configured to cover the light-emitting elements ED.

[0127] Figure 4 The arrangement of pixels SP in the three regions (NA, OA1, and OA2) included in the display area DA of a display panel 110 according to an embodiment of the present disclosure is shown.

[0128] Reference Figure 4 Multiple pixels SP can be set in each of the normal area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0129] Multiple pixels SP can include, for example, red pixels that emit red light (red SP), green pixels that emit green light (green SP), and blue pixels that emit blue light (blue SP).

[0130] Therefore, each of the normal region NA, the first optical region OA1, and the second optical region OA2 may include one or more light-emitting regions EA of one or more red pixels (red SP), one or more light-emitting regions EA of one or more green pixels (green SP), and one or more light-emitting regions EA of one or more blue pixels (blue SP).

[0131] Reference Figure 4 The normal region NA may not include light-transmitting structures, but may include the light-emitting region EA which does not have light-transmitting structures.

[0132] However, the first optical region OA1 and the second optical region OA2 include both the light-emitting region EA and the light-transmitting structure.

[0133] Therefore, the first optical region OA1 may include a light-emitting region EA and a first transmission region TA1 (e.g., a light transmission region), and the second optical region OA2 may include a light-emitting region EA and a second transmission region TA2 (e.g., a light transmission region).

[0134] Depending on whether light transmission is permitted, the luminescent region EA and the transmission regions (TA1, TA2) can be different. For example, the luminescent region EA can be a region that does not allow light transmission, while the transmission regions TA1, TA2 can be regions that allow light transmission.

[0135] The luminescent region EA and the transmission regions TA1 and TA2 can also differ depending on whether a specific metal layer CE is included. For example, a cathode electrode CE can be provided in the luminescent region EA, while a cathode electrode CE may not be provided in the transmission regions (TA1 and TA2). Furthermore, a light-shielding layer may be provided in the luminescent region EA, while a light-shielding layer may not be provided in the transmission regions (TA1 and TA2).

[0136] Since the first optical region OA1 includes the first transmission region TA1, and the second optical region OA2 includes the second transmission region TA2, both the first optical region OA1 and the second optical region OA2 are regions through which light can pass.

[0137] In one embodiment, the transmittance of the first optical region OA1 and the transmittance of the second optical region OA2 can be substantially equal.

[0138] For example, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 can have substantially the same shape or size. In another example, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have different shapes or sizes, the ratio of the first transmission region TA1 to the first optical region OA1 and the ratio of the second transmission region TA2 to the second optical region OA2 can be substantially equal.

[0139] In another embodiment, the transmittance of the first optical region OA1 and the transmittance of the second optical region OA2 may be different.

[0140] For example, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 can have different shapes or sizes. In another example, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have substantially the same shape or size, the ratio of the first transmission region TA1 to the first optical region OA1 and the ratio of the second transmission region TA2 to the second optical region OA2 can be different from each other.

[0141] For example, in an example where the first optical electronic device 11 overlapping with the first optical region OA1 is a camera and the second optical electronic device 12 overlapping with the second optical region OA2 is a sensor for detecting images, the camera may require a much larger amount of light than the sensor.

[0142] Therefore, the transmittance of the first optical region OA1 can be greater than that of the second optical region OA2.

[0143] For example, the first transmission region TA1 of the first optical region OA1 can have a larger size than the second transmission region TA2 of the second optical region OA2. In another example, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have substantially the same size, the ratio of the first transmission region TA1 to the first optical region OA1 can be larger than the ratio of the second transmission region TA2 to the second optical region OA2.

[0144] For ease of description, the following discussion is based on an implementation where the transmittance of the first optical region OA1 is greater than that of the second optical region OA2.

[0145] In addition, such as Figure 4 The transmission regions (TA1, TA2) shown can be called transparent regions, and the term transmission can be referred to as transparency.

[0146] Furthermore, in the following discussion, such as Figure 4 As shown, it is assumed that the first optical region OA1 and the second optical region OA2 are located in the upper edge of the display area DA of the display panel 110 and are arranged to be horizontally adjacent to each other, for example, in the direction extending from the upper edge, unless otherwise explicitly stated.

[0147] Reference Figure 4 The horizontal display area with a first optical region OA1 and a second optical region OA2 is referred to as the first horizontal display area HA1, and the other horizontal display area without the first optical region OA1 and the second optical region OA2 is referred to as the second horizontal display area HA2.

[0148] Reference Figure 4 The first horizontal display area HA1 may include a portion of the normal area NA, a first optical area OA1, and a second optical area OA2. The second horizontal display area HA2 may include another portion of the normal area NA that does not include the first optical area OA1 and the second optical area OA2.

[0149] Figure 5A The arrangement of signal lines in each of the first optical region OA1 and normal region NA of a display panel 110 according to an embodiment of the present disclosure is shown, and Figure 5B The arrangement of signal lines in each of the second optical region OA2 and the normal region NA of a display panel 110 according to an embodiment of the present disclosure is shown.

[0150] like Figure 5A and Figure 5B The first horizontal display area HA1 shown is a portion of the first horizontal display area HA1 of the display panel 110, and Figure 5A and Figure 5B The second horizontal display area HA2 is a portion of the second horizontal display area HA2 of the display panel 110.

[0151] Figure 5A The first optical region OA1 shown is a part of the first optical region OA1 of the display panel 110, and Figure 5B The second optical region OA2 shown is a part of the second optical region OA2 of the display panel 110.

[0152] Reference Figure 5A and Figure 5B The first horizontal display area HA1 may include a portion of the normal area NA, a first optical area OA1, and a second optical area OA2. The second horizontal display area HA2 may include another portion of the normal area NA that does not include the first optical area OA1 and the second optical area OA2.

[0153] Various types of horizontal lines HL1, HL2 and various types of vertical lines VLn, VL1, VL2 can be set in the display panel 11.

[0154] In this text, the terms "horizontal" and "vertical" are used to refer to two directions intersecting the display panel. However, it should be noted that the horizontal and vertical directions can change depending on the viewing direction. The horizontal direction can refer to, for example, the direction in which a gate line GL extends, and the vertical direction can refer to, for example, the direction in which a data line DL extends. Therefore, the terms horizontal and vertical are used to represent two directions.

[0155] Reference Figure 5A and Figure 5B The horizontal lines set in the display panel 110 may include a first horizontal line HL1 set in the first horizontal display area HA1 and a second horizontal line HL2 set in the second horizontal display area HA2.

[0156] The horizontal lines provided in the display panel 110 can be gate lines GL. That is, the first horizontal line HL1 and the second horizontal line HL2 can be gate lines GL. The gate lines GL can include various types of gate lines depending on the structure of one or more pixels SP.

[0157] Reference Figure 5A and Figure 5B The vertical lines set in the display panel 110 may include a typical vertical line VLn set only in the normal area NA, a first vertical line VL1 that passes through both the first optical area OA1 and the normal area NA, and a second vertical line VL2 that passes through both the second optical area OA2 and the normal area NA.

[0158] The vertical lines provided in the display panel 110 may include data lines DL, driving voltage lines DVL, etc., and may also include reference voltage lines, initialization voltage lines, etc. That is to say, a typical vertical line VLn, a first vertical line VL1, and a second vertical line VL2 may include data lines DL, driving voltage lines DVL, etc., and may also include reference voltage lines, initialization voltage lines, etc.

[0159] In some implementations, it should be noted that the term "horizontal" in the second horizontal line HL2 may simply mean that the signal is transmitted from the left side to the right side (or from the right side to the left side) of the display panel, and may not mean that the second horizontal line HL2 travels in a straight line only in the direct horizontal direction. For example, in Figure 5A and Figure 5B In the diagram, although the second horizontal lines HL2 are shown as straight lines, one or more of the second horizontal lines HL2 may include one or more bends or folds that differ from their configuration. Similarly, one or more of the first horizontal lines HL1 may also include one or more bends or folds.

[0160] In some implementations, it should be noted that the term "vertical" in a typical vertical line VLn may mean only that the signal is transmitted from the top to the bottom (or from the bottom to the top) of the display panel, and not that the typical vertical line VLn travels in a straight line only in the directly vertical direction. For example, in Figure 5A and Figure 5B In the diagram, although typical vertical lines VLn are shown as straight lines, one or more of the typical vertical lines VLn may include one or more bends or folds that differ from their configuration. Similarly, one or more of the first vertical lines VL1 and one or more of the second vertical lines VL2 may also include one or more bends or folds.

[0161] Reference Figure 5A The first optical region OA1, which is included in the first horizontal region HA1, may include a light-emitting region EA and a first transmission region TA1. Within the first optical region OA1, each outer region of the first transmission region TA1 may include a corresponding light-emitting region EA.

[0162] Reference Figure 5A In order to improve the transmittance of the first optical region OA1, the first horizontal line HL1 can penetrate the first optical region OA1 while avoiding the first transmission region TA1 in the first optical region OA1.

[0163] Therefore, each of the first horizontal lines HL1 that traverse the first optical region OA1 may include one or more curved or bent portions that pass around one or more corresponding outer edges of one or more first transmission regions TA1.

[0164] Therefore, the first horizontal line HL1 set in the first horizontal region HA1 and the second horizontal line HL2 set in the second horizontal region HA2 can have different shapes or lengths. For example, the first horizontal line HL1 that penetrates the first optical region OA1 and the second horizontal line HL2 that does not penetrate the first optical region OA1 can have different shapes or lengths.

[0165] In addition, in order to improve the transmittance of the first optical region OA1, the first vertical line VL1 can penetrate the first optical region OA1 while avoiding the first transmission region TA1 in the first optical region OA1.

[0166] Therefore, each of the first vertical lines VL1 passing through the first optical region OA1 may include one or more curved or bent portions that pass around one or more corresponding outer edges of one or more first transmission regions TA1.

[0167] Therefore, the first vertical line VL1 that penetrates the first optical region OA1 and the typical vertical line VLn that is set in the normal region NA but does not penetrate the first optical region OA1 can have different shapes or lengths.

[0168] Reference Figure 5A The first transmission region TA1, which is included in the first optical region OA1 in the first horizontal region HA1, can be arranged along the diagonal direction.

[0169] Reference Figure 5A In the first optical region OA1 within the first horizontal region HA1, one or more light-emitting regions EA can be positioned between two horizontally adjacent first transmission regions TA1. In the first optical region OA1 within the first horizontal region HA1, one or more light-emitting regions EA can be positioned between two vertically adjacent first transmission regions TA1.

[0170] Reference Figure 5A The first horizontal line HL1 set in the first horizontal region HA1, that is, the first horizontal line HL1 that runs through the first optical region OA1, may include one or more curved or bent portions that pass around one or more corresponding outer edges of one or more first transmission regions TA1.

[0171] Reference Figure 5B The second optical region OA2, included in the first horizontal region HA1, may include a light-emitting region EA and a second transmission region TA2. Within the second optical region OA2, each outer region of the second transmission region TA2 may include a corresponding light-emitting region EA.

[0172] In one embodiment, the light-emitting region EA and the second transmission region TA2 in the second optical region OA2 can have the same characteristics as... Figure 5A The light-emitting region EA and the first transmission region TA1 in the first optical region OA1 are in substantially the same position and arrangement.

[0173] In another implementation, such as Figure 5B As shown, the light-emitting region EA and the second transmission region TA2 in the second optical region OA2 can have the same characteristics as... Figure 5A The first optical region OA1 has different positions and arrangements of the light-emitting region EA and the first transmission region TA1.

[0174] For example, refer to Figure 5B The second transmission regions TA2 in the second optical region OA2 can be arranged horizontally (from left to right or from right to left). No light-emitting region EA may be provided between two adjacent second transmission regions TA2 in the horizontal direction. Furthermore, one or more light-emitting regions EA in the second optical region OA2 may be provided between adjacent second transmission regions TA2 in the vertical direction (from top to bottom or from bottom to top). For example, one or more light-emitting regions EA may be provided between two rows of second transmission regions.

[0175] In one embodiment, when the first horizontal line HL1 passes through the second optical region OA2 and the normal region NA adjacent to the second optical region OA2, the first horizontal line HL1 can have the same characteristics as... Figure 5A The first horizontal line HLA1 has a basically the same arrangement.

[0176] In another implementation, such as Figure 5B As shown, when the first horizontal line HL1 passes through the second optical region OA2 and the normal region NA adjacent to the second optical region OA2 in the first horizontal region HA1, the first horizontal line HL1 can have the same characteristics as... Figure 5A The first horizontal line HL1 has a different arrangement.

[0177] This is because Figure 5B The luminescent region EA and the second transmission region TA2 in the second optical region OA2 have the same characteristics as... Figure 5A The first optical region OA1 has different positions and arrangements of the light-emitting region EA and the first transmission region TA1.

[0178] Reference Figure 5B When the first horizontal line HL1 passes through the second optical region OA2 and the normal region NA adjacent to the second optical region OA2 in the first horizontal region HA1, the first horizontal line HL1 can travel in a straight line between the vertically adjacent second transmission regions TA2 without having any curved or bent portions.

[0179] For example, a first horizontal line HL1 may have one or more curved or bent portions in a first optical region OA1, but may not have curved or bent portions in a second optical region OA2.

[0180] In order to improve the transmittance of the second optical region OA2, the second vertical line VL2 can penetrate the second optical region OA2 while avoiding the second transmission region TA2 in the second optical region OA2.

[0181] Therefore, each of the second vertical lines VL2 that traverse the second optical region OA2 may include one or more curved or bent portions that pass around one or more corresponding outer edges of the second transmission region TA2.

[0182] Therefore, the second vertical line VL2 that penetrates the second optical region OA2 and the typical vertical line VLn that is set in the normal region NA but does not penetrate the second optical region OA2 can have different shapes or lengths.

[0183] like Figure 5A As shown, each or one or more of the first horizontal lines HL1 that pass through the first optical region OA1 may have one or more curved or bent portions that pass around one or more corresponding outer edges of one or more first transmission regions TA1.

[0184] Therefore, the length of the first horizontal line HL1 that passes through the first optical region OA1 and the second optical region OA2 can be slightly longer than the length of the second horizontal line HL2 that is set in the normal region NA but does not pass through the first optical region OA1 and the second optical region OA2.

[0185] Therefore, the resistance of the first horizontal line HL1 that runs through the first optical region OA1 and the second optical region OA2 (referred to as the first resistance) can be slightly larger than the resistance of the second horizontal line HL2 that is set in the normal region NA but does not run through the first optical region OA1 and the second optical region OA2 (referred to as the second resistance).

[0186] Reference Figure 5A and Figure 5B According to the light transmission structure, since the first optical region OA1, which overlaps at least partially with the first optical electronic device 11, includes a first transmission region TA1, and the second optical region OA2, which overlaps at least partially with the second optical electronic device 12, includes a second transmission region TA2, the first optical region OA1 and the second optical region OA2 can have fewer pixels per unit area than the normal region NA.

[0187] Therefore, the number of pixels connected to each or one or more of the first horizontal lines HL1 that traverse the first optical region OA1 and the second optical region OA2 may be different from the number of pixels connected to each or one or more of the second horizontal lines HL2 that are only set in the normal region NA and do not traverse the first optical region OA1 and the second optical region OA2.

[0188] The number of pixels connected to each or one or more of the first horizontal lines HL1 that traverse the first optical region OA1 and the second optical region OA2 (referred to as the first number) may be less than the number of pixels connected to each or one or more of the second horizontal lines HL2 that are only set in the normal region NA and do not traverse the first optical region OA1 and the second optical region OA2 (referred to as the second number).

[0189] The difference between the first number and the second number can vary based on the difference between the resolution of each of the first optical region OA1 and the second optical region OA2 and the resolution of the normal region NA. For example, as the difference between the resolution of each of the first optical region OA1 and the second optical region OA2 and the resolution of the normal region NA increases, the difference between the first number and the second number can increase.

[0190] As described above, since the number of pixels (first number) connected to each or one or more of the first horizontal lines HL1 that traverse the first optical region OA1 and the second optical region OA2 is less than the number of pixels (second number) connected to each or one or more of the second horizontal lines HL2 that are only set in the normal region NA and do not traverse the first optical region OA1 and the second optical region OA2, the area where the first horizontal line HL1 overlaps with one or more other electrodes or lines adjacent to the first horizontal line HL1 can be smaller than the area where the second horizontal line HL2 overlaps with one or more other electrodes or lines adjacent to the second horizontal line HL2.

[0191] Therefore, the parasitic capacitance (referred to as the first capacitance) formed between the first horizontal line HL1 and one or more other electrodes or lines adjacent to the first horizontal line HL1 can be much smaller than the parasitic capacitance (referred to as the second capacitance) formed between the second horizontal line HL2 and one or more other electrodes or lines adjacent to the second horizontal line HL2.

[0192] Considering the magnitude relationship between the first resistor and the second resistor (first resistor ≥ second resistor) and the magnitude relationship between the first capacitor and the second capacitor (first capacitor << second capacitor), the resistance-capacitance (RC) value of the first horizontal line HL1 that passes through the first optical region OA1 and the second optical region OA2 (referred to as the first RC value) can be much smaller than the RC value of the second horizontal line HL2 that is set in the normal region NA and does not pass through the first optical region OA1 and the second optical region OA2 (referred to as the second RC value). That is, the first RC value << the second RC value.

[0193] Because of this difference (called RC load difference) between the first RC value of the first horizontal line HL1 and the second RC value of the second horizontal line HL2, the signal transmission characteristics through the first horizontal line HL1 may be different from those through the second horizontal line HL2.

[0194] Figure 6 and Figure 7 This is a cross-sectional view of each of the first optical region OA1, the second optical region OA2, and the normal region NA included in the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0195] Figure 6 The example shown is a display panel 110 in which a touch sensor is implemented as a touch panel outside the display panel 110, and Figure 7 The example of a display panel 110 in which a touch sensor TS is implemented inside the display panel 110 is shown.

[0196] Figure 6 and Figure 7 Each of the figures shows a cross-sectional view of the normal region NA, the first optical region OA1, and the second optical region OA2 included in the display area DA.

[0197] Reference Figure 6 and Figure 7 Describe the stacking structure of the normal region NA. The respective light-emitting regions EA of the first optical region OA1 and the second optical region OA2 can have the same stacking structure as the light-emitting region EA of the normal region NA1.

[0198] Reference Figure 6 and Figure 7The substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be located between the first substrate SUB1 and the second substrate SUB2. Since the substrate SUB includes the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2, the substrate SUB can prevent or at least reduce the penetration of moisture. The first substrate SUB1 and the second substrate SUB2 may be, for example, polyimide (PI) substrates. The first substrate SUB1 may be referred to as the main PI substrate, and the second substrate SUB2 may be referred to as the secondary PI substrate.

[0199] Reference Figure 6 and Figure 7 Various types of patterns such as ACT, SD1, GATE, various types of insulating layers such as MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, and various types of metal patterns such as TM, GM, ML1, ML2 can be set on or above the substrate SUB for setting one or more transistors, such as driving transistors DRT.

[0200] Reference Figure 6 and Figure 7 Multiple buffer layers (MBUF) can be provided on the second substrate SUB2, and a first active buffer layer (ABUF1) can be provided on the multiple buffer layers (MBUF).

[0201] A first metal layer ML1 and a second metal layer ML2 can be disposed on the first active buffer layer ABUF1. The first metal layer ML1 and the second metal layer ML2 can be, for example, light-shielding layers LS for shielding light.

[0202] A second active buffer layer ABUF2 can be disposed on the first metal layer ML1 and the second metal layer ML2. An active layer ACT for driving the DRT transistor can be disposed on the second active buffer layer ABUF2.

[0203] The gate insulating layer GI can be set to cover the active layer ACT.

[0204] The gate electrode GATE of the driving transistor DRT can be disposed on the gate insulating layer GI. Alternatively, at a location different from where the driving transistor DRT is disposed, the gate material layer GM can be disposed together with the gate electrode GATE of the driving transistor DRT on the gate insulating layer GI.

[0205] A first interlayer insulating layer (ILD1) can be provided to cover the gate electrode (GATE) and the gate material layer (GM). A metal pattern (TM) can be provided on the first interlayer insulating layer (ILD1). The metal pattern (TM) can be located at a location different from where the driving transistor (DRT) is designed. A second interlayer insulating layer (ILD2) can be provided to cover the metal pattern (TM) on the first interlayer insulating layer (ILD1).

[0206] Two first source-drain electrode patterns SD1 can be formed on the second interlayer insulating layer ILD2. One of the two first source-drain electrode patterns SD1 can be the source node of the driving transistor DRT, and the other can be the drain node of the driving transistor DRT.

[0207] The two first source-drain electrode patterns SD1 can be electrically connected to the first and second sides of the active layer ACT, respectively, through contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI.

[0208] A portion of the active layer ACT overlapping with the gate electrode GATE can be used as a channel region. One of the two first source-drain electrode patterns SD1 can be connected to a first side of the channel region of the active layer ACT, and the other of the two first source-drain electrode patterns SD1 can be connected to a second side of the channel region of the active layer ACT.

[0209] A passivation layer PAS0 can be provided to cover the two first source-drain electrode patterns SD1. A planarization layer PLN can be provided on the passivation layer PAS0. The planarization layer PL may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0210] The first planarization layer PLN1 can be set on the passivation layer PAS0.

[0211] A second source-drain electrode pattern SD2 can be formed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 can be connected to one of the two first source-drain electrode patterns SD1 (corresponding to) through contact holes formed in the first planarization layer PLN1. Figure 3 The second node N2 of the driving transistor DRT in pixel SP).

[0212] The second planarization layer PLN2 can be configured to cover the second source-drain electrode pattern SD2. A light-emitting element ED can be disposed on the second planarization layer PLN2.

[0213] Based on the example stacked structure of the light-emitting element (ED), an anode electrode AE ​​can be disposed on the second planarization layer PLN2. The anode electrode AE ​​can be electrically connected to the second source-drain electrode pattern SD2 through contact holes formed in the second planarization layer PLN2.

[0214] A dam can be set to cover a portion of the anode electrode AE. A portion of the dam corresponding to the light-emitting area EA of pixel SP can be turned on.

[0215] A portion of the anode electrode AE ​​can be exposed through an opening (opening portion) in the dam bank. The luminescent layer EL can be located on the side surface of the dam bank and within the opening (opening portion) of the dam bank. All or at least a portion of the luminescent layer EL can be located between adjacent dams.

[0216] In the opening of the dam BANK, the light-emitting layer EL can contact the anode electrode AE. The cathode electrode CE can be disposed on the light-emitting layer EL.

[0217] As described above, a light-emitting element ED can be formed by including an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The light-emitting layer EL may include a layer of organic material.

[0218] An encapsulation layer ENCAP can be placed on the stack of light-emitting elements (EDs).

[0219] The ENCAP encapsulation layer can have a single-layer or multi-layer structure, for example, Figure 6 and Figure 7 As shown, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0220] The first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be, for example, inorganic material layers, and the second encapsulation layer PCL can be, for example, an organic material layer. Among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL can be the thickest and serves as a planarization layer.

[0221] The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and can be positioned closest to the light-emitting element ED. The first encapsulation layer PAS1 can include an inorganic insulating material that can be deposited using low-temperature deposition. For example, the first encapsulation layer PAS1 can include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), aluminum oxide (Al2O3), etc. Because the first encapsulation layer PAS1 can be deposited in a low-temperature atmosphere, it can prevent damage to the light-emitting layer EL, which includes organic materials susceptible to high-temperature atmospheres, during the deposition process.

[0222] The second encapsulation layer PCL can have a smaller area or size than the first encapsulation layer PAS1. For example, the second encapsulation layer PCL can be configured to expose the ends or edges of the first encapsulation layer PAS1. The second encapsulation layer PCL can act as a buffer to alleviate stress between corresponding layers when the display device 100 is bent or folded, and also to enhance planarization performance. For example, the second encapsulation layer PCL can include organic insulating materials such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon carbide (SiOC), etc. The second encapsulation layer PCL can be configured, for example, using an inkjet printing method.

[0223] A third encapsulation layer, PAS2, can be disposed on a substrate SUB on which a second encapsulation layer, PCL, is disposed, such that the third inorganic encapsulation layer, PAS2, covers the corresponding top and side surfaces of the second encapsulation layer, PCL, and the first encapsulation layer, PAS1. The third encapsulation layer, PAS2, can minimize, prevent, or at least reduce the penetration of external moisture or oxygen into the first encapsulation layer, PAS1, and the second encapsulation layer, PCL. For example, the third encapsulation layer, PAS2, may include inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), aluminum oxide (Al2O3), etc.

[0224] Reference Figure 7 In the example where the touch sensor TS is embedded in the display panel 110, the touch sensor TS can be disposed on the encapsulation layer ENCAP. The structure of the touch sensor will be described in detail below.

[0225] A touch buffer layer (T-BUF) can be set on the ENCAP encapsulation layer. A touch sensor (TS) can be set on the T-BUF touch buffer layer.

[0226] The touch sensor TS may include a touch sensor metal TSM located in different layers and at least one bridging metal BRG.

[0227] A touch interlayer insulating layer (T-ILD) can be set between the touch sensor metal TSM and the bridging metal BRG.

[0228] For example, a touch sensor metal TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM disposed adjacent to each other. In an embodiment where the third touch sensor metal TSM is disposed between the first and second touch sensor metal TSMs, and the first and second touch sensor metal TSMs need to be electrically connected to each other, the first and second touch sensor metal TSMs can be electrically connected to each other through a bridging metal BRG located on different layers. The bridging metal BRG can be electrically insulated from the third touch sensor metal TSM through a touch layer interlayer insulating layer (T-ILD).

[0229] When the touch sensor TS is disposed on the display panel 110, chemical solutions (e.g., developers or etchants) used in the corresponding processes or external moisture may be generated or introduced. By disposing the touch sensor TS on the touch buffer layer T-BUF, chemical solutions or moisture can be prevented from penetrating into the light-emitting layer EL, which includes organic materials, during the manufacturing process of the touch sensor TS. Therefore, the touch buffer layer T-BUF can prevent or at least reduce damage to the light-emitting layer EL, which is susceptible to chemical solutions or moisture.

[0230] To prevent or at least reduce damage to the light-emitting layer EL, which is susceptible to high temperatures and includes organic materials, the touch buffer layer T-BUF can be formed at a low temperature (e.g., 100 degrees Celsius) or lower and using an organic insulating material with a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF may include acrylic-based, epoxy-based, or silicone-based materials. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal located on the touch buffer layer T-BUF may crack or break. Even when the display device 100 is bent, the touch buffer layer T-BUF, as an organic insulating material with planarization properties, can prevent damage to the encapsulation layer ENCAP and / or cracking or breakage of the metal (TSM, BRG) included in the touch sensor TS.

[0231] A protective layer PAC can be provided to cover the touch sensor TS. The protective layer PAC can be, for example, an organic insulating layer.

[0232] Next, we will refer to Figure 6 and Figure 7 Describe the stacking structure of the first optical region OA1.

[0233] Reference Figure 6 and Figure 7The emitting region EA of the first optical region OA1 can have the same stacking structure as the normal region NA. Therefore, in the following discussion, the stacking structure of the first transmission region TA1 in the first optical region OA1 will be described in detail, without repeating the description of the emitting region EA of the first optical region OA1.

[0234] The cathode electrode CE may be disposed in the light-emitting region EA, which is included in the normal region NA and the first optical region OA1, but may not be disposed in the first transmission region TA1 in the first optical region OA1. For example, the first transmission region TA1 in the first optical region OA1 may correspond to the opening of the cathode electrode CE.

[0235] Furthermore, a light-shielding layer LS, comprising at least one of a first metal layer ML1 and a second metal layer ML2, may be disposed in the light-emitting region EA, which is included in the normal region NA and the first optical region OA1, but may not be disposed in the first transmission region TA1 in the first optical region OA1. For example, the first transmission region TA1 in the first optical region OA1 may correspond to the opening of the light-shielding layer LS.

[0236] The substrate SUB and various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN (PLN1, PLN2), BANK, ENCAP (PAS1, PCL, PAS2), T-BUF, T-ILD, PAC) disposed in the light-emitting region EA, which includes the normal region NA and the first optical region OA1, can be disposed in the first transmission region TA1 in the first optical region OA1 in an equal, substantially equal, or similar manner.

[0237] However, apart from insulating materials or layers, all or one or more of the electrically-characteristic material layers (e.g., metal material layers, semiconductor layers, etc.) disposed in one or more of the light-emitting regions EA included in the normal region NA and the first optical region OA1 may not be disposed in the first transmission region TA1 in the first optical region OA1.

[0238] For example, refer to Figure 6 and Figure 7 All or one or more of the metal material layers (ML1, ML2, GATE, GM, TM, SD1, SD2) and semiconductor layers ACT associated with at least one transistor may not be disposed in the first transmission region TA1.

[0239] In addition, refer to Figure 6 and Figure 7The anode electrode AE ​​and cathode electrode CE in the light-emitting element ED may not be disposed in the first transmission region TA1. In some embodiments, depending on design requirements, the light-emitting layer EL of the light-emitting element ED may be disposed in the first transmission region TA1 or may not be disposed in the first transmission region TA1.

[0240] In addition, refer to Figure 7 The touch sensor metal TSM and bridging metal BRG included in the touch sensor TS may not be set in the first transmission region TA1 in the first optical region OA1.

[0241] Therefore, since the material layer with electrical properties (e.g., a metal material layer, a semiconductor layer, etc.) is not disposed in the first transmission region TA1 of the first optical region OA1, the transmittance of the first transmission region TA1 in the first optical region OA1 can be provided or improved. Therefore, the first optoelectronic device 11 can perform a predetermined function (e.g., image sensing) by receiving light transmitted through the first transmission region TA1.

[0242] Since all or one or more of the first transmission regions TA1 in the first optical region OA1 overlap with the first optical electronic device 11, it is desirable to further increase the transmittance of the first transmission regions TA1 in the first optical region OA1 in order for the first optical electronic device 11 to operate normally.

[0243] Therefore, in some embodiments, the first transmission region TA1 formed in the first optical region OA1 of the display panel 110 of the display device 100 may have a transmittance improvement structure TIS.

[0244] Reference Figure 6 and Figure 7 The multiple insulating layers included in the display panel 110 may include at least one buffer layer (MBUF, ABUF1, ABUF2) between at least one substrate (SUB1, SUB2) and at least one transistor (DRT, SCT), at least one planarization layer (PLN1, PLN2) between the transistor DRT and the light-emitting element ED, at least one encapsulation layer ENCAP on the light-emitting element ED, etc.

[0245] Reference Figure 7 The multiple insulating layers included in the display panel 110 may also include a touch buffer layer T-BUF and a touch interlayer insulating layer T-ILD located on the encapsulation layer ENCAP.

[0246] Reference Figure 6 and Figure 7The first transmission region TA1 in the first optical region OA1 may have a structure (e.g., recess, trench, depression, protrusion, etc.) in which the first planarization layer PLN1 and the passivation layer PAS0 have recesses extending downward from their respective surfaces toward the substrate SUB as a transmission improvement structure TIS.

[0247] Reference Figure 6 and Figure 7 In the plurality of insulating layers, the first planarization layer PLN1 may include at least one recess (e.g., a recess, trench, depression, protrusion, etc.). The first planarization layer PLN1 may be, for example, an organic insulating layer.

[0248] In an example where the first planarization layer PLN1 has a recess extending downward from its surface, the second planarization layer PLN2 can essentially be used to provide planarization. In one embodiment, the second planarization layer PLN2 may also have a recess extending downward from its surface. In this embodiment, the second encapsulation layer PCL can essentially be used to provide planarization.

[0249] Reference Figure 6 and Figure 7 The recesses of the first planarization layer PLN1 and the passivation layer PAS0 can pass through the insulating layer, such as the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the gate insulating layer GI, etc., used to form the transistor DRT, and the buffer layer located below the insulating layer and extending to the upper part of the second substrate SUB2, such as the first active buffer layer ABUF1, the second active buffer layer ABUF2, the multi-buffer layer MBUF, etc.

[0250] Reference Figure 6 and Figure 7 The substrate SUB may include at least one recess or depression as a transmittance improvement structure (TIS). For example, in the first transmission region TA1, the upper part of the second substrate SUB2 may be recessed or recessed downwards, or the second substrate SUB2 may be perforated.

[0251] Reference Figure 6 and Figure 7 The first encapsulation layer PAS1 and the second encapsulation layer PCL included in the encapsulation layer ENCAP may also have a transmittance-improving structure TIS in which the first encapsulation layer PAS1 and the second encapsulation layer PCL have recessed portions extending downward from their respective surfaces. The second encapsulation layer PCL may be, for example, an organic insulating layer.

[0252] Reference Figure 7 To protect the touch sensor TS, a protective layer PAC can be set to cover the touch sensor TS on the encapsulation layer ENCAP.

[0253] Reference Figure 7In the portion overlapping with the first transmission region TA1, the protective layer PAC may have at least one recess (e.g., a recess, groove, depression, protrusion, etc.) as a transmittance-improving structure TIS. The protective layer PAC may be, for example, an organic insulating layer.

[0254] Reference Figure 7 The touch sensor TS may include one or more touch sensor metal TSMs with a grid pattern. In the example where the touch sensor metal TSM is formed in a grid pattern, multiple openings may be formed in the touch sensor metal TSM. Each of the multiple openings may be positioned as a light-emitting area EA corresponding to a pixel SP.

[0255] In order to make the first optical region OA1 have a higher transmittance than the normal region NA, the area or size of the touch sensor metal TSM per unit area in the first optical region OA1 can be smaller than the area or size of the touch sensor metal TSM per unit area in the normal region NA.

[0256] Reference Figure 7 The touch sensor TS can be set in the light-emitting area EA of the first optical area OA1, but it can be set out of the first transmission area TA1 of the first optical area OA1.

[0257] Next, we will refer to Figure 6 and Figure 7 Describe the stacking structure of the second optical region OA2.

[0258] Reference Figure 6 and Figure 7 The emitting region EA of the second optical region OA2 can have the same stacking structure as the normal region NA. Therefore, in the following discussion, the stacking structure of the second transmission region TA2 in the second optical region OA2 will be described in detail, without repeating the description of the emitting region EA in the second optical region OA2.

[0259] The cathode electrode CE can be disposed in the light-emitting region EA, which is included in the normal region NA and the second optical region OA2, but it can be disposed outside the second transmission region TA2 in the second optical region OA2. For example, the second transmission region TA2 in the second optical region OA2 can correspond to the opening of the cathode electrode CE.

[0260] Furthermore, a light-shielding layer LS, comprising at least one of a first metal layer ML1 and a second metal layer ML2, may be disposed in the light-emitting region EA, which is included in the normal region NA and the second optical region OA2, but may not be disposed in the second transmission region TA2 in the second optical region OA2. For example, the second transmission region TA2 in the second optical region OA2 may correspond to the opening of the light-shielding layer LS.

[0261] In an example where the transmittance of the second optical region OA2 is the same as that of the first optical region OA1, the stacking structure of the second transmission region TA2 in the second optical region OA2 can be the same as the stacking structure of the first transmission region TA1 in the first optical region OA1.

[0262] In another example where the transmittance of the second optical region OA2 is different from that of the first optical region OA1, the stacking structure of the second transmission region TA2 in the second optical region OA2 may be at least partially different from the stacking structure of the first transmission region TA1 in the first optical region OA1.

[0263] For example, such as Figure 6 and Figure 7 As shown, when the transmittance of the second optical region OA2 is less than that of the first optical region OA1, the second transmittance region TA2 in the second optical region OA2 may not have a transmittance improvement structure (TIS). Therefore, the first planarization layer PLN1 and the passivation layer PAS0 may not be recessed or sunken. Furthermore, the width of the second transmittance region TA2 in the second optical region OA2 may be less than the width of the first transmittance region TA1 in the first optical region OA1.

[0264] The substrate SUB and various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN (PLN1, PLN2), BANK, ENCAP (PAS1, PCL, PAS2), T-BUF, T-ILD, PAC) disposed in the light-emitting region EA, which includes the normal region NA and the second optical region OA2, can be disposed in the second transmission region TA2 in the second optical region OA2 in an equivalent, substantially equivalent, or similar manner.

[0265] However, apart from insulating materials or layers, all or one or more of the electrically conductive material layers (e.g., metal material layers, semiconductor layers, etc.) disposed in the light-emitting regions EA, which are included in the normal region NA and the second optical region OA2, may not be disposed in the second transmission region TA2 of the second optical region OA2.

[0266] For example, refer to Figure 6 and Figure 7 All or one or more of the metal material layers (ML1, ML2, GATE, GM, TM, SD1, SD2) and semiconductor layers ACT associated with at least one transistor may not be disposed in the second transmission region TA2 in the second optical region OA2.

[0267] In addition, refer to Figure 6 and Figure 7The anode electrode AE ​​and cathode electrode CE in the light-emitting element ED may not be disposed in the second transmission region TA2. In some embodiments, depending on design requirements, the light-emitting layer EL of the light-emitting element ED may be disposed on the second transmission region TA2 or may not be disposed on the second transmission region TA2.

[0268] In addition, refer to Figure 7 The touch sensor metal TSM and bridging metal BRG included in the touch sensor TS may not be set in the second transmission region TA2 in the second optical region OA2.

[0269] Therefore, since the material layer with electrical properties (e.g., a metal material layer, a semiconductor layer, etc.) is not disposed in the second transmission region TA2 of the second optical region OA2, the transmittance of the second transmission region TA2 in the second optical region OA2 can be provided or improved. Therefore, the second optoelectronic device 12 can perform a predetermined function (e.g., object or human body proximity detection, external lighting detection, etc.) by receiving light transmitted through the second transmission region TA2.

[0270] Figure 8 This is a cross-sectional view of the edge of a display panel 110 according to an embodiment of the present disclosure.

[0271] To simplify the explanation, Figure 8 A single substrate SUB comprising a first substrate SUB1 and a second substrate SUB2 is shown, and a layer or portion located below the embankment BANK is also shown in a simplified structure. Similarly, Figure 8 A single planarization layer PLN is shown, comprising a first planarization layer PLN1 and a second planarization layer PLN2, and a single interlayer insulation layer INS comprising a second interlayer insulation layer ILD2 and a first interlayer insulation layer ILD1 located below the planarization layer PLN.

[0272] Reference Figure 8 The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and positioned closest to the light-emitting element ED. The second encapsulation layer PCL can have a smaller area or size than the first encapsulation layer PAS1. For example, the second encapsulation layer PCL can be configured to expose the ends or edges of the first encapsulation layer PAS1.

[0273] The third encapsulation layer PAS2 can be disposed on the substrate SUB on which the second encapsulation layer PCL is disposed, such that the third encapsulation layer PAS2 covers the corresponding top and side surfaces of the second encapsulation layer PCL and the first encapsulation layer PAS1.

[0274] The third encapsulation layer PAS2 can reduce or prevent external moisture or oxygen from penetrating into the first encapsulation layer PAS1 and the second encapsulation layer PCL.

[0275] Reference Figure 8 To prevent or at least reduce the collapse of the encapsulation layer ENCAP, the display panel 110 may include one or more dams (DAM1, DAM2) at or near the end or edge of the inclined surface SLP of the encapsulation layer ENCAP. One or more dams (DAM1, DAM2) may exist at or near the boundary point between the display area DA and the non-display area NDA.

[0276] One or more weirs (DAM1, DAM2) may include DFP made of the same material as the dam section BANK.

[0277] Reference Figure 8 In one embodiment, the second encapsulation layer PCL, comprising organic material, may be located only on the inner side of the first weir DAM1, which is situated on the inclined surface SLP closest to the encapsulation layer ENCAP. For example, the second encapsulation layer PCL may not be located on all weirs (DAM1, DAM2). In another embodiment, the second encapsulation layer PCL, comprising organic material, may be located on at least the first weir DAM1 of the first weir DAM1 and the second weir DAM2.

[0278] For example, the second encapsulation layer PCL may extend only to all or at least a portion of the upper portion of the first weir DAM1. In another embodiment, the second encapsulation layer PCL may extend beyond the upper portion of the first weir DAM1 and extend to all or at least a portion of the upper portion of the second weir DAM2.

[0279] Reference Figure 8 The touch panel TP electrically connected to the touch driving circuit 260 can be disposed on a portion of the substrate SUB outside one or more weirs (DAM1, DAM2).

[0280] The touch line TL can electrically connect the touch sensor metal TSM or bridging metal BRG to the touchpad TP. The metal TSM or bridging metal BRG is included in or used as a touch electrode disposed in the display area DA.

[0281] One end or edge of the touch line TL can be electrically connected to the touch sensor metal TSM or the bridging metal BRG, and the other end or edge of the touch line TL can be electrically connected to the touchpad TP.

[0282] The touch line TL can extend downward along the inclined surface SLP of the encapsulation layer ENCAP, extend along the corresponding upper part of the weirs DAM1 and DAM2, and extend to the touch panel TP located outside the weirs (DAM1 and DAM2).

[0283] Reference Figure 8In one embodiment, the touch line TL can be a bridging metal BRG. In another embodiment, the touch line TL can be a touch sensor metal TSM.

[0284] Figure 9 The system configuration of a display device according to an embodiment of the present disclosure is shown.

[0285] Reference Figure 9 According to one embodiment, the display device 100 may include a display panel 110, a data driving circuit 220, a gate driving circuit 230, a first power supply circuit 910, and a second power supply circuit 920.

[0286] The display panel 110 may include a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, a plurality of first initialization power lines VL11 to VL1n and a plurality of power lines VL21 to VL2n, and a plurality of pixels 101 connected to the plurality of data lines DL1 to DLm, the plurality of gate lines GL1 to GLn, the plurality of first initialization power lines VL11 to VL1n and the plurality of power lines VL21 to VL2n, and the plurality of pixels 101 are configured to emit light.

[0287] At least one of the plurality of pixels 101 may include a driving transistor for generating a driving current in response to a voltage corresponding to a data signal and a light-emitting element for emitting light by receiving the driving current.

[0288] The data driver circuit 220 can be connected to multiple data lines DL1 to DLm and supply data signals to these lines. The data driver circuit 220 can be implemented in an integrated circuit. The data driver circuit 220 can receive image signals as digital signals and generate and supply data signals as analog signals.

[0289] The gate drive circuit 230 can be connected to a plurality of gate lines GL1 to GLn and supply gate signals to the plurality of gate lines GL1 to GLn. Although the gate drive circuit 230 is shown as being located outside the display panel 110, in some cases, the gate drive circuit 230 may be disposed within the display panel 110.

[0290] The first power supply circuit 910 can supply a first initialization voltage to a plurality of first initialization power lines VL11 to VL1n. The first initialization voltage can have a voltage level between a first voltage level and a second voltage level. The first initialization voltage can have a first voltage level in a first time period, a third voltage level between the first and second voltage levels in a second time period, and a second voltage level in a third time period. In one embodiment, the second voltage level is lower than the first and third voltage levels. Here, the first, second, and third time periods can be consecutive time periods. Although the first power supply circuit 910 is shown as located outside the display panel 110, in some cases, the first power supply circuit 910 can be disposed within the display panel 110.

[0291] The second power supply circuit 920 can supply driving voltages to multiple power lines VL21 to VL2n. The driving voltages supplied from the second power supply circuit 920 can include a pixel driving voltage (which is a voltage with a high level) and a base voltage (which is a voltage with a low level). The voltage level of the pixel driving voltage can be less than a first voltage level of the first initialization voltage. The voltage level of the pixel driving voltage can be the same as (e.g., matched) a third voltage level of the first initialization voltage. The second power supply circuit 920 can also supply a second initialization voltage. However, the voltages supplied from the second power supply circuit 920 are not limited thereto.

[0292] In addition, the display device 100 may include a display controller 240 capable of controlling the data driving circuit 220, the gate driving circuit 230, the first power supply circuit 910, and the second power supply circuit 920. The display controller 240 may output image signals, clock signals, and synchronization signals.

[0293] A touch sensor for sensing touch can be disposed on the display device 100 so as to overlap with the display panel 110.

[0294] At least one of the data driving circuit 220, the gate driving circuit 230, the first power supply circuit 910, and the second power supply circuit 920 may include logic circuitry. When the display device 100 operates at a low frequency, the time used for logic circuit operation can be reduced, and therefore, the power consumption in the data driving circuit 220, the gate driving circuit 230, the first power supply circuit 910, or the second power supply circuit 920, which includes logic circuitry, can be reduced, thereby lowering the power consumption of the display device 100.

[0295] Figure 10 An embodiment of the setting is shown. Figure 9 The display panel shown contains a gate drive circuit and a first power supply circuit.

[0296] Reference Figure 10 The display panel 110 may include a substrate SUB as previously described above. A plurality of pixels 101 may be disposed on the substrate SUB. Furthermore, various types of signal lines for driving the plurality of pixels 101 may be disposed in the display panel 110.

[0297] Multiple stages 1000 can be disposed on one side of the substrate SUB. However, embodiments of this disclosure are not limited thereto. For example, multiple stages 1000 can be disposed on each of the two sides of the substrate SUB.

[0298] Multiple levels of 1000 can be used Figure 9 The gate drive circuit 230 and the first power supply circuit 910 shown are disposed on the display panel 110. Figure 9 The gate drive circuit 230 in the middle can be implemented by stage 1000a, which is shown in a box without shaded areas in the multiple stages 1000, and Figure 9 The first power supply circuit 910 can be implemented by a stage 1000b, which is shown as a shaded frame among the multiple stages 1000. However, the arrangement of the stages (1000a, 1000b) in the display panel 110 is not limited to this.

[0299] Stage 1000a, included in gate drive circuit 220, can sequentially output gate signals to a plurality of gate lines GL, and stage 1000b, included in first power supply circuit 910, can sequentially apply first initialization voltages to a plurality of first initialization power lines VL1. Gate drive circuit 220 and first power supply circuit 910 are shown to each include three stages, but embodiments of this disclosure are not limited thereto.

[0300] Furthermore, although only multiple stages 1000 are shown disposed on the substrate SUB for ease of description, embodiments of this disclosure are not limited thereto. The multiple stages (1000a, 1000b) included in the gate drive circuit 220 and the first power supply circuit 910 can be disposed during the process of disposing pixels on the substrate SUB. Therefore, the process of manufacturing the display device 100 can be further simplified compared to separately connecting the gate drive circuit 220 and the first power supply circuit 910.

[0301] The gate driving circuit 220 and the first power supply circuit 910 can be disposed in a non-display area on the substrate SUB. In the example where the gate driving circuit 220 and the first power supply circuit 910 are disposed in a non-display area, the bezel of the display device 100 can be thinner.

[0302] Figure 11 An embodiment is shown. Figure 9 The circuit diagram of the pixels used in the display device shown is shown.

[0303] Reference Figure 11 Pixel 101 may include: a driving transistor DRT for causing a driving current to flow from a second node N2 to a third node N3 in response to a voltage of a first node N1 having a voltage corresponding to a data signal, and a light-emitting element ED for emitting light by the driving current from the driving transistor DRT.

[0304] The first and second electrodes of the driving transistor DRT can be connected to the second node N2 and the third node N3, respectively. The gate electrode of the driving transistor DRT can be connected to the first node N1. A voltage corresponding to the data signal can be applied to the first node N1. When the pixel driving voltage ELVDD is applied to the second node N2, the driving transistor DRT can allow current to flow from the second node N2 to the node N3 according to the voltage level applied to the first node N1.

[0305] A light-emitting element (ED) may include an anode electrode, a cathode electrode, and a light-emitting layer disposed between the anode and cathode electrodes. A base voltage ELVSS may be applied to the cathode electrode of the ED. The base voltage applied to the cathode electrode of the ED may be ground voltage or a negative voltage, and when a high-level voltage is applied to the anode electrode of the ED, current can flow from the anode electrode to the cathode electrode. Therefore, the ED can emit light.

[0306] The light-emitting element (ED) can be, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting element, etc. In an example using an organic light-emitting diode as the light-emitting element (ED), the light-emitting layer (EL) included in the light-emitting element (ED) may include an organic light-emitting layer containing organic materials.

[0307] Pixel 101 may include: a first transistor T1 connected between a first node N1 and a third node N3 and turned on in response to a first gate signal SCAN1; a second transistor T2 connected between a data line DL of a plurality of data lines and a second node N2 and turned on in response to a second gate signal SCAN2; a third transistor T3 connected between a pixel driving power line VL2 connected to a pixel driving power supply for supplying pixel driving voltage ELVDD and a second node N2 and turned on in response to a light emission signal EMS; a fourth transistor T4 connected between the third node N3 and the anode electrode of the light-emitting element ED and turned on in response to the light emission signal EMS; a fifth transistor T5 disposed between the first initialization voltage line VL1 for transmitting the first initialization voltage Dvini and the third node N3 and turned on in response to a third gate signal SCAN3; and a storage capacitor Cstg connected between the first node N1 and the pixel driving power line VL2.

[0308] Pixel 101 may include a sixth transistor T6 disposed between the anode electrode of the light-emitting element ED and a second initialization power line VL3 for applying a second initialization voltage VAR to the anode electrode of the light-emitting element ED and turned on in response to a third gate signal SCAN3.

[0309] The gate electrode of the first transistor T1 can be connected to the first gate line GL1, and therefore, the first transistor T1 can be turned on / off in response to the first gate signal SCAN1 transmitted through the first gate line GL1. When the first transistor T1 is turned on, the first node N1 and the third node N3 can be electrically connected, and therefore the driving transistor DRT can enter the diode connection state.

[0310] The gate electrode of the second transistor T2 can be connected to the second gate line GL2, and therefore, the second transistor T2 can be turned on / off in response to the second gate signal SCAN2 transmitted through the second gate line GL2. When the second transistor T2 is turned on, the voltage corresponding to the data signal Vdata transmitted through the data line DL can be transmitted to the second node N2.

[0311] The gate electrode of the third transistor T3 can be connected to the light-emitting line EML, and therefore, the third transistor T3 can be turned on / off in response to the light-emitting signal EMS transmitted through the light-emitting line EML. When the third transistor T3 is turned on by the light-emitting signal EMS, the pixel driving power line for supplying the pixel driving voltage ELVDD and the second node N2 can be connected, and therefore, the pixel driving voltage ELVDD can be applied to the second node N2.

[0312] The gate electrode of the fourth transistor T4 can be connected to the light-emitting line EML, and therefore, the fourth transistor T4 can be turned on / off in response to the light-emitting signal EMS transmitted through the light-emitting line EML. When the fourth transistor T4 is turned on by the light-emitting signal EMS, the anode electrode of the third node N3 and the light-emitting element ED can be connected, and therefore, the drive current flowing through the third node N3 can be applied to the light-emitting element ED.

[0313] The gate electrode of the fifth transistor T5 can be connected to the third gate line GL3, and therefore, the fifth transistor T5 can be turned on / off in response to the third gate signal SCAN3 transmitted through the third gate line GL3. When the fifth transistor T5 is turned on by the third gate signal SCAN3, the first initialization voltage Dvini transmitted to the first initialization signal line VL1 can be transmitted to the third node N3. Since the first initialization voltage Dvini has a higher voltage level than the pixel drive voltage ELVDD, when the data signal Vdata is applied to the gate electrode of the drive transistor DRT, the first initialization voltage Dvini can be transmitted to the second node N2 through the drive transistor DRT. Therefore, the second node N2 and the third node N3 can be initialized by the first initialization voltage Dvini.

[0314] The gate electrode of the sixth transistor T6 can be connected to the third gate line GL3, and therefore, the sixth transistor T6 can be turned on / off in response to the third gate signal SCAN3 transmitted through the third gate line GL3. When the sixth transistor T6 is turned on by the third gate signal SCAN3, the second initialization voltage VAR transmitted to the second initialization signal line VL3 can be transmitted to the anode electrode of the light-emitting element ED, and therefore, the voltage of the anode electrode can be initialized by the second initialization pressure VAR.

[0315] The first transistor T1 can be a transistor using oxide semiconductor as an N-type MOS transistor, and the driving transistor DRT and the second to sixth transistors T2 to T6 can be low-temperature polysilicon transistors as P-type MOS transistors. However, embodiments of this disclosure are not limited to these types of transistors.

[0316] Compared to low-temperature polycrystalline silicon (LTPS) transistors, transistors using oxide semiconductors can reduce the amount of leakage current. Conversely, LTPS transistors can have the advantage of higher carrier mobility than transistors using oxide semiconductors.

[0317] Therefore, if the voltage of the first node N1 decreases due to leakage current, and the image quality of the display device may deteriorate, then the first transistor T1 can be a transistor using oxide semiconductor, and the driving transistor DRT and the second to sixth transistors T2 to T6 can be low-temperature polysilicon transistors. Furthermore, in the example where pixel 101 includes transistors using oxide semiconductor, the amount of leakage current can be reduced, which makes it possible to implement the display device 100 in a larger size.

[0318] The first and second electrodes of the storage capacitor Cstg can be connected to the pixel drive power line VL2 and the first node N1 respectively, and the voltage of the first node N1 can be maintained. The pixel drive power line VL2 is connected to the pixel drive power supply for supplying the pixel drive voltage ELVDD.

[0319] Here, the first gate line GL1, the second gate line GL2, the third gate line GL3, and the light-emitting line EML can correspond to the horizontal lines HL1 and HL2 shown in FIG5. However, the embodiments of this disclosure are not limited thereto.

[0320] Figure 12 This illustrates an embodiment. Figure 11 The timing diagram shows the operation of the pixels shown.

[0321] Reference Figure 12 Pixel 101 can operate during different data write periods Tw and emission periods Te. That is, the data write period Tw and the emission period Te do not overlap. The data write period Tw refers to applying or writing the data signal Vdata. Figure 11 The period shown is the time period of the gate electrode of the driving transistor DRT, while the light-emitting period Te refers to the period during which the driving transistor DRT supplies driving current to the light-emitting element ED through the data signal Vdata applied to the gate electrode of the driving transistor DRT.

[0322] According to one implementation, the data writing period Tw may include a first on-bias stress period OBS1, an initialization period Ti, a sensing period Ts, a second on-bias stress period OBS2, and a reset period Tr.

[0323] The first conduction bias stress period OBS1 and the second conduction bias stress period OBS2 can be periods during which a high-level voltage is applied to the drive transistor DRT. Even when the voltage applied to the drive transistor DRT changes, hysteresis problems may occur because the drive current, which varies according to the magnitude of the changing voltage, does not flow. However, if a high-level voltage is applied to the drive transistor DRT, the hysteresis of the drive transistor DRT can be reduced or eliminated.

[0324] During the data write period Tw, no drive current flows to the light-emitting element ED. With the third transistor T3 and the fourth transistor T4 off, the pixel drive power line VL2, connected to the drive power supply and the second node N2, can be electrically disconnected, and the third node N3 and the light-emitting element ED can also be electrically disconnected. Therefore, no current flows from the drive transistor DRT to the light-emitting element ED. Since the third transistor T3 and the fourth transistor T4, connected to the light-emitting line EML, are P-type MOS transistors, these transistors T3 and T4 are turned off when a high-level signal is supplied, and therefore, during the data write period Tw, the light-emitting signal EMS flowing through the light-emitting line EML can be supplied at a high level.

[0325] Furthermore, during the first conduction bias stress period OBS1, the first gate signal SCAN1 and the third gate signal SCAN3 can be at a low level, and the second gate signal SCAN2 can be at a high level. When the first gate signal SCAN1 is at a low level, the first transistor T1 is turned off because it is an N-type MOS transistor. Because the second gate signal SCAN2 is at a high level, the second transistor T2 can be turned off, and therefore, the data signal Vdata transmitted via the data line DL cannot be supplied to the second node N2. Because the third gate signal SCAN3 is at a low level, the fifth transistor T5 can be turned on, and therefore, the first initialization voltage Dvini can be transmitted to the third node N3.

[0326] Since the first initialization voltage Dvini transmitted to the third node N3 is higher than the driving voltage, the first initialization voltage Dvini with the first voltage level V1 can be transmitted from the third node N3 to the second node N2, and therefore, the hysteresis of the driving transistor DRT can be reduced or eliminated by the first initialization voltage Dvini.

[0327] During the initialization period Ti, the first gate signal SCAN1 can be high, the second gate signal SCAN2 can be high, and the third gate signal SCAN3 can be low. When the first gate signal SCAN1 is high, the first transistor T1 can be turned on. When the first transistor T1 is turned on, the first node N1 and the third node N3 can be connected, making the first transistor T1 a diode connection.

[0328] Since the third gate signal SCAN3 is low, the fifth transistor T5 can be turned on, and therefore, the first initialization voltage Dvini can be transmitted to the third node N3. The first initialization voltage Dvini transmitted to the third node N3 can have a second voltage level V2 that is lower than the first voltage level V1, and is transmitted to the first node N1 and the second node N2. Therefore, the first node N1 to the third node N3 can be initialized with the first initialization voltage Dvini having the second voltage level V2.

[0329] During the sensing period Ts, the first gate signal SCAN1 can be at a high level, and the third gate signal SCAN3 can be at a high level. While the first gate signal SCAN1 and the third gate signal SCAN3 remain at high levels, the second gate signal SCAN2 can be at a low level during the 1H period (a horizontal period). Since the first gate signal SCAN1 and the third gate signal SCAN3 are at high levels, the first transistor T1 can be turned on, and the fifth transistor T5 can be turned off.

[0330] When the second gate signal SCAN2 is low, the second transistor T2 is turned on, and the data signal Vdata flowing through the data line DL can be transmitted to the second node N2. At this time, since the first transistor T1 remains on, current can flow from the second node N2 to the third node N3 through the data signal Vdata applied to the second node N2, and the voltage corresponding to the current flowing from the second node N2 to the third node N3 can be applied to or written to the first node N1. The voltage applied to or written to the second node N2 can be a voltage corresponding to the data signal Vdata and the threshold voltage of the driving transistor DRT.

[0331] During the second conduction bias stress period OBS2, the first gate signal SCAN1 and the third gate signal SCAN3 can be at a low level, and the second gate signal SCAN2 can be at a high level. The first transistor T1 can be turned off by the first gate signal SCAN1, and the second transistor T2 can be turned off by the second gate signal SCAN2. The fifth transistor T5 can be turned on by the third gate signal SCAN3.

[0332] When the first gate signal SCAN1 is low, the first transistor T1 is turned off. Since the second gate signal SCAN2 is high, the second transistor T2 can be turned off, and therefore, the data signal Vdata transmitted via the data line DL cannot be supplied to the second node N2. Since the fifth transistor T5 is on, the first initialization voltage Dvini can be transmitted to the third node N3. Because the first initialization voltage Dvini transmitted to the third node N3 is higher than the pixel drive voltage ELVDD, the first initialization voltage Dvini with a first level V1 transmitted to the third node N3 can be transmitted to the second node N2. Therefore, when the first initialization voltage Dvini is applied to both the second node N2 and the third node N3, the hysteresis of the first transistor T1 can be reduced or eliminated.

[0333] In particular, when the display device 100 is driven at a relatively low frequency, the period of voltage change applied to the driving transistor DRT is very long, and therefore, the effect of reducing or eliminating the hysteresis of the driving transistor DRT by applying the first initialization voltage Dvini during the first conduction bias stress period OBS1 and the second conduction bias stress period OBS2 can be more significant. Furthermore, when the display device 100 is driven at a low frequency, the power consumption of the display device 100 can be reduced.

[0334] During the second conduction bias stress period OBS2, when the first initialization voltage Dvini is applied to the second node N2, the voltage of the second node N2 can have a level higher than the pixel drive voltage ELVDD. When the light emission period Te begins when the voltage of the second node N2 has a level higher than the pixel drive voltage ELVDD, the third transistor T3 and the fourth transistor T4 can be turned on by the light emission signal EMS, and the first transistor T1 enables the drive current, which compensates for the threshold voltage of the first transistor T1 by the data signal Vdata stored in the first node N1 and the voltage corresponding to the threshold voltage of the first transistor T1, to flow from the second node N2 to the third node N3, thereby causing the drive current to flow through the light-emitting element ED.

[0335] When the third transistor T3 is turned on, and the power line VL2, which supplies the pixel drive voltage ELVDD, is connected to the second node N2, the voltage of the second node N2 can decrease from a first voltage level higher than the pixel drive voltage ELVDD (the initialization voltage Dvini) to the voltage level of the pixel drive voltage ELVDD. In this case, it takes time for the voltage of the second node N2 to reach such a level (i.e., decrease).

[0336] However, if the light-emitting period Te is initiated without a sufficient reduction in the voltage of the second node N2, the voltage of the second node N2 can be maintained at a level higher than the pixel driving voltage ELVDD during the light-emitting period Te, which is the period in which driving current is supplied to the light-emitting element ED. Therefore, the voltage difference between the pixel driving voltage ELVDD and the base voltage ELVSS can increase, and consequently, the amount of driving current flowing to the light-emitting element ED can increase. In particular, when the pixel displays low grayscale, the amount of driving current increases, and therefore, there is a possibility that it may display a brightness higher than expected.

[0337] To address these issues, it is desirable to initialize the second node N2 and the third node N3 to voltage levels corresponding to the pixel driving voltage ELVDD during the emission period Te. Therefore, after the second conduction bias stress period OBS2, a reset period Tr can be executed to initialize the second node N2 and the third node N3 to the voltage levels of the pixel driving voltage ELVDD.

[0338] The first initialization voltage Dvini can have a voltage level between a first voltage level V1 and a second voltage level V2. The first initialization voltage Dvini can have a first voltage level V1 in a first time period T1, a third voltage level V3 (between the first and second voltage levels V1 and V2) in a second time period T2 following the first time period T1, and a second voltage level V2 in a third time period T3 following the second time period T2. The first time period T1 can overlap with the second OBS time period OBS2, and the second time period T2 can overlap with the reset time period Tr.

[0339] Therefore, during the reset period Tr, the voltage level of the first initialization voltage Dvini transmitted to the second node N2 and the third node N3 can have a third voltage level V3 corresponding to the voltage level of the pixel driving voltage ELVDD. Thus, the second node N2 and the third node N3 have the same voltage level as the pixel driving voltage ELVDD, and therefore, an increase in the amount of driving current flowing through the pixel 101 can be prevented or at least reduced. Furthermore, the image quality of the display device 100 can be improved.

[0340] Furthermore, since the second node N2 and the third node N3 can be reset to the voltage level of the pixel driving voltage ELVDD without adding separate signal lines to the pixel 101, even if the second node N2 and the third node N3 are reset, the reduction in the aperture ratio of the display device 100 can be prevented or reduced, and the design of the pixel 101 can be simplified. In particular, even when no additional lines are provided in the pixel 101 of the display device 100, the reduction in aperture ratio such as… Figures 1A to 1CThe aperture ratio decreases in each optical region (OA1, OA2) shown.

[0341] Since the sixth transistor T6 is turned on / off in response to the third gate signal SCAN3, a second initialization voltage Var for initializing the anode electrode of the light-emitting element ED can be supplied during the first OBS period OBS1, the second OBS period OBS2, and the reset period Tr, and thus, the anode electrode of the light-emitting element ED can be initialized by the second initialization voltage Var.

[0342] Figure 13 An embodiment is shown. Figure 9 The configuration of the first power supply circuit shown.

[0343] Reference Figure 13 The first power supply circuit 910 may include multiple stages 1301 to 1304. Each of the multiple stages 1301 to 1304 may correspond to Figure 10 The stage 1000b is shown. Multiple stages 1301 to 1304 can generate first initialization voltages (Dvini[n-1], Dvini[n], Dvini[n+1], Dvini[n+2]) and carry signals (Carry_Vini[n-1], Carry_Vini[n], Carry_Vini[n+1], Carry_Vini[n+2]) that are output sequentially respectively.

[0344] Each of the multiple stages 1301 to 1304 can receive a drive voltage VDD, which has: a high voltage VGH with a first voltage level V1, a low voltage VGL with a second voltage level V2, and a drive voltage with a third voltage level V3. Each of the multiple stages 1301 to 1304 can output a first initialization voltage Dvini, such that the voltage level of the first initialization voltage Dvini sequentially has the first voltage level V1, the third voltage level V3, and the second voltage level V2. The voltage level of the drive voltage VDD can be... Figure 11 The pixel driving voltage ELVDD shown is the same.

[0345] Furthermore, the first initialization voltage Dvini supplied from the first power supply circuit 910 may include the (n-1)th first initialization voltage Dvini[n-1], the nth first initialization voltage Dvini[n], the (n+1)th first initialization voltage Dvini[n+1], and the (n+2)th first initialization voltage Dvini[n+2] output sequentially. Furthermore, the (n-1)th first initialization voltage (Dvini[n-1]) can refer to the first initialization voltage transmitted to the pixel receiving the data signal in response to the gate signal transmitted through the (n-1)th gate line among the plurality of gate lines; the nth first initialization voltage (Dvini[n]) can refer to the first initialization voltage transmitted to the pixel receiving the data signal in response to the gate signal transmitted through the nth gate line among the plurality of gate lines; the (n+1)th first initialization voltage (Dvini[n+1]) can refer to the first initialization voltage transmitted to the pixel receiving the data signal in response to the gate signal transmitted through the (n+1)th gate line among the plurality of gate lines; and the (n+2)th first initialization voltage (Dvini[n+2]) can refer to the first initialization voltage transmitted to the pixel receiving the data signal in response to the gate signal transmitted through the (n+2)th gate line among the plurality of gate lines.

[0346] The first power supply circuit 910 may include a (n-1)th stage 1301 for outputting the (n-1)th carry signal Carry_Vini[n-1] and the (n-1)th first initialization voltage Dvini[nl], an nth stage 1302 for outputting the nth carry signal Carry_Vini[n] and the nth first initialization voltage Dvini[n], an (n+1)th stage 1303 for outputting the (n+1)th carry signal Carry_Vini[n+1] and the (n+1)th first initialization voltage Dvini[n+1], and an (n+2)th stage 1304 for outputting the (n+2)th carry signal Carry_Vini[n+2] and the (n+2)th first initialization voltage Dvini[n+2].

[0347] The nth stage 1302 can output the nth first initialization voltage Dvini[n] with the first voltage level V1 in response to the (n-1)th carry signal Carry_Vini[n-1] in the first time period T1, and output the nth first initialization voltage Dvini[n] with the third voltage level V3 corresponding to the driving voltage VDD in response to the (n+2)th carry signal Carry_Vini[n+2] in the second time period T2.

[0348] Figure 14 and Figure 15 According to one implementation method Figure 13 The circuit diagram for the nth stage is shown below.

[0349] Reference Figure 14 and Figure 15 The nth stage 1302 may include: a first switch SW1, which includes a first electrode, a second electrode, and a gate electrode, and can be connected to a first low voltage supply for supplying a first low voltage VGL1, an output node No, and a Q node Q, respectively, and applies the first low voltage VGL1 to the first output node No through the voltage of the Q node Q according to the (n-1)th carry signal Carry_Vini[n-1]; a second switch SW2, which includes a first electrode, a second electrode, and a gate electrode, and can be connected to a first high voltage supply for supplying a first high voltage VGH1, an output node No, and a QB node QB, respectively, and applies the first high voltage VGH1 to the output node No through the voltage of the QB node QB according to the (n-1)th carry signal Carry_Vini[n-1]; and a third switch Sw3, which includes a first electrode, a second electrode, and a gate electrode, and can be connected to the first high voltage supply for supplying a first high voltage VGH1, an output node No, and a QB node QB, respectively, and applies the first high voltage VGH1 to the output node No through the voltage of the QB node QB; and a third switch Sw3, which includes a first electrode, a second electrode, and a gate electrode, and can be connected to the first high voltage supply for supplying a first high voltage VGH1, an output node No, and a QB node QB, respectively. The system includes a first switch SW4, a second switch SW5, a fifth switch SW5, a sixth switch SW6, a seventh switch SW6, a suffix SW6, a suffix SW6, a suffix SW6, a suffix SW6, a suffix SW6, a suffix SW6, a suffix SW6, a suffix SW6, a suffix SW6, a sixth switch SW6, a seventh switch SW6, a eighth switch SW6, a ninth switch SW6, a suffix ... tenth switch SW6, a suffix SW6, a tenth switch SW6, a suffix SW6, a tenth switch SW6, a suffix SW6, a tenth switch SW6, a suffix SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6, a tenth switch SW6,

[0350] The nth initialization voltage Dvini[n] can be output to the first output terminal OUT1, and the nth carry signal Carry_Vini[n] can be output to the second output terminal OUT2.

[0351] The first high voltage VGH1 can correspond to the first voltage level V1 of the first initialization voltage Dvini, and the first low voltage VGL1 can correspond to the second voltage level V2 of the second initialization voltage Dvini. The driving voltage VDD can correspond to the third voltage level V3 of the first initialization voltage Dvini.

[0352] exist Figure 14 In this circuit, the fourth switch SW4 can receive the (n+2)th carry signal Carry_Vini[n+2] via the inverter INV, and thus operate in the opposite manner to the third switch SW3. Furthermore, in Figure 15 In this configuration, the first switches SW1 through SW3, the fifth switch SW5, and the sixth switch SW6 can be P-type MOS transistors, and the fourth switch SW4 can be an N-type MOS transistor. Therefore, even if the third switch SW3 and the fourth switch SW4 receive the same (n+2)th carry signal Carry_Vini[n+2], the fourth switch SW4 can operate in the opposite manner to the third switch SW3. For example, when the third switch SW3 is on, the fourth switch SW4 can be off, and when the third switch SW3 is off, the fourth switch SW4 can be on.

[0353] Furthermore, stage n 1302 may include a first capacitor CB disposed between node Q and output node No, a second capacitor CQB disposed between node QB and a high-voltage supply for supplying a first high voltage VGH1, and a third capacitor CBUF disposed between output node No and a low-voltage supply for supplying a second low voltage VGL2. The voltage at node Q can be maintained by the first capacitor CB. The voltage at node QB can be maintained by the second capacitor CQB. The voltage difference between output node No and the second low-voltage supply can be maintained by the third capacitor CBUF.

[0354] Furthermore, the nth stage 1302 may include the seventh switch SW7 to the eleventh switch SW11. The seventh switch SW7 and the eighth switch SW8 may be connected in series between the input terminal with the (n-1)th carry signal Carry_Dvini[n-1] and the Q node Q, so that the (n-1)th carry signal Carry_Dvini[n-1] can be supplied to the Q node Q.

[0355] The clock signal GCLK can be supplied to the gate electrode of the seventh switch SW7, and therefore, the seventh switch SW7 can be turned on / off in response to the clock signal GCLK.

[0356] The eighth switch SW8 can be turned on by the first low voltage VGL1.

[0357] The ninth switch SW9 can be positioned between the gate electrode of the seventh switch SW7 and the QB node QB. The tenth switch SW10 can be connected between the QB node QB and the high voltage supply used to supply the first high voltage VGH1, and its gate electrode can be connected between the seventh switch SW7 and the eighth switch SW8. The eleventh switch SW11 can be positioned between the first high voltage supply and the gate electrode of the ninth switch SW9, and the clock signal input terminal with the clock signal GCLK can be connected to the gate electrode of the eleventh switch SW11. Furthermore, the fourth capacitor C_ON can be positioned between the gate electrode of the ninth switch SW9 and the clock signal input terminal.

[0358] Here, the voltage levels of the first high voltage VGH1 and the second high voltage VGH2 can be different from each other. Similarly, the voltage levels of the first low voltage VGL1 and the second low voltage VGL2 can be different from each other. However, embodiments of this disclosure are not limited thereto. In some embodiments, the first high voltage VGH1, the second high voltage VGH2, and the first low voltage VGL1 and the second low voltage VGL2 can be derived from... Figure 9 The second power supply circuit 920 shown supplies power to the first power supply circuit 910.

[0359] Figure 16 It is shown Figure 14 or Figure 15 The timing diagram of the operations of the stage shown is shown.

[0360] Reference Figure 16 In the first time period T11, the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n] can be high, and the (n+2)th carry signal Carry_Dvini[n+2] can be low. With the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n], the second switch SW2, the seventh switch SW7, the ninth switch SW9, the tenth switch SW10, and the eleventh switch SW11 can be turned off, and the fifth switch SW5 can be turned on. With the (n+2)th carry signal Carry_Dvini[n+2] being low, the third switch SW3 can be turned on, and the fourth switch SW4 can be turned off. The eighth switch SW8 can be turned on.

[0361] Therefore, the first low voltage VGL1 supplied from the first low voltage supply can be output to the first output terminal OUT1 through the first switch SW1 and the third switch SW3, and thus, the first initialization voltage Dvini[n] can have a second voltage level V2. Furthermore, the second low voltage VGL2 supplied from the second low voltage supply can be output to the second output terminal OUT2 through the fifth switch SW5, and thus, the nth carry signal Carry_Dvini[n] can have a low level.

[0362] In the second time period T12, the (n-1)th carry signal Carry_Dvini[n-1] can be high, the (n+2)th carry signal Carry_Dvini[n+2] can be low, and the clock signal GCLK[n] can be low. With the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n], the first switch SW1, the fifth switch SW5, the seventh switch SW7, the tenth switch SW10, and the eleventh switch SW11 can be turned off, and the second switch SW2, the sixth switch SW6, and the ninth switch SW9 can be turned on. With the (n+2)th carry signal Carry_Dvini[n+2] being low, the third switch SW3 can be turned on, and the fourth switch SW4 can be turned off. The eighth switch SW8 can be turned on.

[0363] Therefore, the first high voltage VGH1 supplied from the first high voltage supply can be output to the first output terminal OUT1 through the second switch SW2 and the third switch SW3, and thus, the first initialization voltage Dvini[n] can have a first voltage level V1. Furthermore, the first high voltage VGH1 supplied from the first high voltage supply can be output to the second output terminal OUT2 through the sixth switch SW6, and thus, the nth carry signal Carry_Dvini[n] can be output at a high level.

[0364] In the third time period T13, the (n-1)th carry signal Carry_Dvini[n-1] can be low, the (n+2)th carry signal Carry_Dvini[n+2] can be low, and the clock signal GCLK[n] can be high. Through the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n], the first switch SW1, the fifth switch SW5, the seventh switch SW7, the ninth switch SW9, and the tenth switch SW10 can be turned off, and the second switch SW2, the sixth switch SW6, and the eleventh switch SW11 can be turned on. Through the (n+2)th carry signal Carry_Dvini[n+2] which is low, the third switch SW3 can be turned on, and the fourth switch SW4 can be turned off. The eighth switch SW8 can be turned on.

[0365] Therefore, the first high voltage VGH1 provided from the first high voltage supply can be output to the first output terminal OUT1 through the second switch SW2 and the third switch SW3, and thus, the first initialization voltage Dvini[n] can have a first voltage level V1. Furthermore, the second high voltage VGH2 provided from the second high voltage supply can be output to the second output terminal OUT2 through the sixth switch SW6, and thus, the nth carry signal Carry_Dvini[n] can have a high level.

[0366] In the fourth time period T14, the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n] can be low, and the (n+2)th carry signal Carry_Dvini[n+2] can be high. With the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n], the second switch SW2, the sixth switch SW6, and the ninth switch SW9 can be turned off, and the first switch SW1, the fifth switch SW5, the seventh switch SW7, and the tenth switch SW10 can be turned on. With the (n+2)th carry signal Carry_Dvini[n+2] being high, the third switch SW3 can be turned off, and the fourth switch SW4 can be turned on. The eighth switch SW8 can be turned on.

[0367] Therefore, although the first low voltage VGL1 supplied from the first low voltage supply is transmitted to the output node No through the first switch SW1, the first low voltage VGL1 cannot be output to the first output terminal OUT1 because the third switch SW3 is turned off. However, because the fourth switch SW4 is turned on, the drive voltage VDD can be transmitted to the first output terminal OUT1 through the fourth switch SW4, and therefore, the first initialization voltage Dvini[n] can have the third voltage level V3, which is the voltage level of the drive voltage VDD. In addition, the second low voltage VGL2 supplied from the second low voltage supply can be output to the second output terminal OUT2 through the fifth switch SW5, and therefore, the nth carry signal Carry_Dvini[n] can be output at a low level.

[0368] In the fifth time period T15, the (n-1)th carry signal Carry_Dvini[n-1] can be low, and the clock signal GCLK[n] and the (n+2)th carry signal Carry_Dvini[n+2] can be high. With the (n-1)th carry signal Carry_Dvini[n-1] and the clock signal GCLK[n], the second switch SW2, the sixth switch SW6, the seventh switch SW7, and the ninth switch SW9 can be turned off, and the first switch SW1, the fifth switch SW5, the tenth switch SW10, and the eleventh switch SW11 can be turned on. With the (n+2)th carry signal Carry_Dvini[n+2] being high, the third switch SW3 can be turned off, and the fourth switch SW4 can be turned on. The eighth switch SW8 can be turned on.

[0369] Therefore, the first low voltage VGL1 supplied from the first low voltage supply can be transmitted to the output node No through the first switch SW1. However, since the third switch SW3 is off, the first low voltage VGL1 cannot be output through the first output terminal OUT1. However, since the fourth switch SW4 is on, the drive voltage VDD can be transmitted to the first output terminal OUT1 through the fourth switch SW4, and therefore, the first initialization voltage Dvini[n] can have the third voltage level V3, which is the voltage level of the drive voltage VDD. In addition, the second low voltage VGL2 supplied from the second low voltage supply can be output to the second output terminal OUT2 through the fifth switch SW5, and therefore, the nth carry signal Carry_Dvini[n] can be output at a low level.

[0370] As described above, the nth carry signal Carry_Dvini[n] has a second voltage level V2 in the first time period T11, a first voltage level V1 in the second time period T12 and the third time period T13, and a third voltage level V3 in the fourth time period T14 and the fifth time period T15. When the fifth time period T15 has passed, the nth carry signal Carry_Dvini[n] again has the second voltage level V2.

[0371] Therefore, the nth first initialization voltage Dvini[n] has a voltage level between the first voltage level V1 and the second voltage level V2, and gradually decreases in the order of the first voltage level V1, the third voltage level V3, and the second voltage level V2. Furthermore, by configuring the reset period Tr and the period in which the nth first initialization voltage Dvini[n] has the third voltage level V3 to overlap, after the second conduction bias stress period OBS2, the second node N2 and the third node N3 of the pixel can be reset to the nth first initialization voltage Dvini[n] with the third voltage level V3.

[0372] Furthermore, in stage n 1302, during the first time period T11, the nth first initialization voltage Dvini[n] can be output at a first voltage level V1 corresponding to a high voltage, based on the voltages of Q node Q and QB node QB; during the second time period T12, the nth first initialization voltage Dvini[n] can be output at a third voltage level V3 corresponding to the driving voltage VDD, based on the voltages of Q node Q and QB node QB; and during the third time period T13, the nth first initialization voltage Dvini[n] can be output at a second voltage level V2, based on the voltages of Q node Q and QB node QB. For example, when the voltage of Q node Q is positive, the voltage of QB node QB can be negative, and when the voltage of Q node Q is negative, the voltage of QB node QB can be positive.

[0373] The foregoing description has been presented to enable any person skilled in the art to make and use the technical concepts of the invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and figures provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be understood based on the appended claims, and all technical concepts within the scope of their equivalents should be understood to be included within the scope of the invention.

Claims

1. A display device, comprising: The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of first initialization power lines, a plurality of power lines, and a plurality of pixels connected to the plurality of gate lines, the plurality of data lines, the plurality of first initialization power lines, and the plurality of power lines, the plurality of pixels being configured to emit light during the light emission period of the display device; A data driving circuit configured to supply data signals to the plurality of data lines; A gate driving circuit configured to supply gate signals to the plurality of gate lines; A first power supply circuit is configured to supply a first initialization voltage to the plurality of first initialization power lines, the first initialization voltage having a voltage level that varies between a first voltage level and a second voltage level; as well as A second power supply circuit is configured to supply pixel driving voltage to a plurality of pixel driving power lines among the plurality of power lines. Wherein, at least one pixel among the plurality of pixels includes: A driving transistor, configured to cause a driving current to flow from a second node to a third node in response to a voltage applied to a first node corresponding to a data signal; and A light-emitting element, which emits light in response to the driving current, and Wherein, when the light-emitting element does not emit light before the light-emitting period, a voltage corresponding to the data signal is applied to the first node, and then the second node and the third node are initialized using the first initialization voltage. The first initialization voltage has the first voltage level in the first period, a third voltage level between the first voltage level and the second voltage level in the second period after the first period, and the second voltage level in the third period after the second period.

2. The display device according to claim 1, wherein, The at least one pixel generates the driving current in response to the pixel driving voltage and the voltage of the first node, and the third voltage level of the first initialization voltage matches the voltage level of the pixel driving voltage.

3. The display device according to claim 1, wherein, The at least one pixel also includes: A first transistor is connected between the first node and the third node, and the first transistor is turned on in response to a first gate signal; A second transistor is connected between one of the plurality of data lines and the second node, and the second transistor is turned on in response to a second gate signal; A third transistor is connected between the second node and the pixel driving power line, the pixel driving power line being connected to the pixel driving power supply, and the third transistor is turned on in response to a light emission signal; A fourth transistor is connected between the third node and the anode electrode of the light-emitting element, and the fourth transistor is turned on in response to the light-emitting signal; A fifth transistor is disposed between the third node and the first initialization voltage line transmitting the first initialization voltage, the fifth transistor being turned on in response to a third gate signal; and A storage capacitor connected between the first node and the pixel driving power line.

4. The display device according to claim 3, wherein, In response to the third gate signal, the fifth transistor turns on before the data signal is applied to the first node, and the fifth transistor turns on after the data signal is applied to the first node. When the data signal is applied to the first node, the first transistor is turned off.

5. The display device according to claim 3, wherein, The pixels also include: A sixth transistor is disposed between the anode electrode of the light-emitting element and the second initialization power line. When the sixth transistor is turned on, the second initialization power line applies a second initialization voltage to the anode electrode of the light-emitting element. The sixth transistor is turned on in response to the third gate signal.

6. The display device according to claim 1, wherein, The first power supply circuit includes multiple stages, each of which is configured to receive a first high voltage having the first voltage level, a first low voltage having the second voltage level, and a drive voltage having the third voltage level, and to supply the first initialization voltage such that the first initialization voltage sequentially has the first voltage level, the third voltage level, and the second voltage level.

7. The display device according to claim 6, wherein, The first initialization voltage includes the (n-1)th first initialization voltage, the nth first initialization voltage, the (n+1)th first initialization voltage, and the (n+2)th first initialization voltage that are output sequentially. The plurality of stages include: a stage (n-1) configured to output the (n-1)th carry signal and the (n-1)th first initialization voltage; an nth stage configured to output the nth carry signal and the nth first initialization voltage; a stage (n+1) configured to output the (n+1)th carry signal and the (n+1)th first initialization voltage; and a stage (n+2) configured to output the (n+2)th carry signal and the (n+2)th first initialization voltage. The nth stage is configured to receive the (n-1)th carry signal and the (n+2)th carry signal, and is configured to output the nth carry signal and the nth first initialization voltage. Specifically, the nth first initialization voltage is output such that, in the first time period, the nth first initialization voltage with the first voltage level is output in response to the (n-1)th carry signal, and in the second time period, the nth first initialization voltage with the third voltage level corresponding to the driving voltage is output in response to the (n+2)th carry signal.

8. The display device according to claim 7, wherein, The nth stage is configured to operate such that, during the first time period, the nth first initialization voltage is output at a first voltage level corresponding to the first high voltage based on the voltages of the Q node and the QB node; during the second time period, the nth first initialization voltage is output at a third voltage level corresponding to the drive voltage based on the voltages of the Q node and the QB node; and during the third time period, the nth first initialization voltage is output at a second voltage level corresponding to the first low voltage based on the voltages of the Q node and the QB node. The nth level includes: A first switch, comprising a first electrode, a second electrode, and a gate electrode of the first switch respectively connected to a first low-voltage supply, an output node, and a Q node, and configured to apply the first low voltage to a first output node based on the voltage of the Q node according to the (n-1)th carry signal; and The second switch includes a first electrode, a second electrode, and a gate electrode of the second switch, respectively connected to a first high voltage supply supplying a first high voltage, the output node, and the QB node, and the second switch is configured to apply the first high voltage to the output node through the voltage of the QB node according to the (n-1)th carry signal.

9. The display device according to claim 7, wherein, The nth level includes: A first switch includes a first electrode, a second electrode, and a gate electrode of the first switch, respectively connected to a first low voltage supply, an output node, and a Q node, and the first switch is configured to apply the first low voltage to the first output node through the voltage of the Q node according to the (n-1)th carry signal. The second switch includes a first electrode, a second electrode, and a gate electrode of the second switch, which are respectively connected to a first high voltage supply supplying the first high voltage, the output node, and the QB node, and the second switch is configured to apply the first high voltage to the output node through the voltage of the QB node according to the (n-1)th carry signal. The third switch includes a first electrode, a second electrode, and a gate electrode of the third switch, which are respectively connected to the output node, the first output terminal, and the carry signal line supplying the (n+2)th carry signal. The fourth switch includes a first electrode, a second electrode, and a gate electrode of the fourth switch, which are respectively connected to a drive power supply that supplies the drive voltage, the first output terminal, and the carry signal line that supplies the (n+2)th carry signal. The fourth switch is configured to be turned on when the third switch is turned off and to be turned off when the third switch is turned on. A fifth switch, comprising a first electrode, a second electrode, and a gate electrode of the fifth switch respectively connected to a second low-voltage supply, a second output terminal, and the output node; and The sixth switch includes a first electrode, a second electrode, and a gate electrode of the sixth switch, which are respectively connected to a second high voltage supply supplying a second high voltage, the second output terminal, and the QB node.

10. The display device according to claim 9, wherein, The fourth switch receives the (n+2)th carry signal via an inverter.

11. The display device according to claim 9, wherein, The third switch includes a P-type metal-oxide-semiconductor (MOS) transistor, and the fourth switch includes an N-type MOS transistor.

12. The display device according to claim 1, wherein, The display panel includes: The display area includes a first optical area and a normal area. The first optical area includes a first plurality of light-emitting areas and a plurality of transmissive areas. The normal area is located outside the first optical area and includes a second plurality of light-emitting areas. Non-display area; and A first optical electronic device located on the rear surface or lower part of the display panel, the first optical electronic device overlapping with at least a portion of the first optical region included in the display area.

13. A power supply device, comprising: Multiple stages are configured to generate a first initialization voltage and a carry signal, which are sequentially output by each of the multiple stages. The first initialization voltage output from each of the plurality of stages has a voltage level between a first voltage level and a second voltage level, and has the first voltage level in a first time period, a third voltage level between the first voltage level and the second voltage level in a second time period after the first time period, and the second voltage level in a third time period after the second time period. The first initialization voltage includes the (n-1)th first initialization voltage, the nth first initialization voltage, the (n+1)th first initialization voltage, and the (n+2)th first initialization voltage output sequentially. The plurality of stages include: a stage (n-1) configured to output the (n-1)th carry signal and the (n-1)th first initialization voltage; an nth stage configured to output the nth carry signal and the nth first initialization voltage; a stage (n+1) configured to output the (n+1)th carry signal and the (n+1)th first initialization voltage; and a stage (n+2) configured to output the (n+2)th carry signal and the (n+2)th first initialization voltage. The nth stage is configured to receive the (n-1)th carry signal and the (n+2)th carry signal, and is configured to output the nth carry signal and the nth first initialization voltage. Specifically, the nth first initialization voltage is output such that, in the first time period, the nth first initialization voltage with the first voltage level is output in response to the (n-1)th carry signal, and in the second time period, the nth first initialization voltage with the third voltage level corresponding to the driving voltage is output in response to the (n+2)th carry signal.

14. The power supply device according to claim 13, wherein, The nth stage is configured to operate such that, during the first time period, the nth first initialization voltage is output at a first voltage level corresponding to a high voltage based on the voltages of the Q node and the QB node; during the second time period, the nth first initialization voltage is output at a third voltage level corresponding to the drive voltage based on the voltages of the Q node and the QB node; and during the third time period, the nth first initialization voltage is output at a second voltage level based on the voltages of the Q node and the QB node. The nth level includes: A first switch, comprising a first electrode, a second electrode, and a gate electrode of the first switch respectively connected to a first low-voltage supply, an output node, and a Q node, and configured to apply the first low voltage to a first output node based on the voltage of the Q node according to the (n-1)th carry signal; and The second switch includes a first electrode, a second electrode, and a gate electrode of the second switch, respectively connected to a first high voltage supply supplying a first high voltage, the output node, and the QB node, and the second switch is configured to apply the first high voltage to the output node through the voltage of the QB node according to the (n-1)th carry signal.

15. The power supply device according to claim 13, wherein, The nth level includes: A first switch includes a first electrode, a second electrode, and a gate electrode of the first switch, respectively connected to a first low voltage supply, an output node, and a Q node, and the first switch is configured to apply the first low voltage to the first output node through the voltage of the Q node according to the (n-1)th carry signal. The second switch includes a first electrode, a second electrode, and a gate electrode of the second switch, which are respectively connected to a first high voltage supply supplying a first high voltage, the output node, and the QB node, and the second switch is configured to apply the first high voltage to the output node through the voltage of the QB node according to the (n-1)th carry signal. The third switch includes a first electrode, a second electrode, and a gate electrode of the third switch, which are respectively connected to the output node, the first output terminal, and the carry signal line supplying the (n+2)th carry signal. The fourth switch includes a first electrode, a second electrode, and a gate electrode of the fourth switch, which are respectively connected to a drive power supply that supplies the drive voltage, the first output terminal, and the carry signal line that supplies the (n+2)th carry signal. The fourth switch is configured to be turned on when the third switch is turned off and to be turned off when the third switch is turned on. A fifth switch, comprising a first electrode, a second electrode, and a gate electrode of the fifth switch respectively connected to a second low-voltage supply, a second output terminal, and the output node; and The sixth switch includes a first electrode, a second electrode, and a gate electrode of the sixth switch, which are respectively connected to a second high voltage supply supplying a second high voltage, the second output terminal, and the QB node. The fourth switch receives the (n+2)th carry signal via an inverter, and The third switch includes a P-type metal-oxide-semiconductor (MOS) transistor, and the fourth switch includes an N-type MOS transistor.

16. The power supply device according to claim 13, wherein, The first initialization voltage is applied to the second and third nodes of the driving transistor included in the pixel to initialize the second and third nodes. Simultaneously, the light-emitting element included in the pixel does not emit light before the pixel's light-emitting period. The second node of the driving transistor is configured to be electrically connected between the data line to which the data signal is applied and the pixel driving power line to which the pixel driving voltage is applied, and the third node of the driving transistor is electrically connected to the light-emitting element. The third node and the second node are initialized after the voltage corresponding to the data signal is applied to the first node of the driving transistor.

17. A pixel, comprising: A driving transistor includes a first node, a second node, and a third node, the second node being configured to be electrically connected between a data line to which a data signal is applied and a pixel driving power line to which a pixel driving voltage is applied, the driving transistor being configured to cause a driving current to flow from the second node to the third node in response to the data signal applied to the first node; as well as A light-emitting element, electrically connected to the third node of the driving transistor, is configured to emit light in response to the driving current. Wherein, when the light-emitting element does not emit light before the light-emitting period of the pixel, after the data signal is applied to the first node of the driving transistor, a first initialization voltage is applied to the second node and the third node of the driving transistor to initialize the second node and the third node. The first initialization voltage has a first voltage level in the first period, a third voltage level between the first voltage level and the second voltage level in the second period after the first period, and the second voltage level in the third period after the second period.

18. The pixel according to claim 17, wherein, The first voltage level of the first initialization voltage is greater than the pixel driving voltage, the third voltage level of the first initialization voltage is substantially matched with the pixel driving voltage, and the second voltage level is less than the third voltage level.

19. The pixel of claim 17, further comprising: A first transistor is connected between the first node and the third node, and the first transistor is turned on in response to a first gate signal; A second transistor is connected between the data line and the second node, and the second transistor is turned on in response to a second gate signal; A third transistor is connected between the second node and the pixel driving power line, and the third transistor is turned on in response to the light emission signal; A fourth transistor is connected between the third node and the anode electrode of the light-emitting element, the fourth transistor being turned on in response to the light-emitting signal to electrically connect the driving transistor to the light-emitting element; A fifth transistor is disposed between the third node and the first initialization voltage line that transmits the first initialization voltage, the fifth transistor being turned on in response to a third gate signal; as well as A storage capacitor connected between the first node and the pixel driving power line.

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