Semiconductor structure manufacturing method and semiconductor structure

Abstract

The embodiments of the present application belong to the field of semiconductor manufacturing technology, and specifically relate to a semiconductor structure manufacturing method and a semiconductor structure. The embodiments of the present application are used to solve the problem in the related art that the matching structures on the array area and the peripheral area substrate need to be manufactured separately, resulting in low production efficiency. The manufacturing method includes: providing a substrate, the substrate including an array area and a peripheral area; forming a first mask layer covering the array area and the peripheral area on the substrate, the first mask layer having a first device structure pattern facing the array area, and a second device structure pattern facing the peripheral area. Through the semiconductor structure manufacturing method, a first mask layer having a first device structure pattern and a second device structure pattern is first formed on the substrate, and the substrate is etched using the first device structure pattern and the second device structure pattern as masks, so as to simultaneously form a peripheral area structure and an array area structure on the substrate, which simplifies the process flow, reduces the difficulty of manufacturing, and is conducive to improving production efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure manufacturing method and a semiconductor structure. Background Art

[0002] A semiconductor structure (such as a memory) includes a substrate and a device layer disposed on the substrate. The semiconductor structure also includes a peripheral region and an array region adjacent to the peripheral region. Corresponding MOS transistors (Metal Oxide Semiconductor Field Effect Transistors) are disposed in the array region and the corresponding device layers in the peripheral region. The substrates of the array region and the peripheral region have mating structures that mate with the corresponding device layers. During fabrication, the mating structures of the array region and the peripheral region are fabricated separately, and then the device layer is formed to complete the fabrication of the semiconductor structure.

[0003] However, in the related art, the matching structures on the array region and the peripheral region substrate need to be manufactured separately, resulting in low production efficiency. Summary of the Invention

[0004] Embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] According to some embodiments, the first aspect of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate, the first mask layer having a first device structure pattern located above the array region, and a second device structure pattern located above the peripheral region; etching the substrate using the first device structure pattern and the second device structure pattern as masks to form a peripheral region structure and an array region structure, respectively.

[0006] In some embodiments of the present disclosure, a first mask layer covering the array region and the peripheral region is formed on the substrate, wherein the first mask layer has a first device structure pattern facing the array region and a second device structure pattern facing the peripheral region, including:

[0007] forming a first dielectric layer on the first mask layer and the first mask pattern,

[0008] forming a second mask layer on the first dielectric layer;

[0009] forming a second mask pattern on the array region; and forming a second device structure pattern on the first mask layer using the second mask pattern as a mask;

[0010] forming a third mask layer on the second device structure pattern;

[0011] A third mask pattern is formed on the peripheral region; and a first device structure pattern is formed on the first mask layer using the third mask pattern as a mask.

[0012] In some embodiments of the present disclosure, the first mask layer includes a first-first mask layer and a first-second mask layer, wherein the first-first mask layer is located above the first-second mask layer.

[0013] Using the second mask pattern as a mask, etching the first mask layer on the array area to form a second device structure pattern;

[0014] The first mask layer on the peripheral region is etched using the third mask pattern as a mask to form a first device structure pattern.

[0015] In some embodiments of the present disclosure, forming a second mask pattern on the array area includes:

[0016] A portion of the second mask layer on the array region and the first dielectric layer on the sidewalls of the first mask pattern on the array region are removed to form a second mask pattern.

[0017] In some embodiments of the present disclosure, the second mask layer includes a second-first mask layer and a second-second mask layer, the second-first mask layer covers the top surface and sidewalls of the first dielectric layer, and the second-second mask layer is located above the second-first mask layer.

[0018] In some embodiments of the present disclosure, the second-second mask layer in the array area, the second-first mask layer located on top of the first mask pattern, and the first dielectric layer are removed;

[0019] The first dielectric layer located on the sidewall of the first mask pattern in the array region is removed to form a second mask pattern.

[0020] In some embodiments of the present disclosure, forming a third mask pattern on the peripheral region includes:

[0021] The first mask pattern and a portion of the first dielectric layer on the peripheral region are removed, and the first dielectric layer located on the sidewall of the first mask pattern is retained to form a third mask pattern.

[0022] In some embodiments of the present disclosure, a pattern density of the first device structure pattern is less than a pattern density of the second device structure pattern.

[0023] In some embodiments of the present disclosure, a pattern density of the first mask pattern in the array region is the same as a pattern density of the first mask pattern in the peripheral region.

[0024] In some embodiments of the present disclosure, the first mask pattern includes a long strip pattern.

[0025] In some embodiments of the present disclosure, forming a first dielectric layer on the first mask layer and the first mask pattern includes:

[0026] The first mask pattern covers a portion of the surface of the first mask layer;

[0027] The first dielectric layer conformally covers the top surface and sidewalls of the first mask pattern and the exposed surface of the first mask layer.

[0028] In some embodiments of the present disclosure, the first mask layer further includes a first third mask layer, and the first third mask layer is located between the first second mask layer and the substrate.

[0029] Before etching the substrate using the first device structure pattern and the second device structure pattern as masks, the first-second mask layer and the first-third mask layer are sequentially etched using the first device structure pattern and the second device structure pattern as masks.

[0030] In some embodiments of the present disclosure, before etching the substrate using the first device structure pattern and the second device structure pattern as masks, the process further includes removing the third mask layer.

[0031] In some embodiments of the present disclosure, after the substrate is masked using the first device structure pattern and the second device structure pattern as masks, the method further includes:

[0032] A first storage structure and a second storage structure are formed on the array area structure.

[0033] According to some embodiments, a second aspect of the present application further provides a semiconductor structure formed by the above-mentioned semiconductor structure manufacturing method.

[0034] The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, including: providing a substrate, the substrate including an array region and a peripheral region; forming a first mask layer on the substrate covering the array region and the peripheral region, the first mask layer having a first device structure pattern facing the array region and a second device structure pattern facing the peripheral region; and etching the substrate using the first device structure pattern and the second device structure pattern as masks to form a peripheral region structure and an array region structure, respectively. The semiconductor structure manufacturing method provided in the present invention simplifies the process flow, reduces the difficulty of manufacturing, and facilitates improved production efficiency by first forming a first mask layer having a first device structure pattern and a second device structure pattern on the substrate, and then etching the substrate using the first device structure pattern and the second device structure pattern as masks to simultaneously form a peripheral region structure and an array region structure on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 A flowchart of the steps of the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0037] Figure 2 A top view of a substrate is provided in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0038] Figure 3 A schematic structural diagram of a substrate provided in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0039] Figure 4 A schematic structural diagram of forming a first mask pattern and a first dielectric layer in a semiconductor structure manufacturing method provided in an embodiment of the present application;

[0040] Figure 5 A schematic structural diagram of forming a second-first mask layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0041] Figure 6 A schematic structural diagram of removing a portion of the second mask layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0042] Figure 7 A schematic structural diagram of removing a portion of the second-first mask layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0043] Figure 8 A schematic structural diagram of forming a second mask pattern in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0044] Figure 9 A schematic structural diagram of forming a second device structure pattern in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0045] Figure 10 A schematic structural diagram of forming a third mask layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0046] Figure 11 A schematic structural diagram of removing a portion of the second mask layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0047] Figure 12A schematic structural diagram of forming a first mask pattern in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0048] Figure 13 A schematic structural diagram of a first device structure pattern and a second device structure pattern in a semiconductor structure manufacturing method provided in an embodiment of the present application;

[0049] Figure 14 A schematic structural diagram of removing a portion of the first mask layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0050] Figure 15 This is a structural schematic diagram of forming a peripheral region structure and an array region structure in the semiconductor structure manufacturing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] Several optional implementations of the present application are introduced below in conjunction with the accompanying drawings. Those skilled in the art should understand that the following implementations are merely illustrative and not an exhaustive list. Based on these implementations, those skilled in the art may replace, splice or combine certain features or examples, which should still be regarded as the disclosed content of the present application.

[0052] Please refer to Figure 1 and Figure 2 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The semiconductor structure generally includes a substrate 10 and a device layer disposed on the substrate 10. The method is used to form a matching structure on the substrate 10 for matching with the device layer, including the following steps:

[0053] Step S101: providing a substrate, wherein the substrate includes an array region and a peripheral region.

[0054] like Figure 2 and Figure 3 As shown, the substrate 10 further includes a peripheral region 11 ( Figure 3 left of the position shown) and array area 12 ( Figure 3 The array region 12 is adjacent to the peripheral region 11. Figure 2 , the peripheral area 11 can be set on the periphery of the array area 12. Of course, in some other examples, the relative positions of the peripheral area 11 and the array area 12 can also be set according to actual needs, and this embodiment does not limit them here. The peripheral area 11 can be used to form a matching structure that cooperates with the peripheral circuit, and the array area 12 can be used to form a matching structure that cooperates with the memory cell. Among them, the array area 12 can also include different areas to cooperate with different types of memory cells. Of course, in some other examples, the matching structure of the peripheral area 11 and the array area 12 can also cooperate with other devices.

[0055] In this embodiment, the substrate 10 may be a semiconductor substrate 10, such as single crystal silicon, polycrystalline silicon, or amorphous silicon or silicon germanium (SiGe), or a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor, or a combination thereof. This embodiment is not limited thereto.

[0056] Step S102 : forming a first mask layer covering the array region and the peripheral region on the substrate, wherein the first mask layer has a first device structure pattern facing the peripheral region and a second device structure pattern facing the array region.

[0057] In this embodiment, a portion of the first mask layer 20 can be removed by etching, thereby forming a first device structure pattern 211 and a second device structure pattern 212 on the first mask layer 20. Since the first device structure pattern 211 faces the peripheral area 11, it is beneficial to subsequently form the peripheral area structure 111 using the first device structure pattern 211 as a mask. The second device structure pattern 212 faces the array area 12, which is beneficial to subsequently form the array area structure 121 using the second device structure pattern 212 as a mask.

[0058] like Figure 3 As shown, the first mask layer 20 includes a first mask layer 21 and a first second mask layer 22, wherein the first mask layer 21 is located above the first second mask layer 22. The material of the first mask layer 21 may include an inorganic material, for example, a dielectric anti-reflective coating (DARC) such as silicon oxide (SiO2), silicon (Si), and silicon-rich silicon oxynitride (SiON). For forming patterns with a pitch close to the resolution limit of photolithography technology, the first mask layer 21 can be provided to minimize light reflection to enhance resolution, thereby increasing the accuracy with which the pattern edge can be defined by photolithography, thereby improving the accuracy of the mask pattern formed on the first mask layer 21. The material of the first second mask layer 22 may include amorphous carbon, which is a material that is highly transparent to light (also known as "transparent carbon") and provides improvements in alignment by being transparent to the wavelength of light used for optical alignment. Furthermore, amorphous carbon has a very high etching selectivity compared to the hard mask material used in the related art, which can further improve the accuracy of forming the mask pattern on the first and second mask layers 22 .

[0059] Continue to refer to Figure 3The first mask layer 20 further includes a first third mask layer 23, which is located between the first second mask layer 22 and the substrate 10. The first third mask layer 23 may be made of silicon nitride, silicon oxide, silicon oxynitride, etc. When forming a photolithographic pattern on the first first mask layer 21 and the first second mask layer 22, the first third mask layer 23 can protect the substrate 10.

[0060] In this embodiment, after forming a first mask layer 20 covering the array region 12 and the peripheral region 11 on the substrate 10, wherein the first mask layer 20 has a first device structure pattern 211 facing the peripheral region 11 and a second device structure pattern 212 facing the array region 12, the following steps are further included:

[0061] Step S103 : etching the substrate using the first device structure pattern and the second device structure pattern as masks to form a peripheral region structure and an array region structure, respectively.

[0062] Optionally, the pattern density of the first device structure pattern 211 may be smaller than the pattern density of the second device structure pattern 212. Figure 13 As shown, in the first device structure pattern 211, there is a first distance L1 between adjacent rectangular blocks. It is worth noting that, Figure 13 The first device structure pattern 211 is merely an example. Depending on actual configuration requirements, the first distance L1 between any adjacent rectangular blocks can be the same (i.e., the multiple rectangular blocks are arranged at equal intervals) or different (i.e., the multiple rectangular blocks are arranged at unequal intervals). The second device structure pattern 212 includes multiple rectangular blocks arranged at intervals, and a second distance L2 is provided between adjacent rectangular blocks. Any first distance L1 is greater than the second distance L2. In other words, the pattern density of the first device structure pattern 211 is less than the pattern density of the second device structure pattern 212. By setting the above-mentioned first device structure pattern 211 and second device structure pattern 212, the embodiment of the present disclosure first forms the second device structure pattern with a larger pattern density, then forms the first device structure pattern with a smaller pattern density, and then simultaneously etches the substrate. This is beneficial to protecting the first device structure pattern with a smaller pattern density, improving the problem of the first device structure pattern with a smaller pattern density collapsing at the periphery, and is beneficial to the subsequent formation of the corresponding peripheral area structure 111 and array area structure 121 in the substrate 10, and making the pattern density of the peripheral area structure 111 smaller than the pattern density of the array area structure 121, which is beneficial to the subsequent formation of the corresponding device layer on the peripheral area structure 111 and the array area structure 121.

[0063] In this embodiment, after etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to form the peripheral region structure 111 and the array region structure 121 respectively, the method further includes: forming a first storage structure and a second storage structure on the array region structure 121 to accommodate different usage requirements within the array region 12. In this embodiment, the first storage structure and the second storage structure may include different types of storage units. For example, the first storage structure may include multiple dynamic random access storage units, each of which includes a transistor structure and a capacitor structure; and the second storage structure may include multiple magnetic random access storage units, each of which includes a transistor structure and a magnetoresistive tunnel junction inserted between two metal wires. By controlling the transistors in the transistor structure, the resistance value of the magnetoresistive tunnel junction is changed, thereby reading and writing data. Of course, in some other examples, the first storage structure and the second storage structure may also include storage units using other storage principles.

[0064] An embodiment of the present application provides a method for fabricating a semiconductor structure, comprising: providing a substrate 10, the substrate 10 including an array region 12 and a peripheral region 11; forming a first mask layer 20 covering the array region 12 and the peripheral region 11 on the substrate 10, the first mask layer 20 having a first device structure pattern 211 facing the array region 12, and a second device structure pattern 212 facing the peripheral region 11; and etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to respectively form a peripheral region structure 111 and an array region structure 121. The method for fabricating a semiconductor structure provided by an embodiment of the present application first forms the first mask layer 20 having the first device structure pattern 211 and the second device structure pattern 212 on the substrate 10, and then etches the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to simultaneously form the peripheral region structure 111 and the array region structure 121 on the substrate 10, thereby simplifying the process flow, reducing the difficulty of fabrication, and facilitating improved production efficiency.

[0065] In this embodiment, a first mask layer 20 covering the array area 12 and the peripheral area 11 is formed on the substrate 10. The first mask layer 20 has a first device structure pattern 211 facing the peripheral area 11 and a second device structure pattern 212 facing the array area 12. It also includes: forming a first mask pattern 30 on the first mask layer 20.

[0066] like Figure 4 As shown, the first mask pattern 30 is projected on the substrate 10 and located in the array area 12 and the peripheral area 11 , so that corresponding matching structures are subsequently formed in the array area 12 and the peripheral area 11 of the substrate 10 through the first mask pattern 30 .

[0067] Optionally, the pattern density of the first mask pattern 30 in the array region 12 is the same as the pattern density of the first mask pattern 30 in the peripheral region 11. The same pattern density of the first mask pattern 30 in the array region 12 and the peripheral region 11 simplifies the process of forming the first mask pattern 30 and improves production efficiency.

[0068] Furthermore, the first mask pattern 30 may include a strip-shaped pattern. Exemplarily, the first mask pattern 30 includes a plurality of strip-shaped patterns spaced apart. In this embodiment, the strip-shaped pattern may be, for example, a rectangle. It is worth noting that, in some embodiments of the present disclosure, the peripheral region structure 111 and the array region structure 121 formed using the first mask pattern 30 having a strip-shaped pattern are also strip-shaped. The peripheral region structure 111 and the array region structure 121 can be used to form a portion (e.g., a fin) of a fin field-effect transistor (FinFET), thereby improving the performance of the semiconductor structure.

[0069] In a specific implementation, the material of the first mask pattern 30 may include a hard mask material. The formation process of the first mask pattern 30 may include: forming a hard mask material layer on the first mask layer 20, and then etching the hard mask material layer to remove a portion of the hard mask material, thereby forming the corresponding first mask pattern 30. The hard mask material layer may be, for example, SOH (Spin on Hardmasks). SOH is an auxiliary material for forming semiconductor fine patterns. It is used for the film under the photoresist to help transcribe the circuit to the target film to achieve the accuracy of the fine pattern and play the role of an appropriate protective film in the subsequent etching process. It is worth noting that the material of SOH is conducive to achieving the pattern accuracy of fine line width, thereby further improving the pattern accuracy of the first mask pattern 30.

[0070] In this embodiment, in the step of forming a first mask layer 20 covering the array area 12 and the peripheral area 11 on the substrate 10, the first mask layer 20 having a first device structure pattern 211 facing the peripheral area 11, and a second device structure pattern 212 facing the array area 12, after forming the first mask pattern 30 on the first mask layer 20, the further step includes: forming a first dielectric layer 40 on the first mask layer 20 and the first mask pattern 30.

[0071] like Figure 4 As shown, the first mask pattern 30 may cover a portion of the surface of the first mask layer 20. In an embodiment where the first mask pattern 30 includes a plurality of spaced rectangular blocks, the first mask layer 20 is exposed between adjacent rectangular blocks, that is, the first mask pattern 30 may cover a portion of the surface of the first mask layer 20.

[0072] The first dielectric layer 40 is formed on the first mask layer 20 and the first mask pattern 30, and further includes: the first dielectric layer 40 can conformally cover the top surface and sidewalls of the first mask pattern 30 and the exposed surface of the first mask layer 20. Figure 4 In this embodiment, the first dielectric layer 40 covers the side walls of the rectangular blocks and the end surfaces of the rectangular blocks facing away from the substrate 10 (i.e., the top surfaces of the first mask patterns 30). The first dielectric layer 40 also covers the first mask layer 20 between adjacent rectangular blocks (i.e., the exposed surfaces of the first mask layer 20).

[0073] In a specific implementation, the material of the first dielectric layer 40 may include silicon oxide, silicon nitride, silicon oxynitride, etc., so that the first dielectric layer 40 can play a role in protecting the first mask pattern 30 .

[0074] In this embodiment, in the step of forming a first mask layer 20 covering the array area 12 and the peripheral area 11 on the substrate 10, the first mask layer 20 having a first device structure pattern 211 facing the peripheral area 11, and a second device structure pattern 212 facing the array area 12, after forming the first dielectric layer 40 on the first mask layer 20 and the first mask pattern 30, the further step includes: forming a second mask layer on the first dielectric layer 40 in the peripheral area 11.

[0075] In this embodiment, the step of forming the second mask layer on the first dielectric layer 40 in the array area 12 may include: forming a second-first mask layer 51 on the first dielectric layer 40, and forming a second-second mask layer 52 on the second-first mask layer 51. Figure 5 As shown, the projection of the second-first mask layer 51 on the substrate 10 is located in the array region 12 and the peripheral region 11 , and the second-second mask layer 52 is located above the second-first mask layer 51 .

[0076] In this embodiment, the sidewalls of the first dielectric layer 40 are located on the surface of the first dielectric layer 40 covering the sidewalls of the first mask pattern 30, and the top surface of the first dielectric layer 40 is located on the surface of the first dielectric layer 40 covering the top surface of the first mask layer 20. Figure 5 As shown, the second-first mask layer 51 can cover the top surface and sidewalls of the first dielectric layer 40. Furthermore, the sidewalls of the first dielectric layer 40 and the first dielectric layer 40 covering the exposed first mask layer 20 can be arranged to form a groove, and the second-first mask layer 51 also fills the groove.

[0077] In a specific real-time method, the material of the second-first mask layer 51 may include a hard mask material, for example, SOH. It is worth noting that the material of SOH has the characteristics of filling gaps, increasing flatness, and enhancing corrosion resistance, which is beneficial for the second-first mask layer 51 to fill the grooves of the first dielectric layer 40 and is beneficial to maintaining the flatness of the second-first mask layer 51. Furthermore, the second-first mask layer 51 can also protect the first dielectric layer 40.

[0078] In this embodiment, in the step of forming a first mask layer 20 covering the array area 12 and the peripheral area 11 on the substrate 10, the first mask layer 20 having a first device structure pattern 211 facing the peripheral area 11, and a second device structure pattern 212 facing the array area 12, after forming the second mask layer on the first dielectric layer 40 in the peripheral area 11, the further steps include: forming a second mask pattern 42 on the array area 12; and forming the second device structure pattern 212 on the first mask layer 20 using the second mask pattern 42 as a mask.

[0079] In this embodiment, refer to Figure 6 The step of forming the second mask pattern 42 on the peripheral area 11 includes: removing the second-second mask layer 52 in the array area 12, the second-first mask layer 51 located on the top of the first mask pattern 30, and the first dielectric layer 40; removing the first dielectric layer 40 located on the sidewall of the first mask pattern 30 in the array area 12 to form the second mask pattern 42.

[0080] It is worth noting that, referring to Figure 7 The second-second mask layer 52 and a portion of the second-first mask layer 51 may be removed first to expose the first dielectric layer 40 covering the top surface of the first mask pattern 30 .

[0081] In a specific implementation, the material of the second-second mask layer 52 may include photoresist. Taking the material of the second-second mask layer 52 as positive photoresist as an example, the process of removing the second-second mask layer 52 is briefly described: positive photoresist is coated on the second-first mask layer 51 to form the second-second mask layer 52, and a mask is formed on the second-second mask layer 52 so that the mask can shield the positive photoresist projected in the peripheral area 11, and the remaining exposed positive photoresist is exposed and developed to remove the initial second-second mask layer 52 projected in the array area 12.

[0082] After removing the second-second mask layer 52 in the array area 12, the first dielectric layer 40 covering the top surface of the first mask pattern 30 is removed, and a portion of the second-first mask layer 51 is simultaneously removed, so that the end surface of the second-first mask layer 51 facing away from the substrate 10 is flush with the top surface of the first mask pattern 30. Then, the first dielectric layer 40 covering the sidewalls of the first mask pattern 30 is removed, leaving the first mask pattern 30, a portion of the first dielectric layer 40, and a portion of the second-first mask layer 51 in the array area 12, thereby forming a second mask pattern 42.

[0083] Reference Figure 8 The second mask pattern 42 may include a plurality of rectangular blocks spaced apart from each other. Of course, in some other examples, the shape of the second mask pattern 42 may be adjusted by adjusting the shape of the first mask pattern 30 and the thickness of the first dielectric layer 40. This embodiment does not specifically limit the shape of the second mask pattern 42.

[0084] In this embodiment, after forming the second mask pattern 42 in the array region 12 , the second device structure pattern 212 is further formed in the first mask layer 20 using the second mask pattern 42 as a mask.

[0085] Refer to the attached Figure 8 and Figure 9 To form the second device structure pattern 212, it is necessary to use the second mask pattern 42 as a mask to remove part of the first mask layer 20. In this embodiment, the first mask layer 21 on the array area 12 is etched using the second mask pattern 42 as a mask to form the second device structure pattern 212. Figure 12 and Figure 13 As shown, the second device structure pattern 212 has the same shape as the second mask pattern 42. The second device structure pattern 212 may include a plurality of rectangular blocks spaced apart from each other. Furthermore, in some other examples, the shape of the second device structure pattern 212 may be adjusted by adjusting the shape of the second mask pattern 42. This embodiment does not specifically limit the shape of the second device structure pattern 212.

[0086] In this embodiment, a first mask layer 20 covering the array area 12 and the peripheral area 11 is formed on the substrate 10, and the first mask layer 20 has a first device structure pattern 211 facing the peripheral area 11, and a second device structure pattern 212 facing the array area 12. In the step, a second mask pattern 42 is formed on the array area 12; after the second device structure pattern 212 is formed on the first mask layer 20 using the second mask pattern 42 as a mask, the method further includes: forming a third mask layer 60 on the second device structure pattern 212.

[0087] like Figure 9As shown, in an embodiment in which the second device structure pattern 212 is shaped as a plurality of rectangular blocks spaced apart in the first mask layer 20, the second device structure pattern 212 is formed on the first-first mask layer 21 and covers a portion of the first-second mask layer 22, such that a portion of the first-second mask layer 22 is exposed between adjacent rectangular blocks. The third mask layer 60 conformally covers the first-first mask layer 21 and the exposed first-second mask layer 22.

[0088] In this embodiment, the step of forming the third mask layer 60 on the second device structure pattern 212 may include: forming an initial third mask layer 60 on the first dielectric layer 40 , and removing the initial third mask layer 60 in the peripheral region 11 to form the third mask layer 60 .

[0089] In a specific implementation, the material of the third mask layer 60 may include photoresist. Taking the material of the third mask layer 60 as positive photoresist as an example, the formation process of the third mask layer 60 is briefly described: positive photoresist is coated on the second device structure pattern 212 and the second mask layer to form an initial third mask layer 60, and a mask is formed on the initial third mask layer 60 so that the mask can shield the positive photoresist projected in the array area 12, and the remaining exposed positive photoresist is exposed and developed to remove the initial third mask layer 60 projected in the peripheral area 11, that is, remove the initial third mask layer 60 covering the second mask layer, and then form the third mask layer 60.

[0090] It is worth noting that in an embodiment where the third mask layer 60 and the second-second mask layer 52 are both made of positive photoresist, a photomask is formed on the initial third mask layer 60 so that the photomask can shield the photoresist projected on the array region 12, and the remaining exposed photoresist is exposed and developed. When the initial third mask layer 60 projected on the peripheral region 11 is removed, the second-second mask layer 52 is exposed. At this point, the second-second mask layer 52 covering the peripheral region 11 can be further removed using exposure and development methods to expose the second-first mask layer 51, facilitating the subsequent removal of the second-first mask layer 51, thereby forming the third mask pattern 41 on the peripheral region 11. In some other examples, the third mask layer 60 and the second-second mask layer 52 can also be made of negative photoresist, and the process is not further described here.

[0091] In this embodiment, a first mask layer 20 covering the array area 12 and the peripheral area 11 is formed on the substrate 10, and the first mask layer 20 has a first device structure pattern 211 facing the peripheral area 11, and a second device structure pattern 212 facing the array area 12. After forming the third mask layer 60 on the second device structure pattern 212, the method further includes: forming a third mask pattern 41 on the peripheral area 11; and forming the first device structure pattern 211 on the first mask layer 20 using the third mask pattern 41 as a mask.

[0092] In this embodiment, the step of forming the third mask pattern 41 in the peripheral region 11 includes removing the first mask pattern 30 and a portion of the first dielectric layer 40 on the peripheral region 11 , and retaining the first dielectric layer 40 on the sidewalls of the first mask pattern 30 to form a second mask pattern 42 .

[0093] It is worth noting that before removing the first mask pattern 30 and a portion of the first dielectric layer 40 on the peripheral region 11 , the second mask layer on the peripheral region 11 needs to be removed first to expose the first mask pattern 30 and the first dielectric layer 40 .

[0094] like Figure 10 、 Figure 11 ,as well as Figure 12 As shown, in this embodiment, the first dielectric layer 40 covering the top surface of the first mask pattern 30 can be removed to expose the first mask pattern 30. Then, the first mask pattern 30 and the first dielectric layer 40 covering the first mask layer 20 are removed, and the first dielectric layer 40 covering the sidewalls of the first mask pattern 30 is retained to form a third mask pattern 41.

[0095] Continue to refer to Figure 12 The third mask pattern 41 may include a plurality of rectangular blocks spaced apart from each other. Of course, in some other examples, the shape of the third mask pattern 41 may be adjusted by adjusting the shape of the first mask pattern 30 and the thickness of the first dielectric layer 40. This embodiment does not specifically limit the shape of the third mask pattern 41.

[0096] In this embodiment, after forming the third mask pattern 41 on the peripheral region 11 , the further step includes forming a first device structure pattern 211 on the first mask layer 20 using the third mask pattern 41 as a mask.

[0097] Refer to the attached Figure 13 、 Figure 14 and Figure 15, forming the first device structure pattern 211, it is necessary to use the third mask pattern 41 as a mask to remove a portion of the first mask layer 20. In this embodiment, the first mask layer 21 on the peripheral region 11 is etched using the third mask pattern 41 as a mask to form the first device structure pattern 211. As shown in the figure, the first device structure pattern 211 has the same shape as the third mask pattern 41, and the first device structure pattern 211 may include a plurality of rectangular blocks arranged at intervals. Furthermore, in some other examples, the shape of the first device structure pattern 211 can be adjusted by setting the shape of the third mask pattern 41. This embodiment does not specifically limit the shape of the first device structure pattern 211.

[0098] In this embodiment, before etching the substrate 10 using the second device structure pattern 212 as a mask, the third mask layer 60 is removed to expose the second device structure pattern 212 and a portion of the substrate 10 located in the array area 12, which is beneficial for subsequent etching of the substrate 10 using the second device structure pattern 212 as a mask.

[0099] Furthermore, if Figure 14 As shown, before etching the substrate 10 using the first device structure pattern 211 as a mask, the first mask pattern 30, the first dielectric layer 40 and the second mask layer 51 of the peripheral area 11 are removed to expose the first device structure pattern 211 and a portion of the substrate 10 located in the peripheral area 11, which is beneficial for the subsequent etching of the substrate 10 using the first device structure pattern 211 as a mask.

[0100] In this embodiment, before etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks, the process also includes: etching the first second mask layer 22 and the first third mask layer 23 in sequence using the first device structure pattern 211 and the second device structure pattern 212 as masks, thereby avoiding subsequent etching effects on the substrate 10.

[0101] The present application also provides a semiconductor structure, a substrate 10, the substrate 10 includes an array area 12 and a peripheral area 11, the peripheral area 11 has a peripheral area structure 111, the array area 12 has an array area structure 121, and a method for manufacturing the peripheral area structure 111 and the array area structure 121 includes: forming a first mask layer 20 covering the array area 12 and the peripheral area 11 on the substrate 10; forming a first mask pattern 30 on the first mask layer 20; forming a first dielectric layer 40 on the first mask layer 20 and the first mask pattern 30; forming a first dielectric layer 40 on the first dielectric layer 40 in the array area 12 ... The method comprises forming a second mask layer; forming a second mask pattern 42 on the peripheral region 11; forming a first device structure pattern 211 on the first mask layer 20 using the second mask pattern 42 as a mask; forming a third mask layer 60 on the first dielectric layer 40 of the peripheral region 11; forming a third mask pattern 41 on the array region 12; forming a second device structure pattern 212 on the first mask layer 20 using the third mask pattern 41 as a mask; etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to form the peripheral region structure 111 and the array region structure 121, respectively. The method for manufacturing a semiconductor structure provided by the embodiment of the present application first forms a first mask layer 20 having the first device structure pattern 211 and the second device structure pattern 212 on the substrate 10, and then etching the substrate 10 using the first device structure pattern 211 and the second device structure pattern 212 as masks to simultaneously form the peripheral region structure 111 and the array region structure 121 on the substrate 10, thereby simplifying the process flow, reducing the manufacturing difficulty, and facilitating improved production efficiency.

[0102] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the division of the above-mentioned functional modules is only used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate, wherein the first mask layer has a first device structure pattern located above the peripheral region and a second device structure pattern located above the array region; Etching the substrate using the first device structure pattern and the second device structure pattern as masks to form a peripheral region structure and an array region structure, respectively; Wherein, a first mask layer covering the array area and the peripheral area is formed on the substrate, the first mask layer having a first device structure pattern facing the peripheral area and a second device structure pattern facing the array area, including: forming a first mask pattern on the first mask layer; forming a first dielectric layer on the first mask layer and the first mask pattern, forming a second mask layer on the first dielectric layer; forming a second mask pattern on the array region; and forming a second device structure pattern on the first mask layer using the second mask pattern as a mask; forming a third mask layer on the second device structure pattern; A third mask pattern is formed on the peripheral region; and a first device structure pattern is formed on the first mask layer using the third mask pattern as a mask.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first mask layer includes a first-first mask layer and a first-second mask layer, wherein the first-first mask layer is located above the first-second mask layer. Using the second mask pattern as a mask, etching the first mask layer on the array area to form a second device structure pattern; The first mask layer on the peripheral region is etched using the third mask pattern as a mask to form a first device structure pattern.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming a second mask pattern on the array area includes: A portion of the second mask layer on the array region and the first dielectric layer on the sidewalls of the first mask pattern on the array region are removed to form a second mask pattern.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The second mask layer includes a second-first mask layer and a second-second mask layer, the second-first mask layer covers the top surface and sidewalls of the first dielectric layer, and the second-second mask layer is located above the second-first mask layer.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: removing the second-second mask layer in the array area, the second-first mask layer located on top of the first mask pattern, and the first dielectric layer; The first dielectric layer located on the sidewall of the first mask pattern in the array region is removed to form a second mask pattern.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming a third mask pattern on the peripheral region includes: The first mask pattern and a portion of the first dielectric layer on the peripheral region are removed, and the first dielectric layer located on the sidewall of the first mask pattern is retained to form a third mask pattern.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: A pattern density of the first device structure pattern is smaller than a pattern density of the second device structure pattern.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: A pattern density of the first mask patterns in the array region is the same as a pattern density of the first mask patterns in the peripheral region.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: The first mask pattern includes a long strip pattern.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming a first dielectric layer on the first mask layer and the first mask pattern includes: The first mask pattern covers a portion of the surface of the first mask layer; The first dielectric layer conformally covers the top surface and sidewalls of the first mask pattern and the exposed surface of the first mask layer.

11. The method for manufacturing a semiconductor structure according to claim 2, wherein: The first mask layer further includes a first third mask layer, and the first third mask layer is located between the first second mask layer and the substrate. Before etching the substrate using the first device structure pattern and the second device structure pattern as masks, the first-second mask layer and the first-third mask layer are sequentially etched using the first device structure pattern and the second device structure pattern as masks.

12. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before etching the substrate using the first device structure pattern and the second device structure pattern as masks, the method further includes removing the third mask layer.

13. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the substrate is masked using the first device structure pattern and the second device structure pattern as masks, the method further includes: A first storage structure and a second storage structure are formed on the array area structure.

14. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for manufacturing the semiconductor structure according to any one of claims 1 to 13.

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