A ring gate transistor and a method of manufacturing the same

Abstract

The application discloses a ring gate transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, which is used to improve the driving performance of the ring gate transistor by applying stress to the channel region through a stress source layer of a stress source structure. The ring gate transistor comprises a semiconductor substrate, an active structure, a gate stack structure and a stress source structure. The semiconductor substrate has a buried oxygen layer. The active structure is formed on the buried oxygen layer. The active structure comprises a source region, a drain region and a channel region between the source region and the drain region. The material of the part of the active structure in the channel region is silicon, germanium silicon or germanium. The gate stack structure surrounds the outer periphery of the channel region. The stress source structure is arranged at least below the channel region and between the gate stack structure and the buried oxygen layer. The material of the stress source structure is germanium silicon, and the germanium content in the material of the part of the active structure in the channel region is different from that in the stress source structure when the material of the part of the active structure in the channel region is germanium silicon.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a ring gate transistor and a manufacturing method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the critical dimension of semiconductor devices is getting smaller and smaller. When the process node of semiconductor devices reaches 28nm or below, for a ring gate transistor, the stress on the channel region can be increased by using a source / drain epitaxy method, so as to improve the mobility of carriers, and further improve the performance of semiconductor devices.

[0003] However, the source region and the drain region formed by using the existing source / drain epitaxy process usually have a large number of defects, which gradually weakens the effect of the source region and the drain region on the channel region, and is not conducive to improving the driving performance of the ring gate transistor. SUMMARY

[0004] The present application aims to provide a ring gate transistor and a manufacturing method thereof, so as to improve the driving performance of the ring gate transistor by manufacturing a stress source layer of a stress source structure to apply stress on the channel region.

[0005] In order to achieve the above-mentioned purpose, the present application provides a ring gate transistor, which comprises a semiconductor substrate, an active structure, a gate stack structure and a stress source structure. The semiconductor substrate has a buried oxide layer. The active structure is formed on the buried oxide layer. The active structure comprises a source region, a drain region and a channel region between the source region and the drain region. The material of the part of the active structure located in the channel region is silicon, silicon germanium or germanium. The gate stack structure surrounds the outer periphery of the channel region. The stress source structure is arranged at least below the channel region and between the gate stack structure and the buried oxide layer. The material of the stress source structure is silicon germanium, and in the case that the material of the part of the active structure located in the channel region is silicon germanium, the germanium content in the material of the stress source structure and the part of the active structure located in the channel region is different.

[0006] Compared with the prior art, the material of the active structure in the part of the channel region in the ring gate transistor provided by the application is silicon, silicon germanium or germanium. In addition, the ring gate transistor further comprises a stress source structure between the gate stack structure and the buried oxide layer, and the material of the stress source structure is silicon germanium. It can be understood that, in the case that the material of the active structure in the part of the channel region is silicon or germanium, the material of the stress source structure is different from that of the active structure in the part of the channel region. In addition, in the case that the material of the active structure in the part of the channel region is silicon germanium, the germanium content of the material of the stress source structure is different from that of the active structure in the part of the channel region. In this case, the material of the stress source structure is also different from that of the active structure in the part of the channel region. Secondly, the stress source structure is arranged at least below the channel region. In this case, in the actual manufacturing process, the stress source layer for manufacturing the stress source structure is formed on the buried oxide layer, and then the channel layer for manufacturing the channel region is formed above the stress source layer. Because the material of the stress source structure is different from that of the active structure in the part of the channel region, the material of the corresponding stress source layer is also different from that of the channel layer. In addition, because the lattice constants of the two different materials are different, when the film layers of the two different materials form a heterojunction, the lattice mismatch problem may exist, and the stress source layer and the channel layer near the interface generate stress, so that the stress source layer for manufacturing the stress source structure is stretched or compressed by external force to exert stress on the channel layer, thereby exerting stress on the channel region manufactured by the channel layer, and solving the problem that the effect of the source region and the drain region formed by using the source and drain epitaxy process to exert stress on the channel region gradually weakens due to a large number of defects of the source region and the drain region, so as to ensure that the channel region has a high carrier mobility and improve the driving performance of the ring gate transistor.

[0007] The application further provides a manufacturing method of a ring gate transistor, which comprises the following steps: firstly, forming a semiconductor substrate. The semiconductor substrate has a buried oxide layer. Next, forming a stress source structure and an active structure on the buried oxide layer. The active structure comprises a source region, a drain region and a channel region between the source region and the drain region. The material of the part of the active structure in the channel region is silicon, silicon germanium or germanium. The stress source structure is arranged at least below the channel region. The material of the stress source structure is silicon germanium, and in the case that the material of the part of the active structure in the channel region is silicon germanium, the germanium content of the material of the stress source structure is different from that of the part of the active structure in the channel region. Next, forming a gate stack structure surrounding the outer periphery of the channel region. The stress source structure is between the gate stack structure and the buried oxide layer.

[0008] Compared with the prior art, the manufacturing method of the ring gate transistor provided by the application has the beneficial effects of the ring gate transistor, which will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0010] Figure 1 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 1 ;

[0011] Figure 2 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 2 ;

[0012] Figure 3 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 3 ;

[0013] Figure 4 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 4 ;

[0014] Figure 5 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 5 ;

[0015] Figure 6 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 6 ;

[0016] Figure 7 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 7 ;

[0017] Figure 8 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 8 ;

[0018] Figure 9 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 9 ;

[0019] Figure 10 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 10 ;

[0020] Figure 11 Structure schematic of the ring gate transistor provided by the embodiment of the present application in the manufacturing process Figure 10 ;

[0021] Figure 12Structure diagram of a ring gate transistor in a manufacturing process Figure 10 Two;

[0022] Figure 13 Flow chart of a manufacturing method of a ring gate transistor.

[0023] The figure shows: 11 is a silicon-on-insulator substrate, 12 is a silicon substrate, 13 is a buried oxygen layer, 14 is a silicon layer, 15 is a diffusion layer, 16 is a stress source layer, 17 is a silicon oxide layer, 18 is a semiconductor substrate, 19 is a stack, 20 is a sacrificial layer, 21 is a channel layer, 22 is a fin, 23 is a first region, 24 is a second region, 25 is a third region, 26 is a shallow trench isolation structure, 27 is a sacrificial gate, 28 is a sidewall, 29 is a source region, 30 is a drain region, 31 is a stress source structure, 32 is a dielectric layer, 33 is a channel region, 34 is a gate stack structure. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0025] Various structure diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale in which certain details are exaggerated for clarity and others are omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary and can deviate in actuality due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0026] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present disclosure, technical solutions and beneficial effects more clear, the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present disclosure and not to limit the present disclosure.

[0027] In addition, the terms "first", "second", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0028] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] With the development of semiconductor technology, the critical dimension of semiconductor devices is getting smaller and smaller. When the process node of semiconductor devices reaches 28nm or below, for ring gate transistors, the stress on the channel region can usually be increased by using source / drain epitaxy, so as to improve the mobility of carriers and further improve the performance of semiconductor devices. For example, for P-type ring gate transistors, the material of source / drain epitaxy is usually a semiconductor material with compressive stress such as germanium silicon or germanium. And for N-type ring gate transistors, the material of source / drain epitaxy is usually a semiconductor material with tensile stress such as Si:C.

[0030] In actual manufacturing process, taking the manufacture of a ring gate transistor with a layer of nanotube as an example, first, a fin structure and a shallow trench isolation structure are formed on a semiconductor substrate. The fin structure is exposed outside the shallow trench isolation structure and includes a sacrificial layer and a channel layer on the sacrificial layer. And along the length direction of the fin structure, the fin structure has a source forming area, a drain forming area, and a channel forming area between the source forming area and the drain forming area. Next, after forming a sacrificial gate and a sidewall across the fin structure with the channel forming area, the part of the fin structure exposed outside the sacrificial gate and the sidewall is removed first; then, using epitaxy process, source / drain regions are formed on both sides of the fin structure corresponding to the channel forming area part, to provide corresponding stress to the channel and improve the driving performance of the device.

[0031] However, after the sacrifice gate and the side wall are used as a mask to remove part of the fin-shaped structure corresponding to the source forming region and the drain forming region, not only the part of the fin-shaped structure corresponding to the channel forming region is exposed, but also the part of the semiconductor substrate not covered by the shallow trench isolation structure and the sacrifice gate is exposed. Therefore, in the process of forming the source region and the drain region by using the existing epitaxial process, the part of the fin-shaped structure corresponding to the channel forming region and the part of the semiconductor substrate not covered by the shallow trench isolation structure and the sacrifice gate can all serve as seed layers of the epitaxial source / drain region, so that the source / drain region can grow not only in the direction parallel to the surface of the semiconductor substrate, but also in the thickness direction of the semiconductor substrate, and thus a large number of defects exist in the obtained source / drain region, which gradually weakens the stress exerted on the channel region by the source / drain region, and affects the driving performance of the gate-all-around transistor.

[0032] To solve the above technical problem, the embodiments of the present application provide a gate-all-around transistor and a manufacturing method thereof. In the gate-all-around transistor provided by the embodiments of the present application, the stress source structure is arranged at least below the channel region; and the material of the part of the active structure located in the channel region is different from the material of the stress source structure. Therefore, in actual application, the stress source layer of the stress source structure can be used to exert stress on the channel region manufactured by using the channel layer, so as to ensure that the channel region has a high carrier mobility and improve the driving performance of the gate-all-around transistor.

[0033] The embodiments of the present application provide a gate-all-around transistor. The conductive type of the gate-all-around transistor can be N-type or P-type. As shown in Figure 12 The gate-all-around transistor provided by the embodiments of the present application comprises a semiconductor substrate, an active structure, a gate stack structure 34 and a stress source structure 31.

[0034] As shown in Figure 12 The semiconductor substrate has a buried oxygen layer 13. The active structure is formed on the buried oxygen layer 13. The active structure comprises a source region 29, a drain region 30 and a channel region 33 located between the source region 29 and the drain region 30. The material of the part of the active structure located in the channel region 33 is silicon, silicon germanium or germanium. The gate stack structure 34 surrounds the outer periphery of the channel region 33. The stress source structure 31 is arranged at least below the channel region 33 and between the gate stack structure 34 and the buried oxygen layer 13. The material of the stress source structure 31 is silicon germanium, and in the case where the material of the part of the active structure located in the channel region 33 is silicon germanium, the germanium content in the material of the stress source structure 31 and the part of the active structure located in the channel region 33 is different.

[0035] Specifically, the specific structure and material of the semiconductor substrate can be set according to the actual application scenario, which is not limited here. For example, the semiconductor substrate in the embodiments of the present application can be a germanium silicon on insulator substrate without any structure formed thereon.

[0036] For the aforementioned active structure, the portions of the active structure corresponding to the source and drain regions can be obtained by directly doping the portions of the fins corresponding to the first and second regions using processes such as ion implantation. In this case, the material of a portion of the active structure corresponding to the source and drain regions is the same as the material of the portion corresponding to the channel region; the material of another portion of the active structure corresponding to the source and drain regions is the same as the material of the sacrificial layer (or the sacrificial layer and the stress source structure).

[0037] Alternatively, the portions of the active structure corresponding to the source and drain regions can also be obtained by processing the portions of the fins corresponding to the first and second regions using processes such as etching and epitaxy. In this case, the materials of the portions of the active structure corresponding to the source and drain regions can be set according to the conductivity type of the gate-around transistor and the actual application scenario, and are not specifically limited here. For example, when the conductivity type of the gate-around transistor is N-type, the material of the portions of the active structure corresponding to the source and drain regions can be silicon, etc. As another example, when the conductivity type of the gate-around transistor is P-type, the material of the portions of the active structure corresponding to the source and drain regions can be germanium-silicon or germanium, etc.

[0038] In some cases, such as Figure 12 As shown, when the active structure corresponding to the source region 29 and the drain region 30 is formed using the above-described epitaxial method, the portion of the active structure located within the source region 29 and the drain region 30 can be an epitaxial structure formed on the buried oxide layer 13. Based on this, in the actual manufacturing process, as... Figure 8 As shown, after the etching process removes portions of the fin corresponding to the first and second regions, the buried oxide layer 13 is exposed. In this case, as... Figure 9 As shown, source region 29 and drain region 30 can only use the portions of the remaining fins exposed as seed layers and are epitaxially formed in a two-dimensional growth manner along a surface direction parallel to the semiconductor substrate. In other words, source region 29 and drain region 30 can grow in a single direction, restricting the growth direction of the semiconductor material forming source region 29 and drain region 30. This can further reduce the defects formed in source region 29 and drain region 30, thereby improving the effect of source region 29 and drain region 30 in applying stress to the channel region, and further improving the driving performance of the gate-around transistor.

[0039] As for the channel region included in the active structure, the channel region can include only one nanostructure, or can include multiple nanostructures. Moreover, each nanostructure has a gap with the semiconductor substrate. When the channel region includes multiple nanostructures, each adjacent two nanostructures also have a gap therebetween. Different nanostructures can be distributed along the thickness direction of the semiconductor substrate, or can be distributed along the width direction of the gate stack structure. The specific number of nanostructures included in the channel region, and the arrangement manner of different nanostructures when the channel region includes multiple nanostructures can be determined according to actual application scenarios, which are not limited here.

[0040] In addition, the material of the part of the active structure located in the channel region can be any one of silicon, silicon germanium or germanium. When the material of the part of the active structure located in the channel region is silicon germanium, the specific content of germanium in the channel region can be determined according to the conduction type of the ring gate transistor and actual needs, as long as it can be applied to the ring gate transistor provided by the embodiment of the present application. For example, when the conduction type of the ring gate transistor is N type, the material of the part of the active structure located in the channel region can be Si 1-x Ge x , 0 < x < 0.5. For another example, when the conduction type of the ring gate transistor is P type, the material of the part of the active structure located in the channel region can be Si 1-x Ge x , 0.5 < x < 1. Specifically, when the channel region includes multiple nanostructures, the materials of different nanostructures can be the same or different. When the materials of different nanostructures included in the channel region are different, the conduction characteristics of the corresponding nanostructure can be regulated by adjusting the content of germanium in each nanostructure, thereby improving the applicability of the ring gate transistor provided by the embodiment of the present application in different application scenarios.

[0041] For the above-mentioned gate stack structure, the gate stack structure can include a gate dielectric layer surrounding the outer periphery of each nanostructure, and a gate electrode located on the gate dielectric layer. The material of the above-mentioned gate dielectric layer can be an insulating material with low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with high dielectric constant such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate electrode can be a conductive material such as doped polysilicon, TiN, TaN or TiSiN.

[0042] For the stressor structure, the stressor structure can be located only below the channel region. Alternatively, the stressor structure can also be located below the source region and the drain region. The forming range of the stressor structure can be determined according to the structure of the source region and the drain region, and the actual application scenario, which is not specifically limited herein. In addition, the specific value of the content of germanium in the material of the stressor structure can be set according to the conductivity type of the ring gate transistor, the material of the part of the active structure located in the channel region, and the actual demand, as long as the material of the stressor structure is different from the material of the part of the active structure located in the channel region.

[0043] For example, the content of germanium in the material of the stressor structure can be 30%, 40%, 50%, 60%, or 70%, etc. In this case, when the content of germanium in the material of the stressor structure is within the above range, the difference between the content of germanium in the material of the stressor structure and the part of the active structure located in the channel region can be prevented from being too small, so that the stress effect of the stressor structure on the channel region is not obvious, the channel region has a high carrier mobility, and the driving performance of the ring gate transistor is further improved.

[0044] Specifically, the content of germanium in the material of each region of the stressor structure can be uniformly distributed, or the content of germanium in different regions of the stressor structure can be set according to actual demand.

[0045] For example, the content of germanium in the material of the stressor structure gradually increases from the bottom to the top. In this case, when the total amount of germanium in the material of the stressor structure is constant, compared with the uniform distribution of the content of germanium in the material of the stressor structure, the gradually increasing content of germanium in the material of the stressor structure from the bottom to the top can make the content of germanium in the material of the top of the stressor structure higher, which is beneficial to increasing the difference between the content of germanium in the stressor structure and the channel region, and further improving the effect of the stress source layer for manufacturing the stressor structure on the channel layer for manufacturing the channel region, and further improving the driving performance of the ring gate transistor.

[0046] For example, when the conductivity type of the ring gate transistor is N-type, the material of the part of the active structure located in the channel region is silicon, or the material of the part of the active structure located in the channel region is germanium silicon, and the content of germanium in the material of the part of the active structure located in the channel region is less than the content of germanium in the material of the stressor structure. In this case, the content of germanium in the material of the stressor structure is higher. At this time, the stress source layer for manufacturing the stressor structure can be used to apply tensile stress to the channel layer for manufacturing the channel region, and the driving performance of the N-type ring gate transistor is improved.

[0047] For example, in the case that the conductive type of the ring gate transistor is N type, the material of the part of the active structure located in the channel region is Si, and the material of the stress source structure is Si 0.7 Ge 0.3 For example, in the case that the conductive type of the ring gate transistor is N type, the material of the part of the active structure located in the channel region is Si 0.9 Ge 0.1 , and the material of the stress source structure is Si 0.6 Ge 0.4 .

[0048] For example, in the case that the conductive type of the ring gate transistor is P type, the material of the part of the active structure located in the channel region is Ge, or the material of the part of the active structure located in the channel region is GeSi, and the content of Ge in the material of the part of the active structure located in the channel region is greater than the content of Ge in the material of the stress source structure. In this case, the content of Ge in the material of the stress source structure is low. At this time, the stress source layer of the stress source structure can be used to apply compressive stress to the channel layer used to manufacture the channel region, so as to improve the driving performance of the P type ring gate transistor.

[0049] For example, in the case that the conductive type of the ring gate transistor is P type, the material of the part of the active structure located in the channel region is Ge, and the material of the stress source structure is Si 0.5 Ge 0.5 For example, in the case that the conductive type of the ring gate transistor is P type, the material of the part of the active structure located in the channel region is Si 0.2 Ge 0.8 , and the material of the stress source structure is Si 0.6 Ge 0.4 .

[0050] It should be noted that in the case that the material of the part of the active structure located in the channel region and the material of the stress source structure both contain Ge, the difference between the content of Ge in the material of the part of the active structure located in the channel region and the content of Ge in the material of the stress source structure can be set according to actual needs, as long as it can be applied to the ring gate transistor provided in the embodiments of the present application.

[0051] For example, in the case that the material of the part of the active structure located in the channel region and the material of the stress source structure both contain Ge, the absolute value of the difference between the content of Ge in the material of the part of the active structure located in the channel region and the content of Ge in the material of the stress source structure is greater than or equal to 20% and less than or equal to 50%. In this case, the difference between the content of Ge in the material of the stress source structure and the material of the part of the active structure located in the channel region is large, which can improve the stress applied by the stress source structure to the channel region, ensure that the channel region has a high carrier mobility, and further improve the driving performance of the ring gate transistor.

[0052] The thickness of the stress source structure can be set according to actual needs and is not specifically limited here. For example, the thickness of the portion of the stress source structure located below the channel region can be greater than or equal to 10 nm and less than or equal to 100 nm. For instance, the thickness of the portion of the stress source structure located below the channel region can be 10 nm, 30 nm, 60 nm, 90 nm, or 100 nm, etc.

[0053] In one example, the stress source structure may be doped with impurities, and the doping type of the impurities in the stress source structure is opposite to that of the impurities in the source and drain regions, respectively, to suppress source-drain leakage current and improve the electrical performance of the gate-around-the-loop transistor. Furthermore, the doping concentration of the impurities on the side of the stress source structure closest to the channel region is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 19 cm -3 .

[0054] In some cases, such as Figure 10 and Figure 12 As shown, the gate-around transistor provided in this embodiment of the invention may further include a shallow trench isolation structure 26, sidewalls 28, and a dielectric layer 32. The shallow trench isolation structure 26 defines the active region of the semiconductor substrate. The shallow trench isolation structure 26 can be made of insulating materials such as SiN, Si3N4, SiO2, or SiCO. The sidewalls 28 are located on both sides of the gate stack structure 34 along its length, and are used to isolate the gate stack structure 34 from the subsequently formed conductive structure, ensuring that the gate-around transistor has good electrical characteristics. The dielectric layer 32 covers the semiconductor substrate. Furthermore, the top of the dielectric layer 32 is flush with the top of the gate stack structure 34. It should be understood that during the manufacturing process of the gate-around transistor provided in this embodiment of the invention, such as... Figure 10 and Figure 11 As shown, the presence of dielectric layer 32 protects the source region 29 and drain region 30 from etching, cleaning, and other operations during the etching of the sacrificial gate 27. Specifically, the sidewall 28 or dielectric layer 32 can be made of insulating materials such as SiO2 or SiN.

[0055] As can be seen from the above, such as Figure 12As shown, in the ring-gate transistor provided in this embodiment of the invention, the material of the portion of the active structure located within the channel region 33 is silicon, germanium-silicon, or germanium. Additionally, the ring-gate transistor also includes a stress source structure 31 located between the gate stack structure 34 and the buried oxide layer 13, and the material of this stress source structure 31 is germanium-silicon. It is understood that when the material of the portion of the active structure located within the channel region 33 is silicon or germanium, the material of the stress source structure 31 is different from the material of the portion of the active structure located within the channel region 33. Furthermore, when the material of the portion of the active structure located within the channel region 33 is germanium-silicon, the germanium content in the materials of the stress source structure 31 and the portion of the active structure located within the channel region 33 is different. In this case, the material of the stress source structure 31 is also different from the material of the portion of the active structure located within the channel region 33. Furthermore, the stress source structure 31 is at least disposed below the channel region 33. In this case, during the actual manufacturing process, such as... Figures 3 to 12 As shown, after a stress source layer 16 for manufacturing a stress source structure 31 is formed on the buried oxide layer 13, and a channel layer 21 for manufacturing a channel region 33 is formed above the stress source layer 16, the material of the stress source structure 31 is different from the material of the part of the active structure located in the channel region 33, and the material of the stress source layer 16 is also different from the material of the channel layer 21. Furthermore, due to the different lattice constants between the different materials, there may be a lattice mismatch problem when the two different material films form a heterojunction. Stress is generated in the stress source layer 16 and the channel layer 21 near the interface, thereby applying stress to the channel layer 21 through the stretching or compression of external forces. This achieves the application of stress to the channel region 33 manufactured by the channel layer 21 through the stress source layer 16 for manufacturing the stress source structure 31. This solves the problem in the prior art where the source and drain regions formed by the source-drain epitaxial process have a large number of defects, which causes the effect of applying stress to the channel region to gradually weaken. This ensures that the channel region 33 has a high carrier mobility and improves the driving performance of the gate ring transistor.

[0056] like Figure 13 As shown, this embodiment of the invention provides a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 1 to 12 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes the following steps:

[0057] First, such as Figure 3 As shown, a semiconductor substrate 18 is formed. The semiconductor substrate 18 has a buried oxide layer 13. The specific structure of the semiconductor substrate 18 can be referred to the previous text, and will not be repeated here.

[0058] In one example, forming a semiconductor substrate as described above may include the step of: first, providing a silicon-on-insulator substrate. For example... Figure 1As shown, the silicon-on-insulator substrate 11 includes a silicon substrate 12, a buried oxide layer 13, and a silicon layer 14 stacked sequentially. Next, as... Figure 1 As shown, a diffusion layer 15 is formed that completely covers the silicon layer 14. The material of the diffusion layer 15 is germanium-silicon. Next, as... Figure 2 As shown, selective oxidation is performed on the diffusion layer and the silicon layer to allow germanium elements in the diffusion layer to diffuse into the silicon layer, forming a stress source layer 16 and a silicon oxide layer 17 sequentially stacked along the thickness direction of the silicon substrate 12 on the buried oxide layer 13. Then, as... Figure 3 As shown, the silicon oxide layer is removed to obtain the semiconductor substrate 18.

[0059] In practical applications, the aforementioned diffusion layer can be formed using processes such as epitaxial growth. Subsequently, during selective oxidation, the diffusion layer serves as a diffusion source, diffusing germanium into the silicon layer within the silicon substrate on the insulator to form a stress source layer for fabricating the stress source structure. Based on this, the thickness of the diffusion layer and the germanium content within its material can be determined according to the thickness of the stress source structure, its material and doping characteristics, the thickness of the silicon layer, and the specific application scenario; no specific limitations are imposed here. For example, the germanium content in the diffusion layer can be 10% to 40%, and the thickness can be 30 nm to 200 nm. Furthermore, the temperature for selective oxidation of the diffusion layer and silicon layer can be 1000℃ to 1150℃, and the time can be 300 min to 600 min. Of course, other suitable values ​​can be set for the temperature and time of the selective oxidation process depending on the specific requirements of the application scenario. Specifically, during the selective oxidation process, the silicon element in the diffusion layer reacts with oxygen to form a silicon oxide layer. At least some of the germanium element in the diffusion layer diffuses downwards into the silicon layer, thereby forming the stress source layer through germanium oxidation concentration. Finally, the silicon oxide layer can be removed by methods such as wet etching to expose the stress source layer.

[0060] Next, as Figure 11 As shown, a stress source structure 31 and an active structure are formed on the buried oxide layer 13. The active structure includes a source region 29, a drain region 30, and a channel region 33 located between the source region 29 and the drain region 30. The material of the portion of the active structure located within the channel region 33 is silicon, germanium-silicon, or germanium. The stress source structure 31 is disposed at least below the channel region 33. The material of the stress source structure 31 is germanium-silicon, and when the material of the portion of the active structure located within the channel region 33 is germanium-silicon, the germanium content in the materials of the stress source structure 31 and the portion of the active structure located within the channel region 33 differs.

[0061] For details on the materials and specific structures of active structures and stress source structures, please refer to the previous text; they will not be repeated here.

[0062] In one example, forming the stress source structure and active structure on the buried oxide layer may include the following steps:

[0063] like Figure 4 As shown, at least one stack 19 is formed to cover the stress source layer 16. Each stack 19 includes a sacrificial layer 20 and a channel layer 21 located on the sacrificial layer 20.

[0064] In practical applications, the aforementioned channel layer is used at least to form the portion of the active structure located within the channel region. Therefore, the material and number of layers in the stack can be determined based on the material of the portion of the active structure located within the channel region, as well as the number and arrangement of the nanostructures included in the channel region. Furthermore, when the channel region includes only one nanostructure layer, the aforementioned sacrificial layer is used to form the gap between the nanostructure and the stress source structure. When the channel region includes multiple nanostructures, the aforementioned sacrificial layer is also used to form the gap between adjacent nanostructure layers. The gate stack structure surrounds the outer periphery of the channel region through these gaps, so the thickness of the sacrificial layer can be determined based on the specifications of the gate stack structure. The material of the sacrificial layer can be any semiconductor material different from that of the nanostructure and the stress source structure.

[0065] like Figure 5 As shown, at least one stacked layer and a stress source layer are patterned to form a fin 22 on a semiconductor substrate. Along the length of the fin 22, the fin 22 includes a first region 23, a second region 24, and a third region 25 located between the first region 23 and the second region 24. The portion of the channel layer 21 included in the at least one stacked layer located in the third region 25 corresponds to the portion of the active structure located in the channel region 33.

[0066] In practical applications, photolithography and etching processes can be used to etch downwards from the top layer of the stack down to the stress source layer to obtain the fins. Next, as... Figure 6 As shown, shallow trench isolation structures 26 can be formed on the portion of the buried oxide layer 13 exposed outside the fin 22 using processes such as deposition and etching. The top height of the shallow trench isolation structure 26 is less than or equal to the bottom height of the underlying sacrificial layer. Then, as... Figure 7 As shown, processes such as deposition and selective etching can be used to sequentially form the sacrificial gate 27 and sidewall 28 across the exposed portion of the third region of the fin 22.

[0067] like Figure 11 As shown, the portions of the fin located in the first and second regions are processed to obtain source region 29 and drain region 30. The remaining portion of the stress source layer forms stress source structure 31.

[0068] In practical applications, under the masking effect of the sacrificial gate and sidewalls, processes such as ion implantation can be used to directly dope the exposed portions of the first and second regions of the fin, obtaining the source and drain regions of the active structure. Alternatively, as... Figure 8 As shown, the portion of the fin located in the first and second regions can also be removed using an etching process under the masking effect of the sacrificial gate 27 and the sidewall 28. Then, as... Figure 9 As shown, by using processes such as epitaxial growth, source region 29 and drain region 30 are formed on both sides along the length direction of the remaining part of the fin.

[0069] Next, as Figure 10 As shown, a dielectric layer 32 covering the semiconductor substrate can be formed using processes such as deposition and chemical mechanical planarization. The top of this dielectric layer 32 is flush with the top of the sacrificial gate 27. Then, as... Figure 11 As shown, under the protection of the dielectric layer 32, wet etching or dry etching processes can be used to remove the sacrificial gate and the remaining part of the sacrificial layer, exposing the channel region 33 included in the active structure.

[0070] Next, as Figure 12 As shown, a gate stack structure 34 surrounding the channel region 33 can be formed using processes such as atomic layer deposition. The stress source structure 31 is located between the gate stack structure 34 and the buried oxide layer 13. The specific structure and materials of the gate stack structure 34 can be referred to the previous text, and will not be repeated here.

[0071] It should be noted that active structures and gate stack structures can be formed in various ways. How to form active structures and gate stack structures is not the main feature of this invention; therefore, this specification only provides a brief description to enable those skilled in the art to easily implement this invention. Those skilled in the art can certainly conceive of other ways to fabricate the above structures.

[0072] Compared with the prior art, the beneficial effects of the manufacturing method of the ring gate transistor provided in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the ring gate transistor provided in the embodiments of the present invention, which will not be repeated here.

[0073] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0074] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A gate-ring transistor, characterized in that, include: A semiconductor substrate having a buried oxide layer; An active structure is formed on the buried oxide layer; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; the material of the portion of the active structure located in the channel region is silicon, silicon germanium, or germanium; A grid stack structure surrounds the outer periphery of the channel region; The stress source structure is disposed at least below the channel region and between the gate stack structure and the buried oxide layer; The stress source structure is made of germanium-silicon; When the material of the portion of the active structure located in the channel region is germanium-silicon, the germanium content in the stress source structure and the material of the portion of the active structure located in the channel region are different, and the absolute value of the difference in germanium content between the material of the portion of the active structure located in the channel region and the material of the stress source structure is greater than or equal to 20% and less than or equal to 50%.

2. The gate-ring transistor according to claim 1, characterized in that, The germanium content in the material of the stress source structure gradually increases from the bottom to the top.

3. The gate-ring transistor according to claim 1, characterized in that, The conduction type of the gate ring transistor is N-type; The active structure located within the channel region is made of silicon; or, the active structure located within the channel region is made of germanium-silicon, and the germanium content in the active structure located within the channel region is less than the germanium content in the stress source structure.

4. The gate-ring transistor according to claim 1, characterized in that, The conduction type of the gate ring transistor is P-type; The active structure located within the channel region is made of germanium; or, the active structure located within the channel region is made of germanium-silicon, and the germanium content in the active structure located within the channel region is greater than the germanium content in the stress source structure.

5. The gate-to-ring transistor according to claim 1, characterized in that, The thickness of the portion of the stress source structure located below the channel region is greater than or equal to 10 nm and less than or equal to 100 nm; and / or, The material of the stress source structure contains germanium with a content greater than or equal to 30% and less than or equal to 70%.

6. The gate-to-ring transistor according to claim 5, characterized in that, The stress source structure is doped with impurities, and the doping type of the impurities in the stress source structure is opposite to the doping type of the impurities in the source region and the drain region, respectively. The doping concentration of the impurities on the side of the stress source structure closest to the channel region is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 19 cm -3 .

7. The gate-ring transistor according to claim 1, characterized in that, The portion of the active structure located within the source region and the drain region is an epitaxial structure formed on the buried oxide layer.

8. A method for manufacturing a gate-ring transistor, characterized in that, include: Form a semiconductor substrate; The semiconductor substrate has a buried oxide layer; A stress source structure and an active structure are formed on the buried oxide layer; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; the material of the portion of the active structure located in the channel region is silicon, silicon germanium, or germanium; the stress source structure is disposed at least below the channel region. The stress source structure is made of germanium-silicon; When the material of the portion of the active structure located within the channel region is germanium-silicon, the germanium content in the stress source structure and the material of the portion of the active structure located within the channel region are different, and the absolute value of the difference in germanium content between the material of the portion of the active structure located within the channel region and the material of the stress source structure is greater than or equal to 20% and less than or equal to 50%; A gate stack structure is formed around the outer periphery of the channel region; the stress source structure is located between the gate stack structure and the buried oxide layer.

9. The method for manufacturing a gate-to-ring transistor according to claim 8, characterized in that, The process of forming a semiconductor substrate includes: A silicon-on-insulator substrate is provided; the silicon-on-insulator substrate includes a silicon substrate, the buried oxide layer and the silicon layer stacked sequentially; A diffusion layer is formed that covers the entire silicon layer; the material of the diffusion layer is germanium-silicon. The diffusion layer and the silicon layer are selectively oxidized to allow germanium elements in the diffusion layer to diffuse into the silicon layer, thereby forming a stress source layer and a silicon oxide layer that are sequentially stacked along the thickness direction of the silicon substrate on the buried oxide layer. Remove the silicon oxide layer to obtain the semiconductor substrate.

10. The method for manufacturing a gate-to-ring transistor according to claim 9, characterized in that, The formation of stress source structures and active structures on the buried oxide layer includes: Form at least one stack that completely covers the stress source layer; each of the stacks includes a sacrificial layer and a channel layer located on the sacrificial layer; The at least one stack and the stress source layer are patterned to form fins on the semiconductor substrate; along the length direction of the fins, the fins include a first region, a second region, and a third region located between the first region and the second region; the portion of the channel layer included in the at least one stack located in the third region corresponds to the portion of the active structure located in the channel region; The portions of the fin located in the first and second regions are processed to obtain the source region and the drain region; the remaining portion of the stress source layer forms the stress source structure.

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