Semiconductor memory device and method of manufacturing the semiconductor memory device

Abstract

A semiconductor memory device and a manufacturing method thereof are provided. The semiconductor memory device includes a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked in a vertical direction, a dummy stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers alternately stacked in the vertical direction, the dummy stack structure being disposed at a height at which the gate stack structure is disposed, a channel structure penetrating the gate stack structure, a memory layer disposed between each of the plurality of conductive patterns and the channel structure, and a dummy pillar penetrating a portion of the dummy stack structure in the vertical direction with a length less than a length of the channel structure.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memory devices and methods for manufacturing such semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices and methods for manufacturing such three-dimensional semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices include multiple memory cells capable of storing data. Three-dimensional semiconductor memory devices may include multiple memory cells arranged in three dimensions. Therefore, compared to semiconductor memory devices comprising multiple memory cells arranged in two dimensions, three-dimensional semiconductor memory devices can increase the integration density of memory cells within a limited area. The integration density of three-dimensional semiconductor memory devices can be further increased by increasing the number of memory cells stacked in the vertical direction. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a semiconductor memory device is provided, which may include: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked in a vertical direction; a dummy stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers alternately stacked in a vertical direction, the dummy stack structure being disposed at a height disposed on the gate stack structure; a channel structure penetrating the gate stack structure; a memory layer disposed between each of the plurality of conductive patterns and the channel structure; and a dummy pillar penetrating a portion of the dummy stack structure, wherein the length of the dummy pillar in the vertical direction is less than the length of the channel structure.

[0004] According to another embodiment of this disclosure, a method for manufacturing a semiconductor memory device is provided. The method may include: forming a lower stacked structure including a lower die region and a lower chip region; forming a lower via through the lower die region of the lower stacked structure; forming a measurement post in the lower via, the measurement post including a buried layer disposed at the lower part of the lower via and a reflective metal layer and an etch stop layer disposed at the upper part of the lower via; forming an upper stacked structure on the lower stacked structure to cover the measurement post; and forming an upper via overlapping the measurement post, the upper via penetrating the upper stacked structure. Attached Figure Description

[0005] Examples of embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to enable those skilled in the art to implement this disclosure.

[0006] In the accompanying drawings, dimensions may have been enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, that element may be the only element between the two elements, or there may be additional intermediate elements. Throughout the drawings, the same reference numerals denote the same elements.

[0007] Figure 1 This is a plan view illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B and Figure 2C This is a cross-sectional view illustrating a first type of dummy column according to various embodiments of the present disclosure.

[0009] Figure 3 This is a cross-sectional view illustrating the dummy stacked structure and gate stacked structure of a semiconductor memory device according to one embodiment of the present disclosure.

[0010] Figure 4 and Figure 5 This is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 6 This is a plan view of a substrate according to one embodiment of the present disclosure.

[0012] Figure 7A and Figure 7B The diagram illustrates, for example, the process of forming a lower-layer structure and the process of forming multiple columns.

[0013] Figure 8A and Figure 8B This is a cross-sectional view illustrating, for example, the process of forming an upper-layered structure and the process of forming multiple holes.

[0014] Figure 9 , Figure 10A , Figure 10B and Figure 10C This is a view illustrating the overlapping measurement method.

[0015] Figure 11A and Figure 11B This is a cross-sectional view illustrating, for example, the process of creating channel holes.

[0016] Figure 12A and Figure 12B This is a cross-sectional view illustrating, for example, the process of forming memory layers and cell pillars.

[0017] Figure 13 This is a cross-sectional view illustrating, for example, a process for forming multiple conductive patterns.

[0018] Figure 14 This is a block diagram illustrating the configuration of a memory system according to one embodiment of the present disclosure.

[0019] Figure 15 This is a block diagram illustrating the configuration of a computing system according to one embodiment of the present disclosure. Detailed Implementation

[0020] The specific structural and functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure can be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0021] It should be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, not to imply the number or order of elements.

[0022] Embodiments of this disclosure can provide a semiconductor memory device capable of reducing structural defects and a method for manufacturing the semiconductor memory device.

[0023] Figure 1 This is a plan view illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0024] Reference Figure 1 The semiconductor memory device may include a cell array region (CAR) and a connection region (CNR) extending from the cell array region (CAR). The semiconductor memory device may include a gate stack structure (GST), a dummy stack structure (DST), a plurality of first-type dummy pillars (DPL1) buried in the dummy stack structure (DST), conductive contact plugs (CT) penetrating the dummy stack structure (DST), a plurality of cell pillars (CPL) penetrating the gate stack structure (GST), a memory layer (ML) surrounding the sidewall of each of the cell pillars (CPL), a plurality of second-type dummy pillars (DPL2) penetrating the gate stack structure (GST), and a vertical insulating layer (VI) located between the gate stack structure (GST) and the dummy stack structure (DST).

[0025] Each of the multiple cell pillars (CPL), multiple first-type dummy pillars (DPL1), multiple second-type dummy pillars (DPL2), and the vertical insulating layer (VI) can extend in a vertical direction, and the gate stack structure (GST) can extend in a direction intersecting with the multiple cell pillars (CPL). The first direction (D1), second direction (D2), and third direction (D3) shown in the figure are the directions facing each other's intersecting axes. For example, the first direction (D1), second direction (D2), and third direction (D3) can be defined as the directions facing the X-axis, Y-axis, and Z-axis of the XYZ coordinate system, respectively. The third direction (D3) shown in the figure can correspond to the aforementioned vertical direction.

[0026] The sidewalls of the gate stack structure GST can be defined by slits SI. The slits SI can be filled with various materials. In one embodiment, the slits SI can be filled with an insulating material. In another embodiment, the slits SI can be filled with a vertical conductive pattern and a sidewall insulating layer located between the vertical conductive pattern and the gate stack structure GST. Multiple cell pillars CPLs can be disposed in the cell array region CAR and surrounded by the gate stack structure GST. Memory layers ML can be disposed between their corresponding cell pillars and the gate stack structure GST.

[0027] The gate stack structure (GST) can extend from the cell array region (CAR) to the connection region (CNR). The gate stack structure (GST) can have sidewalls extending along the vertical insulating layer (VI) in the connection region (CNR).

[0028] The vertical insulating layer VI can be disposed between the dummy stack structure DST and the gate stack structure GST in the connection region CNR, and surround the sidewall of the dummy stack structure DST. The slit SI can extend from the cell array region CAR to the connection region CNR and is adjacent to the vertical insulating layer VI.

[0029] Each of the plurality of first-type dummy columns DPL1 can be configured to have a length smaller than the length of each of the plurality of unit columns CPL and the plurality of second-type dummy columns DPL2 in a third direction D3, which is the vertical direction. For example, refer to Figure 2A The first type of dummy pillar DPL1 can be formed with a length L1 on the third direction D3 that is less than the length L2 of the unit pillar CPL. Multiple first type dummy pillars DPL1 can extend through a portion of the dummy stack structure DST, and another portion of the dummy stack structure DST can cover multiple first type dummy pillars DPL1. Multiple second type dummy pillars DPL2 can be used as supports to structurally support the gate stack structure GST.

[0030] The first type dummy pillar DPL1 and the second type dummy pillar DPL2 can be formed with different structures. In one embodiment, the second type dummy pillar DPL2 can be configured as an insulating pillar that penetrates the gate stack structure GST. In another embodiment, the second type dummy pillar DPL2 may include the same material layer as the cell pillar CPL and the same material layer as the memory layer ML, and is formed with the same structure as the cell pillar CPL and the memory layer ML.

[0031] The first type of dummy pillar DPL1 may include the same material layer as a measurement pillar formed in the process of manufacturing a semiconductor memory device. The first type of dummy pillar DPL1 may include at least three material layers. Hereinafter, the first type of dummy pillar DPL1 will be described based on various embodiments of the present disclosure.

[0032] Figures 2A to 2C This is a cross-sectional view illustrating a first type of dummy column according to various embodiments of the present disclosure. Figures 2A to 2C Each example in the example shows along Figure 1 The cross-section of the connection region CNR taken by line I-I' of the dummy stacked structure DST of the semiconductor memory device shown, and along... Figure 1 The cross-section of the cell array region CAR is taken from line II-II' of the gate stack structure GST of the semiconductor memory device shown.

[0033] Reference Figures 2A to 2C The dummy layer structure DST may include a plurality of dummy interlayer insulating layers 111A1 and 111B1 and a plurality of sacrificial layers 613A and 613B alternately stacked on a third direction D3. The plurality of sacrificial layers 613A and 613B may be formed of an insulating material different from the insulating material of the plurality of dummy interlayer insulating layers 111A1 and 111B1. In one embodiment, the plurality of dummy interlayer insulating layers 111A1 and 111B1 may be formed of silicon oxide, while the plurality of sacrificial layers 613A and 613B may be formed of silicon nitride.

[0034] Multiple dummy interlayer insulating layers 111A1 and 111B1 and multiple sacrificial layers 613A and 613B can be divided into layers constituting a first type of dummy stack structure DST1 and layers constituting a second type of dummy stack structure DST2. The first type of dummy stack structure DST1 and the second type of dummy stack structure DST2 can be stacked on a third direction D3.

[0035] The multiple dummy interlayer insulation layers 111A1 and 111B1 may include multiple first dummy interlayer insulation layers 111A1 and multiple second dummy interlayer insulation layers 111B1. The first type of dummy stack structure DST1 and the second type of dummy stack structure DST2 may be stacked on a third direction D3.

[0036] Multiple sacrificial layers 613A and 613B may include multiple first sacrificial layers 613A and multiple second sacrificial layers 613B. A first type of dummy stack structure DST1 may include a first dummy stack structure formed by multiple first dummy interlayer insulating layers 111A1 and multiple first sacrificial layers 613A alternately arranged in the third direction D3. A second type of dummy stack structure DST2 may include multiple second dummy interlayer insulating layers 111B1 and multiple second sacrificial layers 613B alternately arranged in the third direction D3.

[0037] The dummy layer structure DST can be positioned at the height of the gate layer structure GST. The gate layer structure GST may include multiple interlayer insulating layers 111A2 and 111B2 and multiple conductive patterns 113A and 113B alternately stacked on the third direction D3. The multiple interlayer insulating layers 111A2 and 111B2 and the multiple conductive patterns 113A and 113B can be divided into layers constituting a first type gate layer structure GST1 and layers constituting a second type gate layer structure GST2. The first type gate layer structure GST1 and the second type gate layer structure GST2 can be stacked on the third direction D3.

[0038] A first type gate stack structure GST1 can be disposed at the height set by a first type dummy stack structure DST1, and a second type gate stack structure GST2 can be disposed at the height set by a second type dummy stack structure DST2. Multiple interlayer insulating layers 111A2 and 111B2 may include multiple first interlayer insulating layers 111A2 and multiple second interlayer insulating layers 111B2. Multiple conductive patterns 113A and 113B may include multiple first conductive patterns 113A and multiple second conductive patterns 113B. Multiple first interlayer insulating layers 111A2 can be disposed at the height set by multiple first dummy interlayer insulating layers 111A1, multiple first conductive patterns 113A can be disposed at the height set by multiple first sacrificial layers 613A, multiple second interlayer insulating layers 111B2 can be disposed at the height set by multiple second dummy interlayer insulating layers 111B1, and multiple second conductive patterns 113B can be disposed at the height set by multiple second sacrificial layers 613B. The first type of gate stack structure GST1 may include a first gate stack structure consisting of a plurality of first interlayer insulating layers 111A2 and a plurality of first conductive patterns 113A alternately stacked on the third direction D3. The second type of gate stack structure GST2 may include a plurality of second interlayer insulating layers 111B2 and a plurality of second conductive patterns 113B alternately stacked on the third direction D3.

[0039] The first type of dummy stacked structure DST1 can be penetrated by the first type of dummy column DPL1. The second type of dummy stacked structure DST2 can be set at a different height than the first type of dummy column DPL1. The second type of dummy stacked structure DST2 can extend to cover the first type of dummy column DPL1.

[0040] The cell pillar CPL can extend in the third direction D3 to penetrate the first type gate stack structure GST1 and the second type gate stack structure GST2. A memory layer ML can be disposed between each conductive pattern 113A or 113B and the cell pillar CPL. In one embodiment, the memory layer ML can extend along the sidewall of the cell pillar CPL. The cell pillar CPL can include a channel structure CH. The channel structure CH can be configured as a semiconductor layer including silicon or the like and serves as a channel region. The channel structure CH can be formed in various structures including cylindrical shapes, tubular shapes, etc. In one embodiment, the channel structure CH can be formed in a tubular shape. The cell pillar CPL can also include a core insulating layer CO and a capping pattern CAP filling the central region of the tubular channel structure CH. The capping pattern CAP can be formed of a semiconductor material including silicon or the like. A portion of the capping pattern CAP and the channel structure CH in contact with the capping pattern CAP can constitute a channel doped region including a conductivity type dopant. In one embodiment, the channel doped region can include an n-type impurity.

[0041] A memory layer ML can be disposed between a gate stack structure GST and a channel structure CH. The memory layer ML can include various data storage materials. Data storage materials can include charge trapping layers, ferroelectric layers, phase change material layers, ferromagnetic material layers, nanodots, etc. In one embodiment, the memory layer ML can include a tunneling insulating layer between the gate stack structure GST and the channel structure CH, a data storage layer between the tunneling insulating layer and the gate stack structure GST, and a barrier insulating layer between the data storage layer and the gate stack structure GST. The data storage layer can be formed of silicon nitride capable of trapping charge, and the tunneling insulating layer can be formed of silicon oxide capable of tunneling charge. The barrier insulating layer can be formed of an insulating material for charge blocking. In one embodiment, the barrier insulating layer can include at least one of silicon oxide and a metal oxide.

[0042] The memory layer ML and the cell pillar CPL may have an inflection point at the first gate interface IF1' between the first type gate stack structure GST1 and the second type gate stack structure GST2, or in the region adjacent to the first gate interface IF1'.

[0043] The first type of dummy stack structure DST1 can be penetrated by a group of dummy vias. The group of dummy vias may include dummy vias 621 penetrating multiple first dummy interlayer insulating layers 111A1 and multiple first sacrificial layers 613A of the first dummy stack structure. The dummy vias 621 may include a first portion P1 adjacent to the first inter-dummy interface IF1 between the first type of dummy stack structure DST1 and the second type of dummy stack structure DST2, and a second portion P2 extending from the first portion P1 in a direction away from the first inter-dummy interface IF1. The volume of the second portion P2 may be larger than the volume of the first portion P1.

[0044] The first type of dummy post DPL1 may include a first dummy post disposed in a dummy hole 621. The first dummy post may include a buried layer 121, an etch stop layer 127A, 127B or 127 and a reflective metal layer 125A, 125B or 125C.

[0045] The buried layer 121 may be disposed in the second portion P2 of the dummy via 621. Compared to the etch stop layers 127A, 127B, or 127 and the reflective metal layers 125A, 125B, or 125C disposed in the first portion P1, which has a relatively small volume, the buried layer 121 disposed in the second portion P2, which has a larger volume compared to the first portion P1, may be formed of a material that applies relatively low stress to the gate stack structure GST. In order to reduce the stress applied to the gate stack structure GST, the buried layer 121 may be formed of a material with a hardness lower than that of the etch stop layers 127A, 127B, or 127 and the reflective metal layers 125A, 125B, or 125C. In one embodiment, the buried layer 121 may be a carbon-based material including an amorphous carbon layer, etc. The pores 123 may be retained in the buried layer 121, but the embodiments of this disclosure are not limited thereto. For example, the second portion P2 of the dummy via 621 may be filled with the buried layer 121 without pores 123.

[0046] Etch stop layers 127A, 127B, or 127 may be disposed in a portion of the first portion P1 of the dummy via 621. Etch stop layers 127A, 127B, or 127 may be formed from a material selected in addition to the etch selectivity in the dry etching process, taking into account ion scattering in the dry etching process. In one embodiment, etch stop layers 127A, 127B, or 127 may comprise a titanium nitride (TiN) layer. Reference will be made later. Figure 8A and Figure 8B To describe etching selectivity and ion scattering.

[0047] The material of the reflective metal layers 125A, 125B, or 125C can be selected by considering the detection efficiency of the backscattering electrode in the overlay measurement. To improve the detection efficiency of the backscattering electrode, the reflective metal layers 125A, 125B, or 125C can be formed of a material with a higher atomic number (high z material) compared to the etch stop layers 127A, 127B, or 127. In one embodiment, the reflective metal layers 125A, 125B, or 125C can be formed of a material with an atomic number greater than 55. For example, the reflective metal layers 125A, 125B, or 125C may include at least one of tantalum and tungsten.

[0048] The etch stop layer 127A, 127B or 127 and the reflective metal layer 125A, 125B or 125C can be configured in various structures in the first part P1 of the dummy hole 621.

[0049] Reference Figure 2A According to one embodiment of this disclosure, the reflective metal layer 125A and the etch stop layer 127A included in the first dummy pillar DPL1A can be stacked on the buried layer 121 in the third direction D3. In other words, the etch stop layer 127A can be positioned closer to the first interface IF1 between dummy pillars than the reflective metal layer 125A, and the reflective metal layer 125A can be positioned between the buried layer 121 and the etch stop layer 127A.

[0050] Reference Figure 2B According to one embodiment of this disclosure, the reflective metal layer 125B included in the first dummy pillar DPL1B can be disposed in the central region of the first portion P1 of the dummy hole 621. The etch stop layer 127B included in the first dummy pillar DPL1B can extend along the sidewall of the first portion P1 and surround the sidewall of the reflective metal layer 125B. The etch stop layer 127B can extend between the reflective metal layer 125B and the buried layer 121.

[0051] Reference Figure 2C According to one embodiment of the present disclosure, the first dummy post DPL1C may include a reflective metal layer 125C, a backing pattern 127C1, and a core pattern 127C2. The backing pattern 127C1 and the core pattern 127C2 may be separated from each other by the reflective metal layer 125C. Each of the backing pattern 127C1 and the core pattern 127C2 may be configured as an etch stop layer 127. The backing pattern 127C1 may extend along the surface of the buried layer 121 facing the third-party direction D3 and the sidewall of the first portion P1 of the dummy hole 621. The core pattern 127C2 may be disposed in the central region of the first portion P1. The reflective metal layer 125C may be disposed between the backing pattern 127C1 and the core pattern 127C2.

[0052] Figure 3This is a cross-sectional view illustrating the dummy stacked structure and gate stacked structure of a semiconductor memory device according to one embodiment of the present disclosure. Figure 3 Show along Figure 1 The cross-section of the connection region CNR taken by line I-I' of the dummy stacked structure DST of the semiconductor memory device shown, and along... Figure 1 The cross-section of the cell array region CAR, taken from line II-II' of the gate stack structure GST of the semiconductor memory device shown. For simplicity, the relationship with... Figures 2A to 2C The components shown are repeated descriptions of the same components.

[0053] Reference Figure 3 The dummy stack structure DST may include a plurality of dummy interlayer insulating layers 111A1', 111A1, and 111B1 alternately stacked on the third direction D3, and a plurality of sacrificial layers 613A', 613A, and 613B. The dummy stack structure DST may include a first type dummy stack structure DST1 and a second type dummy stack structure DST2 stacked on the third direction D3. The first type dummy stack structure DST1 may include not only a first dummy stack structure DST11 in contact with the second type dummy stack structure DST2, but also at least one second dummy stack structure DST12 overlapping the first dummy stack structure DST11 in the direction opposite to the third direction D3. Although in Figure 3 The illustration shows a second dummy stack structure DST12, but embodiments of the present disclosure are not limited thereto. In one embodiment, two or more second dummy stack structures may be stacked on a third direction D3.

[0054] The plurality of dummy interlayer insulating layers 111A1', 111A1, and 111B1 may include not only the plurality of first dummy interlayer insulating layers 111A1 of the first dummy stacked structure DST11 and the plurality of second dummy interlayer insulating layers 111B1 of the second type of dummy stacked structure DST2, but may also include a plurality of lower dummy interlayer insulating layers 111A1'. The plurality of sacrificial layers 613A', 613A, and 613B may include not only the plurality of first sacrificial layers 613A of the first dummy stacked structure DST11 and the plurality of second sacrificial layers 613B of the second type of dummy stacked structure DST2, but may also include a plurality of lower sacrificial layers 613A'. The plurality of lower dummy interlayer insulating layers 111A1' and the plurality of lower sacrificial layers 613A' may be alternately stacked on a third direction D3 and constitute the second dummy stacked structure DST12.

[0055] The gate stack structure GST may include a plurality of interlayer insulating layers 111A2', 111A2, and 111B2 alternately stacked on the third-direction D3, and a plurality of conductive patterns 113A', 113A, and 113B. The gate stack structure GST may include a first type gate stack structure GST1 and a second type gate stack structure GST2 stacked on the third-direction D3. The first type gate stack structure GST1 may include not only a first gate stack structure GST11 in contact with the second type gate stack structure GST2, but also at least one second gate stack structure GST12 overlapping the first gate stack structure GST11 in the direction opposite to the third-direction D3. Although in Figure 3 An example of a second gate stack structure GST12 is illustrated, but embodiments of the present disclosure are not limited thereto. In one embodiment, two or more second gate stack structures may be stacked on a third-direction D3.

[0056] The multiple interlayer insulating layers 111A2', 111A2, and 111B2 may include not only the multiple first interlayer insulating layers 111A2 of the first gate stack structure GST11 and the multiple second interlayer insulating layers 111B2 of the second type gate stack structure GST2, but may also include multiple lower interlayer insulating layers 111A2'. The multiple conductive patterns 113A', 113A, and 113B may include not only the multiple conductive patterns 113A of the first gate stack structure GST11 and the multiple second conductive patterns 113B of the second type gate stack structure GST2, but may also include multiple lower conductive patterns 113A'. The multiple lower interlayer insulating layers 111A2' and the multiple lower conductive patterns 113A' may be alternately stacked on the third-direction D3 and constitute the second gate stack structure GST12.

[0057] The second gate stack structure GST12 can be disposed at the height set by the second dummy stack structure DST12. Multiple lower interlayer insulating layers 111A2' can be disposed at the height set by the multiple lower dummy interlayer insulating layers 111A1' respectively, and multiple lower conductive patterns 113A' can be disposed at the height set by the multiple lower sacrificial layers 613A' respectively.

[0058] The first type of dummy post DPL1 penetrating the first type of dummy stacked structure DST1 may include a first dummy post DPL11 penetrating the first dummy stacked structure DST11 and a second dummy post DPL12 penetrating the second dummy stacked structure DST12. The first dummy post DPL11 may overlap with the second dummy post DPL12. The first dummy post DPL11 may be aligned with a reference... Figures 2A to 2CThe first dummy pillars DPL1A, DPL1B, and DPL1C are formed of the same material layer in an identical structure. The longitudinal cross-sectional structure of the second dummy pillar DPL12 may be the same as that of the first dummy pillar DPL11, and the second dummy pillar DPL12 may be formed of the same material layer as the first dummy pillar DPL11.

[0059] The cell pillar CPL can penetrate the first gate stack structure GST11 and the second gate stack structure GST12 of the first type gate stack structure GST1, and extend in the third direction D3 to penetrate the second type gate stack structure GST2. The memory layer ML can be disposed between the cell pillar CPL and each of the first gate stack structure GST11, the second gate stack structure GST12, and the second type gate stack structure GST2. See reference... Figures 2A to 2C The unit post CPL may include a channel structure CH, a core insulation layer CO, and a capping pattern CAP.

[0060] The memory layer ML and cell pillar CPL may have inflection points at the interface between the first gate stack structure GST11, the second gate stack structure GST12, and the second type gate stack structure GST2. Alternatively, the memory layer ML and cell pillar CPL may have inflection points in a region adjacent to the interface between the first gate stack structure GST11, the second gate stack structure GST12, and the second type gate stack structure GST2.

[0061] Reference Figure 1 , Figures 2A to 2C and Figure 3 The described components may overlap with the external circuit structure. (See reference...) Figure 1 , Figures 2A to 2C and Figure 3 Each of the gate stack-up structures (GSTs) described can be disposed between the bit line and the peripheral circuit structure, or between the peripheral circuit structure and the source layer.

[0062] Figure 4 and Figure 5 This is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 4 and Figure 5 Each example in the example shows along Figure 1 The cross-section of the connection region CNR taken by line I-I' of the dummy stacked structure DST of the semiconductor memory device shown, and along... Figure 1 The cross-section of the cell array region CAR, taken from line II-II' of the gate stack structure GST of the semiconductor memory device shown. For simplicity, the relationship with... Figure 1 and Figures 2A to 2C The components shown are repeated descriptions of the same components.

[0063] Figure 4 An embodiment of a semiconductor memory device including a gate stack structure GST disposed between a bit line BL and a peripheral circuit structure PS is illustrated. Figure 5 An embodiment of a semiconductor memory device including a gate stack structure GST disposed between a peripheral circuit structure PS and a source layer SL is illustrated.

[0064] Reference Figure 4 and Figure 5 The peripheral circuit structure PS may include multiple transistor PTRs. Each transistor PTR may include a gate insulating layer GI, a gate electrode GE, and a junction JN. The gate insulating layer GI and the gate electrode GE may be stacked on the active region of the semiconductor substrate SUB. The active region of the semiconductor substrate SUB may be separated by an isolation layer ISO buried in the semiconductor substrate SUB. The junction JN may be defined as a region in the active region of the semiconductor substrate SUB located on both sides of the gate electrode GE, wherein at least one of an n-type impurity and a p-type impurity is implanted. The junction JN may be provided as the source and drain regions of its corresponding transistor PTR.

[0065] Multiple transistor PTRs can be connected to multiple interconnect ICs disposed on a semiconductor substrate SUB. Each interconnect IC may include conductive patterns that are connected to each other, and the conductive patterns of the interconnect ICs may be disposed in two or more layers.

[0066] The semiconductor substrate (SUB) and multiple transistor PTRs can be covered by a lower insulating structure (LIL). Multiple interconnect components (ICs) can be buried within the lower insulating structure (LIL). The lower insulating structure (LIL) may include two or more insulating layers.

[0067] The structure, including the source layer SL, bit line BL, and gate stack structure GST, can be placed on the peripheral circuit structure PS. (Refer to...) Figure 1 and Figures 2A to 2C The described gate stack structure GST can be disposed between the source layer SL and the bit line BL. However, embodiments of this disclosure are not limited thereto. In one embodiment, reference is made to... Figure 3 The described gate stack structure GST can be positioned between the source layer SL and the bit line BL.

[0068] The gate stack structure GST may include multiple interlayer insulating layers 111 and multiple conductive patterns 113 alternately stacked on the peripheral circuit structure PS. At least one conductive pattern of the multiple conductive patterns 113 adjacent to the source layer SL can be used as a source select line SSL, and at least one conductive pattern of the multiple conductive patterns 113 adjacent to the bit line BL can be used as a drain select line DSL. Although not shown in the figure, each of two or more conductive patterns of the multiple conductive patterns 113 adjacent to the source layer SL can be used as a source select line SSL, and each of two or more conductive patterns of the multiple conductive patterns 113 adjacent to the bit line BL can be used as a drain select line DSL. The conductive patterns of the multiple conductive patterns 113 located between the source select line SSL and the drain select line DSL can be used as multiple word lines WL respectively.

[0069] Reference Figure 1 and Figures 2A to 2C The described dummy stack structure DST can be disposed at the height of the gate stack structure GST. However, embodiments of this disclosure are not limited thereto. In one embodiment, reference is made to... Figure 3 The described dummy stack structure DST can be set at the height set by the gate stack structure GST.

[0070] The source cut insulation layer (SCI) can be positioned at the height set by the source layer (SL). The source cut insulation layer (SCI) can overlap with the dummy layer structure (DST).

[0071] The process for forming the structure, which includes the source layer SL, bit line BL, and gate stack structure GST, can be performed on the peripheral circuit structure PS, or provided by a process separate from the peripheral circuit structure PS.

[0072] Figure 4 An example of a semiconductor memory device is provided, for instance, by performing a process on a peripheral circuit structure PS to form a structure including a source layer SL, a bit line BL, and a gate stack structure GST.

[0073] Reference Figure 4 The gate stack structure (GST) and the dummy stack structure (DST) can be located on the source layer (SL). The third direction (D3) can be considered as the direction from the peripheral circuit structure (PS) toward the gate stack structure (GST) or the dummy stack structure (DST).

[0074] A source layer SL and a source cleavage insulating layer SCI can be disposed on a lower insulating structure LIL. In one embodiment, the source layer SL may include a first source layer SL1 and a second source layer SL2 stacked on a third-direction D3. The source layer SL may also include a third source layer SL3 located on the second source layer SL2. Each of the first source layer SL1, the second source layer SL2, and the third source layer SL3 may be configured as a doped semiconductor layer including at least one of n-type impurities and p-type impurities. In one embodiment, each of the first source layer SL1, the second source layer SL2, and the third source layer SL3 may be formed of n-type doped silicon.

[0075] The first type of dummy post DPL1 may include an end extending into the source-cut insulating layer (SCI). The first type of dummy post DPL1 may be formed as shown in reference... Figures 2A to 2C The various structures described. The first type of dummy pillar DPL1 may have a first surface facing third-party direction D3 and a second surface facing source-cutting insulating layer SCI. The first surface of the first type of dummy pillar DPL1 may be covered by a portion of the dummy stack structure DST.

[0076] The cell pillar CPL may include an end extending into the source layer SL. In one embodiment, the cell pillar CPL may penetrate through the third source layer SL3 and the second source layer SL2, and extend into the first source layer SL1.

[0077] The channel structure CH and core insulating layer CO of the unit post CPL can extend into the source layer SL. The core insulating layer CO of the unit post CPL can have a first surface facing third direction D3 and a second surface facing the source layer SL. The capping pattern CAP of the unit post CPL can contact the first surface of the core insulating layer CO.

[0078] The gate stack structure GST can be covered by a first insulating layer IL1. The first insulating layer IL1 can extend to cover the dummy stack structure DST. The first insulating layer IL1 can be penetrated by conductive bit line contacts BCT. The conductive bit line contacts BCT can contact the capping pattern CAP of the cell pillar CPL.

[0079] The first insulating layer IL1 can be covered by the second insulating layer IL2. The second insulating layer IL2 can be penetrated by the bit line BL. The bit line BL can contact the conductive bit line contact BCT.

[0080] The second source line SL2 can penetrate the memory layer ML to contact the sidewall of the channel structure CH. The memory layer ML can be divided into a first memory pattern ML1 and a second memory pattern ML2 by the second source layer SL2. The first memory pattern ML1 can be disposed between the channel structure CH and the gate stack structure GST, and extends between the channel structure CH and the third source layer SL3. The second memory pattern ML2 can be disposed between the channel structure CH and the first source layer SL1.

[0081] Figure 5 An example is a semiconductor memory device provided, for instance, by means of a structure including bit lines BL, gate stack structure GST, etc., provided via a process that allows the structure to be connected to the peripheral circuit structure PS via a bonding process.

[0082] Reference Figure 5 ,exist Figures 2A to 2C and Figure 3 Each of the gate stack structure GST and dummy stack structure DST shown in the diagram can be arranged in a vertically inverted configuration on the peripheral circuit structure PS. The third direction D3 can be considered as the direction from the gate stack structure GST or the dummy stack structure DST toward the peripheral circuit structure PS.

[0083] The peripheral circuit structure PS may also include multiple first conductive bonding patterns BP1 embedded in the lower insulating structure LIL. The multiple first conductive bonding patterns BP1 may be disposed in the uppermost layer of the peripheral circuit structure PS.

[0084] The structure, including bit line BL, gate stack structure GST, and dummy stack structure DST, can be provided through a process separate from the peripheral circuit structure PS. Bit line BL and gate stack structure GST can be formed to be electrically connected to multiple second conductive bonding patterns BP2. Some of the bit line BL and multiple second conductive bonding patterns BP2 can be disposed between the gate stack structure GST and the peripheral circuit structure PS. Other patterns of the multiple second conductive bonding patterns BP2 can be disposed between the dummy stack structure DST and the peripheral circuit structure PS.

[0085] In one embodiment, a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3 may be disposed between the gate stack structure GST and the peripheral circuit structure PS. The first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 may extend between a dummy stack structure DST and the peripheral circuit structure PS. The first insulating layer IL1 may be disposed between the second insulating layer IL2 and the gate stack structure GST, and is penetrated by a conductive bit line contact BCT. The second insulating layer IL2 may be disposed between the first insulating layer IL1 and the third insulating layer IL3, and is penetrated by a bit line BL. The third insulating layer IL3 may be disposed between the lower insulating structure LIL and the second insulating layer IL2, and is penetrated by a plurality of second conductive bonding patterns BP2.

[0086] Bit line BL can contact the capping pattern of unit post CPL via conductive bit line contact BCT. Some of the patterns in a plurality of second conductive bonding patterns BP2 can be connected to bit line BL. Bit line BL can be connected to junction JN of semiconductor substrate SUB via the second conductive bonding patterns BP2 and the first conductive bonding pattern BP1 that are bonded to each other, as well as interconnect IC.

[0087] The gate stack structure GST may include a first surface facing the peripheral circuit structure PS and a second surface facing in the opposite direction to the first surface. A source layer SL may be disposed on the second surface of the gate stack structure GST. The source layer SL may be configured as a doped semiconductor layer including at least one of n-type and p-type impurities. In one embodiment, the source layer SL may be formed of n-type doped silicon.

[0088] The first type of dummy pillar DPL1 may include an end extending into the source cleavage insulating layer SCI. The unit pillar CPL may include an end extending into the source layer SL.

[0089] The first type of dummy column DPL1 can be formed as shown in the reference. Figures 2A to 2C The various structures described. (Refer to...) Figures 2A to 2C The first type of dummy pillar DPL1 described can overlap with the peripheral circuit structure PS in a vertically inverted structure. A portion of the dummy stack structure DST can extend between the first type of dummy pillar DPL1 and the first insulating layer IL1.

[0090] The channel structure CH and core insulating layer CO of the cell pillar CPL can extend further into the source layer SL than the memory layer ML. In one embodiment, the channel structure CH and core insulating layer CO can extend into the source layer SL. The end of the channel structure CH that extends into the source layer SL can contact the source layer SL.

[0091] Based on the above reference Figure 4 and Figure 5The described structure defines a string of memory cells electrically connected between the source layer SL and the bit line BL. The string of memory cells may include source select transistors, multiple memory cells, and drain select transistors connected in series via a channel structure CH. The source select transistors may be located at the intersection of the channel structure CH and the source select line SSL, the multiple memory cells may be located at the intersection of the channel structure CH and multiple word lines WL, and the drain select transistors may be located at the intersection of the channel structure CH and the drain select line DSL.

[0092] Below, a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure will be described. The process examples in the following manufacturing method can be used not only for manufacturing... Figure 1 and Figures 2A to 2C The semiconductor memory device shown can also be used to manufacture Figure 3 , Figure 4 and Figure 5 The semiconductor memory device shown.

[0093] Figure 6 This is a plan view of a substrate according to one embodiment of the present disclosure.

[0094] Reference Figure 6 The substrate 510 may include a dicing region SR and a plurality of chip regions CR separated by the dicing region SR. In one embodiment, the substrate 501 may be a reference. Figure 4 The substrate SUB is described. In another embodiment, substrate 501 may be a sacrificial substrate.

[0095] The structure of the memory cell array of a semiconductor memory device can be formed in each chip region CR.

[0096] Figure 7A and Figure 7B The diagram illustrates, for example, the process of forming a lower-layer structure and the process of forming multiple columns. Figure 7A Examples are shown in Figure 6 The structure formed on the diced region SR of the substrate 501 shown, and Figure 7B Examples are shown in Figure 6 The structure formed on the chip region CR of the substrate 501 shown.

[0097] Reference Figure 7A and Figure 7B , can Figure 6 A lower stacked structure 610A is formed on the substrate 501 shown. Although not shown in the figure, Figure 5 The peripheral circuit structure PS shown can be formed in Figure 6In each chip region CR of the substrate 501 shown, the structure for the source layer can be formed on the peripheral circuit structure PS, and then the lower stack-up structure 610A can be formed on the structure for the source layer. However, embodiments of this disclosure are not limited thereto. For example, the lower stack-up structure 610A can be formed on the protective layer. Figure 6 The protective layer is then formed on the substrate 510 shown, or it is formed directly on the substrate 510. Figure 6 On the substrate 501 shown.

[0098] The lower stacked structure 610A may include and Figure 6 The substrate 501 shown has a scribe region SR overlapping with the lower scribe region 610SR and the scribe region 610SR with the substrate 501. Figure 6 The substrate 501 shown has a lower chip region 610CR overlapping the chip region CR. The lower chip region 610CR may include a cell array region CAR and a connection region CNR extending from the cell array region CAR.

[0099] The lower stacked structure 610A may include a plurality of first material layers 111A and a plurality of first sacrificial layers 613A. Each of the plurality of first material layers 111A and the plurality of first sacrificial layers 613A may extend in a first direction D1 and a second direction D2. The plurality of first material layers 111A and the plurality of first sacrificial layers 613A may be alternately stacked in a third direction D3. The plurality of first material layers 111A may be formed by referring to... Figures 2A to 2C and Figure 3 The plurality of first dummy interlayer insulating layers 111A1 and the plurality of first interlayer insulating layers 111A2 described herein are formed of the same material. In one embodiment, the plurality of first material layers 111A may be formed of silicon oxide. The plurality of first sacrificial layers 613A may be formed of an insulating material having etch selectivity relative to the plurality of first material layers 111A. In one embodiment, the first sacrificial layer 613A may be formed of silicon nitride.

[0100] Subsequently, multiple first holes 621A, 621B, and 621C penetrate the lower stack-up structure 610A. The multiple first holes 621A, 621B, and 621C can be formed using the same mask process. The multiple first holes 621A, 621B, and 621C may include a lower hole 621A, a dummy hole 621B, and a lower channel hole 621C. The lower hole 621A can penetrate the lower scribing region 610SR of the lower stack-up structure 610A. The dummy hole 612B and the lower channel hole 612C can penetrate the lower chip region 160CR of the lower stack-up structure 610A. The dummy hole 621B can penetrate the connection region CNR of the lower chip region 610CR, and the lower channel hole 621C can penetrate the cell array region CAR of the lower chip region 610CR.

[0101] Subsequently, multiple pillars MP, SPL, and DPL1 can be formed in multiple first holes 621A, 621B, and 621C, respectively. The multiple pillars MP, SPL, and DPL1 can be formed using the same process. The multiple pillars MP, SPL, and DPL1 may include a measuring pillar MP in the lower hole 621A, a first-type dummy pillar DPL1 in the dummy hole 621A, and a sacrificial pillar SPL in the lower channel hole 621C. The first dummy pillar DPL1A of the first-type dummy pillar DPL1 can be disposed in the dummy hole 621B.

[0102] The measuring pillar MP, the first dummy pillar DPL1A, and the sacrificial pillar SPL can be formed from the same material layer. Therefore, the process of forming the plurality of pillars MP, SPL, and DPL1 can include forming a buried layer 121 at the bottom of each of the plurality of first holes 621A, 621B, and 621C, and forming a reflective metal layer (e.g., 125A) and an etch stop layer (e.g., 127A) at the top of each of the plurality of first holes 621A, 621B, and 621C. The reflective metal layer and the etch stop layer can overlap with the buried layer 121. Apertures 123 can be retained within the buried layer 121, but embodiments of this disclosure are not limited thereto.

[0103] The process of forming a reflective metal layer and an etch stop layer on top of each of the multiple first holes 621A, 621B and 621C can be performed in various ways.

[0104] In one implementation, each of the plurality of columns MP, SPL, and DPL1 can be configured to be... Figure 2A The first dummy pillar DPL1A shown has the same structure. The process of forming the reflective metal layer 125A and the etch stop layer 127A of each of the plurality of pillars MP, SPL and DPL1 may include the process of forming the reflective metal layer 125A on the buried layer 121 and the process of forming the etch stop layer 127A on the reflective metal layer 125A.

[0105] In another embodiment, each of the plurality of columns MP, SPL, and DPL1 can be configured to interact with... Figure 2B The structure is the same as the first dummy column DPL1B shown. Each of the plurality of columns MP, SPL, and DPL1 may include Figure 2B The etch stop layer 127B and reflective metal layer 125B are shown. Formation Figure 2B The process of the etch stop layer 127B and the reflective metal layer 125B shown may include forming along the etch stop layer 127B and the reflective metal layer 125B. Figure 7A and Figure 7BThe process shown includes the fabrication of an etch stop layer 127B extending from the surface of the buried layer 121 and the upper sidewall of each of the plurality of first holes 621A, 621B, and 621C, and the process of forming a reflective metal layer 125B on the etch stop layer 127B. The reflective metal layer 125B can be formed as a filler. Figure 7A and Figure 7B The upper central region of each of the plurality of first holes 621A, 621B and 621C shown.

[0106] In yet another embodiment, each of the plurality of columns MP, SPL, and DPL1 can be configured to interact with... Figure 2C The structure is the same as the first dummy column DPL1C shown. Each of the plurality of columns MP, SPL, and DPL1 may include Figure 2C The diagram shows the substrate pattern 127C1, the reflective metal layer 125C, and the core pattern 127C2. Formation Figure 2C The process of the shown substrate pattern 127C1, reflective metal layer 125C, and core pattern 127C2 may include forming along... Figure 7A and Figure 7B The process includes the following steps: the process of forming a backing pattern 127C1 extending from the surface of the buried layer 121 and the upper sidewall of each of the plurality of first holes 621A, 621B and 621C; the process of forming a reflective metal layer 125C along the surface of the backing pattern 127C1; and the process of forming a core pattern 127C2 on the reflective metal layer 125C. The core pattern 127C2 may be formed to fill the central region of the upper portion of each of the plurality of first holes 621A, 621B and 621C.

[0107] The material layers of the aforementioned columns MP, SPL, and DPL1 can be compared with the reference. Figures 2A to 2C The material layers of the first dummy pillars DPL1A, DPL1B, or DPL1C described are identical. For example, the buried layer 121 of each of the plurality of pillars MP, SPL, and DPL1 can be formed of a material with a hardness less than that of the reflective metal layer 125A and the etch stop layer 127A; the etch stop layer 127A of each of the plurality of pillars MP, SPL, and DPL1 can be formed of a material selected by taking into account the etch selectivity and ion scattering in the dry etching process described later; and the reflective metal layer 125A of each of the plurality of pillars MP, SPL, and DPL1 can be formed of a material with an atomic number greater than that of the etch stop layer 127A. For example, as shown in the reference... Figures 2A to 2C The buried layer 121 may be formed of a carbon-based material, the reflective metal layer 125A may be formed of tantalum, tungsten, etc. with an atomic number greater than 55, and the etch stop layer 127A may be formed of a titanium nitride layer.

[0108] As described above, multiple columns MP, SPL, and DPL1 with various structures are provided, so that the cross-sectional structure of the measuring column MP can be varied in some embodiments.

[0109] Figure 8A and Figure 8B This is a cross-sectional view illustrating, for example, the process of forming an upper-layered structure and the process of forming multiple holes. Figure 8A Examples of the same Figure 7A The lower layer structure 610A shown has an overlapping structure of lower subdivision regions 610SR, and... Figure 8B Examples of formation in Figure 7B The structure on the lower chip region 610CR of the lower stacked structure 610A shown.

[0110] Reference Figure 8A and Figure 8B The upper stacked structure 610B can be formed on the lower stacked structure 610A.

[0111] The upper stacked structure 610B may include a plurality of second material layers 111B and a plurality of second sacrificial layers 613B. The plurality of second material layers 111B may be formed of an insulating material, which is determined by a reference... Figures 2A to 2C and Figure 3 The described plurality of second dummy interlayer insulating layers 111B1 and 111B2 are formed. In one embodiment, the plurality of second material layers 111B may be formed of silicon oxide. The plurality of second sacrificial layers 613B may be formed of an insulating material having etch selectivity relative to the plurality of second material layers 111B. In one embodiment, the second sacrificial layer 613B may be formed of silicon nitride.

[0112] Each of the plurality of second material layers 111B and the plurality of second sacrificial layers 613B in the upper stacked structure 610B can extend in a first direction D1 and a second direction D2 to cover the measurement post MP, the first dummy post DPL1A, and the sacrificial post SPL. The plurality of second material layers 111B and the plurality of second sacrificial layers 613B can be alternately stacked in a third direction D3. The upper stacked structure 610B may include an upper etched region 610SR' overlapping with the lower etched region 610SR of the lower stacked structure 610A and an upper chip region 610CR' overlapping with the lower chip region 610CR of the lower stacked structure 610A.

[0113] Subsequently, a plurality of second holes 623A and 623C can be formed through the upper stacked structure 610B. The plurality of second holes 623A and 623C can be formed using the same mask process. The plurality of second holes 623A and 623C may include a top hole 623A and a top channel hole 623C. The top hole 623A may overlap with the measurement post MP. The top hole 623A may penetrate the upper scribe region 610SR' of the upper stacked structure 610B to expose the measurement post MP. The top channel hole 623C may overlap with the sacrificial post SPL. The top channel hole 623C may penetrate the upper die region 610CR' of the upper stacked structure 610B to expose the sacrificial post SPL.

[0114] The process for the aforementioned plurality of second holes 623A and 623C can be performed using a dry etching process. An etch stop layer 127A can be exposed during the dry etching process. The etch stop layer 127A can be formed of a titanium nitride layer or the like that can induce ion scattering. Therefore, during the dry etching process, the width of the lower portion of each of the plurality of second holes 623A and 623C can be extended due to ion scattering through the etch stop layer 127A exposed at the bottom of each of the plurality of second holes 623A and 623C. Because the etch stop layer 127A is formed of a titanium nitride layer or the like that that has etch selectivity relative to the upper stacked structure 610B, the etch stop layer 127A can be used to detect the endpoint of the aforementioned dry etching process.

[0115] The process variable compensation value can be calculated by measuring the overlap based on the center point estimated from the center point of the reflective metal layer (e.g., 125A) of the measurement column MP.

[0116] Figure 9 , Figure 10A , Figure 10B and Figure 10C This is a view illustrating the overlapping measurement method.

[0117] Figure 9 This is an example, for instance. Figure 7A The lower hole 621A shown and Figure 8A The plan view showing the overlap between the upper holes 623A.

[0118] Reference Figure 9 It can radiate electron beams to include Figure 8A and Figure 8BOn the sample with the structure shown, images of the lower hole 621A and the upper hole 623A can be obtained by detecting electrons radiated from the sample using high-voltage scanning electron microscopy (HV-SEM). The positions of the center point LC of the lower hole 621A and the center point UC of the upper hole 623A can be calculated based on the acquired images. The overlap between the lower hole 621A and the upper hole 623A can be measured based on the calculated positions of the center point LC of the lower hole 621A and the center point UC of the upper hole 623A.

[0119] Based on the overlap measured in the manner described above, it can be determined whether correction is required. Figure 7A and Figure 7B The process and reference shown Figure 8A and Figure 8B The process is described. When it is necessary to correct process variables, correction values ​​for the process variables can be calculated based on overlapping measurements. Subsequently, the reference values ​​can be corrected by reflecting the calculated correction values. Figure 7A , Figure 7B , Figure 8A and Figure 8B The described process.

[0120] It can be detected from Figure 8A The image of the lower aperture 621A is obtained by measuring the backscattered electrons emitted by the reflective metal layer (e.g., 125A) of the measurement column MP. This is because the selection will be based on ion scattering phenomena and etching selectivity during the dry etching process. Figure 8A The properties of the etch stop layer 127A shown may limit the efficiency of backscattered electron detection in one embodiment. To overcome this limitation and ensure efficient backscattered electron detection, in one embodiment... Figure 8A The reflective metal layer (e.g., 125A) of the measurement column MP shown can be formed of a material with an atomic number greater than that of the etch stop layer 127A. For example, Figure 8A The reflective metal layer (e.g., 125A) of the measurement column MP shown can be formed of a material with an atomic number greater than 55 (e.g., tantalum or tungsten).

[0121] Figure 10A , Figure 10B and Figure 10C This is a view illustrating a method for obtaining an image of a lower hole by using a reflective metal layer of a measuring column in various embodiments of this disclosure. Figure 10A Examples are given by forming Figure 2A The process of the first dummy column DPL1A shown provides a reflective metal layer 125A for the measurement column. Figure 10B Examples are given by forming Figure 2B The process of the first dummy column DPL1B shown provides a reflective metal layer 125B for the measurement column. Figure 10C Examples are given by forming Figure 2C The process of the first dummy column DPL1C shown provides a reflective metal layer 125C for the measurement column.

[0122] Reference Figure 10A The image measured through the reflective metal layer 125A in the lower aperture 621A can correspond to the cross-sectional shape of the lower aperture 621A. The reflective metal layer 125A can be... Figure 2A and Figure 8A The etch stop layer 127A is shown as a barrier. The accelerating voltage of the electron beam used for image measurement of the lower aperture 621A is controlled so that the electron beam can penetrate to the arrangement depth of the reflective metal layer 125A, thereby enabling the radiation of backscattered electrons from the reflective metal layer 125A. Therefore, in one embodiment, the center point of the lower aperture 621A can be estimated from the obtained image of the reflective metal layer 125A, and the overlap between the lower aperture 621A and the upper aperture 623A can be measured.

[0123] Reference Figure 10B The reflective metal layer 125B in the lower aperture 621A can have a structure surrounded by an etch stop layer 127B. The image measured through the reflective metal layer 125B can correspond to the shape of the central region of the lower aperture 621A. The center point of the lower aperture 621A can be estimated through the image of the reflective metal layer 125B, and the overlap between the lower aperture 621A and the upper aperture 623A can be measured.

[0124] Reference Figure 10C The reflective metal layer 125C in the lower aperture 621A can be disposed between the liner pattern 127C1 configured as an etch stop layer and the core pattern 127C2 configured as an etch stop layer, and the cross-sectional shape of the reflective metal layer 125C can have an annular structure. In one embodiment, the center point of the lower aperture 621A can be estimated by an image measured via the reflective metal layer 125C, and the overlap between the lower aperture 621A and the upper aperture 623A can be measured.

[0125] As described above, in one embodiment, the center point of the lower aperture 621 can be estimated using reflective metal layers 125A, 125B, and 125C having various structures. Furthermore, in one embodiment, the accuracy of the overlap measurement between the lower aperture 621A and the upper aperture 623A can be improved using reflective metal layers 125A, 125B, and 125C.

[0126] Figure 11A and Figure 11B This is a cross-sectional view illustrating, for example, the process of creating channel holes. Figure 11A Examples Figure 8AThe subsequent processes for the lower labeled region 610SR of the lower stacked structure 610A and the upper labeled region 610SR' of the upper stacked structure 610B are shown, and Figure 11B Examples Figure 8B The following are the subsequent processes for the lower chip region 610CR of the lower stacked structure 610A and the upper chip region 610CR' of the upper stacked structure 610B.

[0127] Reference Figure 11A and Figure 11B It can be removed through the upper channel hole 623C. Figure 8B The sacrificial column SPL is shown. Therefore, a channel hole 620C defined by connecting the upper channel hole 623C and the lower channel hole 621C to each other can be opened.

[0128] In removal Figure 8B When the sacrificial column SPL is shown, it can be removed through the upper hole 623A. Figure 8A The measuring column MP is shown. Therefore, a vertical hole 620A can be formed by connecting the upper hole 623A and the lower hole 621A to each other.

[0129] Figure 12A and Figure 12B This is a cross-sectional view illustrating, for example, the process of forming memory layers and cell pillars. Figure 12A Examples Figure 11A The subsequent processes for the vertical hole 620A shown, and Figure 12B Examples Figure 11B The subsequent process of the channel hole 620C shown.

[0130] Reference Figure 12A and Figure 12B A memory layer ML can be formed on the sidewall of the channel hole 620C. (See reference...) Figures 2A to 2C The memory layer ML may include a barrier insulating layer, a data storage layer, and a tunneling insulating layer. When forming the memory layer ML, a dummy memory layer DML may be formed on the sidewall of the vertical via 620A. The dummy memory layer DML may be formed from the same material layer as the memory layer ML.

[0131] Subsequently, a semiconductor layer for the channel structure CH can be formed on the memory layer ML. Then, a core insulating layer CO and a capping pattern CAP can be formed in the central region of the channel via 620C opened by the channel structure CH. Therefore, a cell pillar CPL comprising the channel structure CH, the core insulating layer CO, and the capping pattern CAP can be formed. The channel structure CH of the cell pillar CPL can be formed to be longer than the first type of dummy pillar DPL1 in the third direction D3. The capping pattern CAP can be formed from a doped semiconductor material including n-type doped silicon. Impurities in the capping pattern CAP can diffuse into the portion of the channel structure CH that contacts the capping pattern CAP.

[0132] When forming the channel structure CH, a dummy channel structure DCH can be formed on the dummy memory layer DML. When forming the core insulating layer CO and the capping pattern CAP, a dummy core insulating layer DCO and a dummy capping pattern DCAP can be formed in the central region of the vertical hole 620A opened by the dummy channel structure DCH.

[0133] Figure 13 This is a cross-sectional view illustrating, for example, a process for forming multiple conductive patterns. Figure 13 Examples Figure 12B The following are the subsequent processes for the lower chip region 610CR of the lower stacked structure 610A and the upper chip region 610CR' of the upper stacked structure 610B.

[0134] Reference Figure 1 and Figure 13 This can form a vertical insulating layer VI and multiple second-type dummy pillars DPL2, which penetrate through... Figure 12B The connection region CNR of each of the lower chip region 610CR of the lower stacked structure 610A and the upper chip region 610CR' of the upper stacked structure 610B shown. The vertical insulating layer VI and the plurality of second-type dummy pillars DPL2 can be formed of insulating material and extend on the third direction D3. Figure 12B The plurality of first material layers 111A shown can be separated by a vertical insulating layer VI into a plurality of dummy interlayer insulating layers 111A1 and a plurality of first interlayer insulating layers 111A2. Figure 12B The plurality of second material layers 111B shown can be separated by a vertical insulating layer VI into a plurality of second dummy interlayer insulating layers 111B1 and a plurality of second interlayer insulating layers 111B2. A plurality of first dummy interlayer insulating layers 111A1 and a plurality of sacrificial layers 613A alternately stacked on a third direction D3, and a plurality of second dummy interlayer insulating layers 111B1 and a plurality of second sacrificial layers 613B alternately stacked on a third direction D3, can define a dummy stack structure DST. The dummy stack structure DST can be surrounded by the vertical insulating layer VI.

[0135] Subsequently, a slit SI can be formed in the cell array region CAR, which penetrates... Figure 12B The lower chip region 610CR of the lower stacked structure 610A and the upper chip region 610CR' of the upper stacked structure 610B are shown. A slit SI may extend toward the vertical insulating layer VI and expose the end of the vertical insulating layer VI. The slit SI may be spaced apart from the dummy stacked structure DST, and the vertical insulating layer VI is inserted between the slit SI and the dummy stacked structure DST.

[0136] Subsequently, it can be removed via slit SI. Figure 12B Multiple first sacrificial layers 613A in the lower chip region 610CR shown and Figure 12B The diagram shows multiple second sacrificial layers 613B in the upper chip region 610CR'. In one embodiment, when multiple first sacrificial layers 613A and multiple second sacrificial layers 613B are removed through slit SI, the multiple first sacrificial layers 613A and multiple second sacrificial layers 613B of the dummy stack structure DST can be protected by the vertical insulating layer VI. In other words, in one embodiment, the vertical insulating layer VI can be used as an etch stop while removing multiple first sacrificial layers 613A and multiple second sacrificial layers 613B. In one embodiment, multiple first-type dummy pillars DPL1 retained in the dummy stack structure DST can assist the aforementioned etch stop. For example, when the vertical insulating layer VI does not completely penetrate the multiple first dummy interlayer insulating layers 111A1 and multiple first sacrificial layers 613A, the multiple first-type dummy pillars DPL1 can be used as etch stops to prevent etch material from being introduced from slit SI. Therefore, in one embodiment, the stability of the semiconductor memory device manufacturing process can be improved by using the first-type dummy pillars DPL1, and structural defects can be prevented or mitigated.

[0137] Subsequently, multiple first conductive patterns 113A can be formed in the regions where multiple first sacrificial layers 613A are etched, and multiple second conductive patterns 113B can be formed in the regions where multiple second sacrificial layers 613B are etched. Thus, a gate stack structure GST can be formed.

[0138] Subsequently, processes for forming the structure of the filling slit SI and the process for forming the conductive contact plug CT can be performed. After fabricating the memory cell array, Figure 6 and Figure 12A The dicing region SR shown can be isolated from the chip region CR through the dicing process.

[0139] Figure 14 This is a block diagram illustrating the configuration of a memory system according to one embodiment of the present invention.

[0140] Reference Figure 14 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0141] The memory device 1120 may include a gate stack structure, a dummy stack structure disposed at a height provided by the gate stack structure, a channel structure penetrating the gate stack structure, a memory layer located between the channel structure and the gate stack structure, and a dummy pillar penetrating a portion of the dummy stack structure in the length direction of the channel structure by a length less than the length of the channel structure.

[0142] Memory controller 1110 controls memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction block 1114, and memory interface 1115. SRAM 1111 serves as operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. Error correction block 1114 detects errors in data read from memory device 1120 and corrects the detected errors. Memory interface 1115 interfaces with memory device 1120. Memory controller 1110 may also include read-only memory (ROM) for storing code data for interfacing with the host.

[0143] The memory system 1100 configured as described above can be a memory card or solid-state drive (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1100 can communicate with an external (e.g., a host) via one of various interface protocols such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0144] Figure 15 This is a block diagram illustrating the configuration of a computing system according to one embodiment of the present disclosure.

[0145] Reference Figure 15 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0146] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

[0147] The memory device 1212 may include a gate stack structure, a dummy stack structure disposed at a height provided by the gate stack structure, a channel structure penetrating the gate stack structure, a memory layer located between the channel structure and the gate stack structure, and a dummy pillar penetrating a portion of the dummy stack structure in the length direction of the channel structure by a length less than the length of the channel structure.

[0148] The memory controller 1211 can be referenced above. Figure 14 The memory controller 1110 described is configured in the same way.

[0149] According to this disclosure, in one embodiment, the structural stability of the gate stack structure can be improved by using dummy pillars. According to this disclosure, in one embodiment, the stability of the manufacturing process can be improved by using measurement pillars comprising a buried layer, a reflective metal layer, and an etch stop layer.

[0150] In one embodiment of this disclosure, structural defects in semiconductor memory devices can be reduced by improving structural stability or manufacturing process stability as described above.

[0151] Cross-references to related applications

[0152] This application claims priority to Korean Patent Application No. 10-2021-0143985, filed on October 26, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked in a vertical direction; A dummy stack structure, comprising a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers alternately stacked in the vertical direction, wherein the dummy stack structure is disposed at the height of the gate stack structure; A channel structure that extends through the gate stack structure; A memory layer, wherein the memory layer is disposed between each of the plurality of conductive patterns and the channel structure; as well as A dummy column extends through a portion of the dummy layered structure, wherein the length of the dummy column in the vertical direction is less than the length of the channel structure.

2. The semiconductor memory device according to claim 1, wherein, The dummy stacked structure includes a first type of dummy stacked structure and a second type of dummy stacked structure stacked in the vertical direction, and In this configuration, the first type of dummy layered structure is penetrated by the dummy column, and The second type of dummy stacked structure extends to cover the dummy column.

3. The semiconductor memory device according to claim 2, wherein, The dummy column is disposed in a dummy hole that penetrates the first type of dummy stacked structure. The dummy hole includes a first portion adjacent to the interface between the first type of dummy stacked structure and the second type of dummy stacked structure, and a second portion extending from the first portion in a direction away from the interface. The dummy pillar includes a reflective metal layer and an etch stop layer disposed in the first portion of the dummy hole, and a buried layer disposed in the second portion of the dummy hole. Wherein, the hardness of the buried layer is less than the hardness of the reflective metal layer and the etch stop layer, and The reflective metal layer is formed of a material with an atomic number greater than that of the etch stop layer.

4. The semiconductor memory device according to claim 3, wherein, The buried layer is formed of carbon-based material.

5. The semiconductor memory device according to claim 3, wherein, The reflective metal layer is formed of a material with an atomic number greater than 55.

6. The semiconductor memory device according to claim 5, wherein, The reflective metal layer includes at least one of tantalum and tungsten.

7. The semiconductor memory device according to claim 6, wherein, The etch stop layer includes a titanium nitride layer.

8. The semiconductor memory device according to claim 3, wherein, The etch stop layer is positioned closer to the interface than the reflective metal layer, and The reflective metal layer is disposed between the buried layer and the etch stop layer.

9. The semiconductor memory device according to claim 3, wherein, The first portion of the dummy aperture includes a central region filled with the reflective metal layer, and The etch stop layer surrounds the sidewall of the reflective metal layer and extends between the reflective metal layer and the buried layer.

10. The semiconductor memory device according to claim 3, wherein, The etch stop layer constitutes each of the backing pattern and the core pattern. The lining pattern extends along the surface of the buried layer facing the vertical direction and the sidewall of the first portion of the dummy hole. The first portion of the dummy hole includes a central region filled with the core pattern, and The reflective metal layer is disposed between the liner pattern and the core pattern.

11. The semiconductor memory device of claim 1, further comprising: A conductive contact plug, the conductive contact plug being surrounded by the dummy layered structure; as well as A vertical insulating layer is disposed between the gate stack and the dummy stack, the vertical insulating layer extending to surround the sidewall of the dummy stack.

12. A method for manufacturing a semiconductor memory device, the method comprising the following steps: This forms a lower-layer stack-up structure that includes a lower-layer chip area and a lower-chip area; A lower hole is formed that penetrates the lower slit area of ​​the lower stacked structure; A measuring post is formed in the lower hole, the measuring post including a buried layer disposed at the lower part of the lower hole and a reflective metal layer and an etch stop layer disposed at the upper part of the lower hole; An upper stacked structure is formed on the lower stacked structure to cover the measuring column; as well as An upper hole is formed that overlaps with the measuring column, and the upper hole penetrates the upper stacked structure. Wherein, the hardness of the buried layer is less than the hardness of the reflective metal layer and the etch stop layer, and The reflective metal layer is formed of a material with an atomic number greater than that of the etch stop layer.

13. The method according to claim 12, further comprising the following step: After forming the upper hole that penetrates the upper stacked structure The overlap between the lower hole and the upper hole is measured based on the center point measured from the center point of the reflective metal layer of the measuring column.

14. The method according to claim 12, wherein, The lower chip region of the lower stacked structure includes a cell array region and a connection region extending from the cell array region. Specifically, during the formation of the lower hole, a lower channel hole is formed that penetrates the unit array region of the lower stacked structure, and a dummy hole is formed that penetrates the connection region of the lower stacked structure. Specifically, during the formation of the measuring column, a sacrificial column is formed in the lower channel hole, and a dummy column is formed in the dummy hole. Specifically, when forming the upper hole, an upper channel hole is formed that penetrates the upper stacked structure and overlaps with a portion of the sacrificial column.

15. The method according to claim 12, wherein, The buried layer is formed of carbon-based material.

16. The method according to claim 12, wherein, The reflective metal layer is formed of a material with an atomic number greater than 55.

17. The method according to claim 16, wherein, The reflective metal layer includes at least one of tantalum and tungsten.

18. The method according to claim 12, wherein, The etch stop layer includes a titanium nitride layer.

19. The method according to claim 12, wherein, The steps for forming the measurement column include the following: The buried layer is formed at the lower part of the lower hole; The reflective metal layer is formed on the buried layer; and The etch stop layer is formed on the reflective metal layer.

20. The method according to claim 12, wherein, The steps for forming the measurement column include the following: The buried layer is formed at the lower part of the lower hole; Forming an etch stop layer extending along the surface of the buried layer and the sidewall of the upper portion of the lower aperture; and The reflective metal layer is formed on the etch stop layer to fill the central region of the upper part of the lower hole.

21. The method according to claim 12, wherein, The steps for forming the measurement column include the following: The buried layer is formed at the lower part of the lower hole; A lining pattern is formed that extends along the surface of the buried layer and the sidewall of the upper part of the lower hole; The reflective metal layer is formed along the surface of the lining pattern; and A core pattern is formed on the reflective metal layer to fill the central region of the upper part of the lower aperture, and Each of the liner pattern and the core pattern is the etch stop layer.

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