A gate-all-around transistor device and a method for manufacturing the same

Abstract

The present invention provides a gate-all-around transistor device and a method for manufacturing the same. The device comprises: a substrate layer, an insulating layer, a top semiconductor layer, a first gate, a second gate, a source electrode, and a drain electrode. A groove is provided between the insulating layer and the top semiconductor layer, the first gate is provided within the groove, a pre-charge layer is provided on the first surface of the insulating layer where the first gate is not provided, and / or a pre-charge layer is provided on the surface of the semiconductor boss in contact with the insulating layer. By providing a pre-charge layer around the first gate between the top semiconductor layer and the insulating layer, the present invention enables the channel switching of the gate-all-around transistor to be primarily controlled by a gate-all-around, thereby fully leveraging the performance advantages of the gate-all-around transistor. Simultaneously, nanocrystals are formed by sequential ion implantation to further reduce the control of the π-type channel on the device. Furthermore, by cleaning the top semiconductor layer above the groove, the influence of the pre-charge layer on the channel threshold voltage of the gate-all-around is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a gate-all-around transistor device and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the critical dimensions of semiconductor devices, especially field-effect transistors (MOSFETs), have continued to shrink, even down to 10nm and below nodes. However, the short-channel effect of the devices has become increasingly significant, and traditional planar devices can no longer meet the performance and integration requirements of the devices.

[0003] As semiconductor device sizes continue to shrink, gate-all-around (GAA) silicon nanowire transistors, due to their shorter channel length, further reduce device size and exhibit superior performance. In existing device structures, when fabricating gate-all-around transistors, to ensure minimal overlap between the source and drain regions and the gate within the groove beneath the silicon nanowire, thereby reducing parasitic capacitance and mitigating the bias electric field on the gate dielectric, and due to the limited precision of photolithography alignment, the gate length at the top of the silicon nanowire is typically set to be longer than the gate length within the groove to avoid overlap between the gate and the source and drain within the groove.

[0004] However, the above solution will result in the appearance of GAA-type channels in which the gate completely wraps the channel, and π-type channels in which the gate in the groove does not wrap the channel. Since the π-type channel lacks the wrapping of the back gate in the groove, its turn-on speed is often slower than that of the GAA-type channel, resulting in a larger subthreshold slope and a smaller on-state current density, thereby limiting the GAA silicon nanowire transistor from exhibiting its ideal electrical performance.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are explained in the background technology part of this application. Summary of the Invention

[0006] In view of the above shortcomings of the prior art, the object of the present invention is to provide a ring-gate transistor device and a preparation method thereof, so as to solve the problems of large subthreshold slope and low on-state current density of the ring-gate transistor in the prior art.

[0007] To achieve the above object, the present invention provides a gate-all-around transistor device, the gate-all-around transistor device comprising: a substrate layer, an insulating layer, a top semiconductor layer, a first gate, a second gate, a source electrode, and a drain electrode;

[0008] The insulating layer is located above the substrate layer, and the top semiconductor layer is located above the insulating layer. A groove is provided between the insulating layer and the top semiconductor layer, and the groove does not penetrate the insulating layer. The top semiconductor layer includes a suspended channel and a semiconductor platform. The semiconductor platforms are located on both sides of the groove, and the semiconductor platform is connected to the suspended channel. The suspended channel spans the groove.

[0009] A first gate is disposed in the groove, and a second gate is disposed above and on the sidewall of the top semiconductor layer, wherein the length of the second gate is greater than that of the first gate;

[0010] A pre-charge layer is provided at a position on the first surface of the insulating layer where the first gate is not provided, and / or a pre-charge layer is provided on a surface of the semiconductor platform in contact with the insulating layer, wherein the pre-charge layer is used to adjust a threshold voltage of a corresponding channel;

[0011] The top semiconductor layer at both ends of the suspended channel is respectively provided with a source region and a drain region, the source electrode is provided above the source region, and the drain electrode is provided above the drain region.

[0012] Optionally, the groove is only located in the insulating layer; or the groove extends into the top semiconductor layer; or the groove extends into the substrate layer; or the groove extends into both the top semiconductor layer and the substrate layer.

[0013] The present invention also provides a method for preparing a gate-all-around transistor device, the method being used to prepare any one of the above-mentioned gate-all-around transistor devices, the method comprising:

[0014] Providing a supply substrate, the supply substrate comprising a top semiconductor layer; providing a second substrate, the second substrate comprising a base layer and an insulating layer, the insulating layer being located on the base layer, the surface of the insulating layer away from the base layer being a first surface, and the first surface being provided with a groove;

[0015] Doping the first surface of the insulating layer and / or surface doping the top semiconductor layer;

[0016] The supply substrate is bonded to the second substrate via the top semiconductor layer, and the top semiconductor layer is in contact with the first surface of the insulating layer;

[0017] The structure of the donor substrate except the top semiconductor layer is removed.

[0018] Optionally, the supply substrate further includes a first oxide layer and a first substrate, the first oxide layer is located on the first substrate, and the top semiconductor layer is located on the first oxide layer.

[0019] Optionally, the method for preparing the supply substrate includes: providing a third substrate, and implanting hydrogen ions into the third substrate to form a peeling interface in the third substrate, wherein the peeling interface separates the third substrate into a temporary substrate and the top semiconductor layer.

[0020] Optionally, hydrogen ions are first implanted into the third substrate to form the peeling interface, and then the top semiconductor layer is surface doped; or one surface of the third substrate is first doped, and then hydrogen ions are implanted into the surface to form the peeling interface in the third substrate.

[0021] Optionally, the top semiconductor layer is surface-doped with one or more of Si, Ge, C, P, As, B, O, N, F or Al, or / and the insulating layer is surface-doped with one or more of Si, Ge, C, P, As, B, O, N, F or Al.

[0022] Optionally, a method of doping the top semiconductor layer and / or the insulating layer includes low-energy ion implantation, surface plasma treatment, or annealing in a preset atmosphere.

[0023] Optionally, when doping the top semiconductor layer and / or the insulating layer, Si and / or Ge are doped first, an annealing process is performed, and then any one or any combination of more than one of B, P or As is doped, and an annealing process is performed again to form nanocrystals with preset doping elements.

[0024] Optionally, the preparation method further comprises: cleaning the top semiconductor layer above the groove to reduce the doping concentration of the top semiconductor layer above the groove.

[0025] As described above, the gate-all-around transistor device and the method for manufacturing the same of the present invention have the following beneficial effects:

[0026] The present invention arranges a pre-charge layer around the first gate between the top semiconductor layer and the insulating layer, so that the channel switch of the ring-gate transistor is mainly controlled by the full-surround gate, thereby giving full play to the performance advantages of the ring-gate transistor;

[0027] The present invention uses sequential ion implantation to form nanocrystals to further reduce the control of the π-type channel on the device;

[0028] The present invention cooperates with the cleaning of the top semiconductor layer above the groove to reduce the influence of the preset charge layer on the channel threshold voltage of the all-around gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It shows a schematic structural diagram of a gate-all-around transistor device in the prior art.

[0030] Figure 2 It shows a schematic structural diagram of a GAA type channel in the prior art.

[0031] Figure 3 It shows a schematic structural diagram of a π-type channel in the prior art.

[0032] Figure 4 Shown is a schematic structural diagram of a gate-all-around transistor device in Embodiment 1 of the present invention.

[0033] Figure 5 It shows a schematic structural diagram of the π-type channel in the first embodiment of the present invention.

[0034] Figure 6 It shows a schematic structural diagram of a GAA type channel in the first embodiment of the present invention.

[0035] Figure 7 It shows a schematic structural diagram of the process of providing a wafer substrate and its doping process in steps 1 and 2 in the first embodiment of the present invention.

[0036] Figure 8 It shows a structural schematic diagram of providing a second substrate and its doping process in steps 1 and 2 in the first embodiment of the present invention.

[0037] Figure 9 It is a schematic structural diagram showing the bonding between the top semiconductor layer and the second substrate in step 3 of the first embodiment of the present invention.

[0038] Figure 10 It shows a schematic diagram of the structure presented by removing other structures in step 4 in embodiment 1 of the present invention.

[0039] Figure 11 It shows a schematic structural diagram of the preparation of the wafer substrate in S1 in the second embodiment of the present invention.

[0040] Figure 12 It shows a schematic structural diagram of providing a second substrate in S2 in the second embodiment of the present invention.

[0041] Figure 13 It shows a schematic structural diagram of the bonding between the top semiconductor layer and the second substrate in S3 in the second embodiment of the present invention.

[0042] Figure 14 It shows a schematic structural diagram of the removal of the temporary substrate in S4 in the second embodiment of the present invention.

[0043] Component number description

[0044] 10. Substrate layer; 20. Insulating layer; 21. Groove; 30. Top semiconductor layer; 31. Suspended channel; 32. Semiconductor boss; 33. Precharge layer; 331. Ion implantation beam; 41. First gate; 42. Second gate; 401. Gate dielectric layer; 43. Passivation layer; 51. Source; 52. Drain; 60. Supply substrate; 61. First oxide layer; 62. First substrate; 71. Lifting interface; 72. Temporary substrate; A1. GAA type channel; A2. π-type channel. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0047] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0048] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0049] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0050] Example 1:

[0051] In the prior art, Figure 1As shown, when preparing a gate-all-around transistor device, in order to ensure that the source 51, the drain 52 and the gate in the groove 21 below the suspended channel 31 do not overlap too much, so as to reduce parasitic capacitance and alleviate the bias electric field at the gate dielectric layer 401, and because of the limited accuracy of photolithography alignment, the gate length at the top of the suspended channel 31 is usually set to be greater than the gate length in the groove 21 to avoid overlapping areas between the gate in the groove 21 and the source 51 and the drain 52. However, such a structural setting will cause the channel region of the device to appear as follows Figure 2 The gate shown completely surrounds the GAA channel A1 and Figure 3 The gate shown does not completely wrap around the π-type channel A2. Figure 2 and Figure 3 for Figure 1 As shown in the local enlarged view, since the π-type channel A2 lacks the wrapping of the first gate 41 in the groove 21, the opening of the π-type channel A2 is often later than the opening of the GAA-type channel A1, resulting in a larger subthreshold slope of the entire device and a smaller on-state current density, which limits the GAA silicon nanowire transistor from exhibiting its ideal electrical performance.

[0052] like Figure 4 As shown, the present invention provides a gate-all-around transistor device, which includes: a substrate layer 10, an insulating layer 20, a top semiconductor layer 30, a first gate 41, a second gate 42, a source 51, and a drain 52;

[0053] The insulating layer 20 is located above the substrate layer 10, and the top semiconductor layer 30 is located above the insulating layer 20. A groove 21 is provided between the insulating layer 20 and the top semiconductor layer 30. The groove 21 does not penetrate the insulating layer 20. The top semiconductor layer 30 includes a suspended channel 31 and a semiconductor platform 32. The semiconductor platforms 32 are located on both sides of the groove 21. The semiconductor platforms 32 are connected to the suspended channel 31. The suspended channel 31 spans the groove 21.

[0054] A first gate 41 is disposed in the groove 21 , and a second gate 42 is disposed above and on the sidewall of the top semiconductor layer 30 . The length of the second gate 42 is greater than that of the first gate 41 .

[0055] A pre-charge layer 33 is provided on the first surface of the insulating layer 20 where the first gate 41 is not provided, and / or a pre-charge layer 33 is provided on the surface of the semiconductor platform 32 in contact with the insulating layer 20, wherein the pre-charge layer 33 is used to adjust the threshold voltage of the corresponding channel;

[0056] The top semiconductor layer 30 at both ends of the suspended channel 31 is provided with a source region and a drain region, respectively. The source electrode 51 is provided above the source region, and the drain electrode 52 is provided above the drain region.

[0057] Figure 5 and Figure 6 for Figure 4 The present invention forms a fixed form of defect charge by setting a preset charge layer 33 on the insulating layer 20, and forms a movable charge carrier by setting a preset charge layer 33 on the semiconductor platform 32. The two preset charge layers 33 are used in combination to ensure Figure 5 The π-type channel A2 on the upper and sidewalls of the pre-charge layer 33 is formed before Figure 6 The GAA type channel A1 shown is turned on, so that the GAA type channel A1 has a higher control ability over the device switch, thereby giving full play to the excellent performance of the all-around gate device, reducing the overall subthreshold slope of the device, and improving the on-state current density of the device.

[0058] Specifically, the exposed surface of the suspended channel 31 is surrounded by the gate, and the length of the gate above and on the sidewalls (not shown in the drawings) of the suspended channel 31 is greater than the length of the gate below the suspended channel 31. The sidewalls refer to the side surfaces of the suspended channel 31 exposed except the upper surface and the lower surface connected to the groove 21, on which the second gate 42 is arranged in the three-dimensional structure, so that there is no overlapping area between the source region, the drain region and the gate in the groove 21.

[0059] In one embodiment, the suspended channel 31 can be a variety of semiconductor nanostructures such as semiconductor nanowires and semiconductor nanosheets.

[0060] In one embodiment, the groove 21 is only located in the insulating layer 20; or the groove 21 extends into the top semiconductor layer 30; or the groove 21 extends into the substrate layer 10; or the groove 21 extends into both the top semiconductor layer 30 and the substrate layer 10.

[0061] In the present invention, when the groove 21 is only provided in the insulating layer 20 , the process complexity during the manufacturing process can be reduced.

[0062] Specifically, the surface of the suspended channel 31 wraps around the gate dielectric layer 401 , and the surface of the gate dielectric layer 401 wraps around the first gate 41 and the second gate 42 .

[0063] In one embodiment, a passivation layer 43 is disposed between the second gate 42 and the source 51 and the drain 52 .

[0064] The present invention also provides a method for preparing a gate-all-around transistor device, the method being used to prepare any one of the above-mentioned gate-all-around transistor devices, the method comprising:

[0065] Step 1: providing a substrate 60, wherein the substrate 60 includes a top semiconductor layer 30; providing a second substrate, wherein the second substrate includes a substrate layer 10 and an insulating layer 20, wherein the insulating layer 20 is located on the substrate layer 10, and the surface of the insulating layer 20 away from the substrate layer 10 is a first surface, wherein a groove 21 is provided on the first surface;

[0066] Step 2: doping the first surface of the insulating layer 20 and / or doping the surface of the top semiconductor layer 30;

[0067] Step 3: The feed substrate 60 is bonded to the second substrate via the top semiconductor layer 30 , and the top semiconductor layer 30 is in contact with the first surface of the insulating layer 20 ;

[0068] Step 4: removing the structure of the supply substrate 60 except the top semiconductor layer 30 .

[0069] The preparation method of the ring-gate transistor device of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the ring-gate transistor device protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0070] First, if Figure 7 and Figure 8 As shown in the structure, step 1 is performed to provide a sheet substrate 60, wherein the sheet substrate 60 includes a top semiconductor layer 30; a second substrate is provided, wherein the second substrate includes a substrate layer 10 and an insulating layer 20, wherein the insulating layer 20 is located on the substrate layer 10, and the surface of the insulating layer 20 away from the substrate layer 10 is the first surface, and a groove 21 is provided on the first surface.

[0071] In one embodiment, the substrate 60 further includes a first oxide layer 61 and a first substrate 62 . The first oxide layer 61 is located on the first substrate 62 , and the top semiconductor layer 30 is located on the first oxide layer 61 .

[0072] Then, if Figure 7 and Figure 8 As shown in the process, step 2 is performed to dope the first surface of the insulating layer 20 and / or to dope the surface of the top semiconductor layer 30.

[0073] Specifically, the first surface of the insulating layer 20 and / or the surface of the top semiconductor layer 30 are doped in order to form a preset charge layer 33. Doping on either of the two surfaces can cause the π-type channel A2 above and on the sidewalls of the preset charge layer 33 formed by doping to open before the GAA-type channel A1. When both surfaces are doped to set the preset charge layer 33, it can be further ensured that the π-type channel A2 above and on the sidewalls of the preset charge layer 33 opens before the GAA-type channel A1.

[0074] In one embodiment, the insulating layer 20 is doped first, and then the groove 21 is provided on the first surface of the insulating layer 20; or the groove 21 is provided on the first surface of the insulating layer 20, and then the first surface of the insulating layer 20 is doped.

[0075] In one embodiment, the top semiconductor layer 30 is surface-doped with one or more of Si, Ge, C, P, As, B, O, N, F or Al, or / and the insulating layer 20 is surface-doped with one or more of Si, Ge, C, P, As, B, O, N, F or Al.

[0076] Specifically, the doping elements are mainly group IV elements, and may also be other elements that can change the doping state of the top semiconductor layer 30 or / and introduce fixed charges into the insulating layer 20 to achieve the effect of early opening of the π-type channel A2.

[0077] Specifically, when the ring-gate transistor device is an NMOS device, the doping of the top semiconductor layer 30 and / or the insulating layer 20 is N-type doping to form a negative preset charge layer 33; when the ring-gate transistor device is a PMOS device, the doping of the top semiconductor layer 30 and / or the insulating layer 20 is P-type doping to form a positive preset charge layer 33.

[0078] In one embodiment, ion implantation is performed on the top semiconductor layer 30 and / or the insulating layer 20 by an ion implantation beam 331 to achieve doping. Specifically, other suitable doping methods may also be used for doping.

[0079] In one embodiment, a method of doping the top semiconductor layer 30 and / or the insulating layer 20 includes low-energy ion implantation, surface plasma treatment, or annealing in a predetermined atmosphere.

[0080] In one embodiment, when doping the top semiconductor layer 30 and / or the insulating layer 20, Si and / or Ge are doped first, an annealing process is performed, and then any one or any combination of more than one of B, P or As is doped, and an annealing process is performed again to form nanocrystals of the preset doping elements.

[0081] The present invention forms nanocrystals with dangling bonds on their surfaces, thereby further enabling the π-type channel A2 to be opened in advance or kept in a normally open state, thereby reducing the control capability of the π-type channel A2 over the device switch and ensuring that the ring-gate transistor can fully exert its excellent performance.

[0082] Then, if Figure 9 As shown, step 3 is performed, the supply substrate 60 is bonded to the second substrate through the top semiconductor layer 30 , and the top semiconductor layer 30 is in contact with the first surface of the insulating layer 20 .

[0083] Finally, if Figure 10 As shown, step 4 is performed to remove the structure of the supply substrate 60 except the top semiconductor layer 30 .

[0084] Specifically, in this embodiment, the structure of the supply substrate 60 excluding the top semiconductor layer 30 includes the first oxide layer 61 and the first substrate 62 .

[0085] In one embodiment, the first substrate 62 is removed by polishing and / or etching, and the first oxide layer 61 is removed by etching.

[0086] In one embodiment, the preparation method further includes: cleaning the top semiconductor layer 30 above the groove 21 to reduce the doping concentration of the top semiconductor layer 30 above the groove 21 .

[0087] Since the entire surface of the top semiconductor layer 30 is doped before bonding, after removing other structures of the supply substrate 60, the present invention cleans the top semiconductor layer 30 above the groove 21 and oxidizes the doped ions therein, so that the GAA type channel A1 formed above the groove 21 will not be affected by the doping of the preset charge layer 33, thereby avoiding the threshold voltage of the device itself from significantly deviating from the preset value. At the same time, there is no need to consider the specific doping position and concentration during the initial doping, thereby reducing the process difficulty.

[0088] Example 2:

[0089] The present invention also provides another method for preparing a gate-all-around transistor device. The preparation method is similar to the preparation method in Example 1 in other features, except that the preparation method comprises the following steps:

[0090] S1: If Figure 11As shown, a supply substrate 60 is provided. The preparation method of the supply substrate 60 includes: providing a third substrate, implanting hydrogen ions into the third substrate to form a peeling interface 71 in the third substrate, wherein the peeling interface 71 separates the third substrate into a temporary substrate 72 and the top semiconductor layer 30, and performing surface doping on the top semiconductor layer 30;

[0091] S2: If Figure 12 As shown, a second substrate is provided, the second substrate comprising a substrate layer 10 and an insulating layer 20, the insulating layer 20 being located on the substrate layer 10, the surface of the insulating layer 20 away from the substrate layer 10 being a first surface, a groove 21 being provided on the first surface, and the first surface of the insulating layer 20 being doped;

[0092] S3: If Figure 13 As shown, the supply substrate 60 is bonded to the second substrate through the top semiconductor layer 30 , and the top semiconductor layer 30 is in contact with the first surface of the insulating layer 20 ;

[0093] S4: As Figure 14 As shown, the temporary substrate 72 of the supply substrate 60 is removed.

[0094] It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the all-around gate transistor device protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0095] The present invention obtains the easily peelable peeling interface 71 by directly injecting hydrogen ions into the third substrate, thereby reducing the preparation complexity of the supply substrate 60, thereby reducing costs and improving preparation efficiency.

[0096] In one embodiment, in S1, hydrogen ions are first implanted into the third substrate to form the peeling interface 71, and then the top semiconductor layer 30 is surface doped; or one surface of the third substrate is first doped, and then hydrogen ions are implanted into the surface to form the peeling interface 71 in the third substrate.

[0097] In summary, the ring-gate transistor device and its preparation method of the present invention can set a preset charge layer around the first gate between the top semiconductor layer and the insulating layer, so that the channel switch of the ring-gate transistor is mainly controlled by the full-surround gate, thereby giving full play to the performance advantages of the ring-gate transistor; at the same time, nanocrystals are formed by sequentially injecting ions to further reduce the control of the π-type channel on the device; in addition, in conjunction with the cleaning of the top semiconductor layer above the groove, the channel threshold voltage of the full-surround gate is reduced to be affected by the preset charge layer.

[0098] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A gate-all-around transistor device, characterized in that: The gate-all-around transistor device comprises: a substrate layer, an insulating layer, a top semiconductor layer, a first gate, a second gate, a source electrode, and a drain electrode; The insulating layer is located above the substrate layer, and the top semiconductor layer is located above the insulating layer. A groove is provided between the insulating layer and the top semiconductor layer, and the groove does not penetrate the insulating layer. The top semiconductor layer includes a suspended channel and a semiconductor platform. The semiconductor platforms are located on both sides of the groove, and the semiconductor platform is connected to the suspended channel. The suspended channel spans the groove. A first gate is disposed in the groove, and a second gate is disposed above and on the sidewall of the top semiconductor layer, wherein the length of the second gate is greater than that of the first gate; A pre-charge layer is provided at a position on the first surface of the insulating layer where the first gate is not provided, and / or a pre-charge layer is provided on a surface of the semiconductor platform in contact with the insulating layer, wherein the pre-charge layer is used to adjust a threshold voltage of a corresponding channel; The top semiconductor layer at both ends of the suspended channel is respectively provided with a source region and a drain region, the source electrode is provided above the source region, and the drain electrode is provided above the drain region.

2. The gate-all-around transistor device according to claim 1, wherein: The groove is located only in the insulating layer; or the groove extends into the top semiconductor layer; or the groove extends into the substrate layer; or the groove extends into both the top semiconductor layer and the substrate layer.

3. A method for preparing a gate-all-around transistor device, characterized in that: The preparation method is used to prepare the gate-all-around transistor device according to any one of claims 1 to 2, and the preparation method comprises: Providing a supply substrate, the supply substrate comprising a top semiconductor layer; providing a second substrate, the second substrate comprising a base layer and an insulating layer, the insulating layer being located on the base layer, the surface of the insulating layer away from the base layer being a first surface, and the first surface being provided with a groove; Doping the first surface of the insulating layer and / or surface doping the top semiconductor layer; The supply substrate is bonded to the second substrate via the top semiconductor layer, and the top semiconductor layer is in contact with the first surface of the insulating layer; The structure of the donor substrate except the top semiconductor layer is removed.

4. The method for preparing a gate-all-around transistor device according to claim 3, wherein: The supply substrate further includes a first oxide layer and a first substrate, wherein the first oxide layer is located on the first substrate, and the top semiconductor layer is located on the first oxide layer.

5. The method for preparing a gate-all-around transistor device according to claim 3, wherein: The method for preparing the supply substrate includes providing a third substrate, and implanting hydrogen ions into the third substrate to form a peeling interface in the third substrate, wherein the peeling interface separates the third substrate into a temporary substrate and the top semiconductor layer.

6. The method for preparing a gate-all-around transistor device according to claim 5, wherein: The third substrate is first implanted with hydrogen ions to form the peeling interface, and then the top semiconductor layer is surface doped; or one surface of the third substrate is first doped, and then hydrogen ions are implanted into the surface to form the peeling interface in the third substrate.

7. The method for preparing a gate-all-around transistor device according to claim 3, wherein: The top semiconductor layer is surface-doped with one or more of Si, Ge, C, P, As, B, O, N, F or Al, or / and the insulating layer is surface-doped with one or more of Si, Ge, C, P, As, B, O, N, F or Al.

8. The method for preparing a gate-all-around transistor device according to claim 3, wherein: Methods of doping the top semiconductor layer and / or the insulating layer include low-energy ion implantation, surface plasma treatment, or annealing in a preset atmosphere.

9. The method for preparing a gate-all-around transistor device according to claim 3, wherein: When doping the top semiconductor layer and / or the insulating layer, Si and / or Ge are first doped, an annealing process is performed, and then any one or any combination of more than one of B, P or As is doped, and an annealing process is performed again to form nanocrystals containing the preset doping elements.

10. The method for preparing a gate-all-around transistor device according to claim 3, wherein: The preparation method further includes: cleaning the top semiconductor layer above the groove to reduce the doping concentration of the top semiconductor layer above the groove.

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