Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of low channel mobility of an IGZO thin film transistor, which affects the on-state capability. The semiconductor structure provided by the application is characterized in that a channel stack structure is arranged to include a first oxide semiconductor layer, a second oxide semiconductor layer arranged in a stack, and a gate structure embedded between the first oxide semiconductor layer and the second oxide semiconductor layer. In this way, the interface area rich in oxygen vacancies can be increased, the oxygen vacancy concentration of the channel region is improved, and the carrier mobility of the channel region is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of semiconductor technology, indium gallium zinc oxide (IGZO) gradually becomes the channel material of thin film transistor, so the IGZO thin film transistor becomes a research hotspot. However, the channel carrier mobility of the current IGZO thin film transistor is low, which affects its on ability, so it is necessary to further improve the channel carrier mobility of the IGZO thin film transistor. SUMMARY

[0003] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a preparation method thereof, which can improve the channel carrier mobility of the IGZO thin film transistor.

[0004] The first aspect of the embodiments of the present application provides a semiconductor structure, comprising a substrate, a channel stack structure, a source, a drain and a gate structure; an active area of the substrate is provided with an insulating layer, the gate structure, the source and the drain are respectively embedded in the insulating layer, and the source and the drain are located on both sides of the gate structure; a barrier layer is arranged between the channel stack structure and the insulating layer; the channel stack structure comprises a first oxide semiconductor layer and a second oxide semiconductor layer which are stacked, the first oxide semiconductor layer and the second oxide semiconductor layer surround the gate structure, and an isolation structure is arranged between both sides of the gate structure and the channel stack structure; part of the channel stack structure is electrically connected with the source and the drain respectively, part of the channel stack structure is configured to form a channel region of the semiconductor structure, and the first oxide semiconductor layer and the second oxide semiconductor layer gather vacancy defects.

[0005] The semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0006] The semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0007] The IGZO semiconductor layer in the related art adopts a single-layer structure, which has a small contact area with the gate structure, resulting in a low oxygen vacancy concentration in the channel region, which affects the carrier mobility. However, in the embodiment of the present application, the channel stack structure includes a double-layer oxide semiconductor layer, and the gate structure is embedded between the double-layer oxide semiconductor layer, so as to increase the interface area rich in oxygen vacancies, thereby increasing the oxygen vacancy concentration in the channel region, and further improving the carrier mobility in the channel region.

[0008] The semiconductor structure as described above, the first oxide semiconductor layer and the second oxide semiconductor layer partially located in the channel region enclose a cavity, and the gate structure is located in the cavity; the isolation structure is arranged in the cavity and includes isolation blocks arranged on both sides of the gate structure, respectively.

[0009] The semiconductor structure as described above, the gate structure includes a first gate dielectric layer, a gate layer and a second gate dielectric layer arranged in sequence and in a stack; the first gate dielectric layer is attached to the first oxide semiconductor layer, and the second gate dielectric layer is attached to the second oxide semiconductor layer.

[0010] The semiconductor structure as described above, at least part of the channel stack structure is inserted into the source and the drain.

[0011] The semiconductor structure as described above, the first oxide semiconductor layer and the second oxide semiconductor layer partially located outside the channel region are attached and form a plug portion; the plug portion is inserted into the source and the drain and is electrically connected.

[0012] The second aspect of the embodiment of the present application provides a preparation method of a semiconductor structure, including the following steps:

[0013] A substrate is provided, and an active region of the substrate has an insulating layer;

[0014] A barrier layer is formed in the insulating layer;

[0015] A channel stack structure and a gate structure are formed in the active region, wherein the channel stack structure covers the barrier layer, the channel stack structure includes a first oxide semiconductor layer and a second oxide semiconductor layer arranged in a stack, the first oxide semiconductor layer and the second oxide semiconductor layer enclose the gate structure, and isolation structures are arranged between both sides of the gate structure and the channel stack structure;

[0016] A source and a drain are formed in the active region, and the source and the drain are located on both sides of the gate structure and are electrically connected to the channel stack structure, respectively.

[0017] The preparation method of the semiconductor structure as described above, the step of forming the barrier layer in the insulating layer includes:

[0018] vertically etching the insulating layer to form a first filling slot;

[0019] depositing a barrier material in the first filling slot to form a barrier layer, the barrier layer covering a bottom of the first filling slot.

[0020] It should be noted that the semiconductor structure preparation method provided by the embodiments of the present application has the same advantages as the semiconductor structure provided by the first aspect, which will not be repeated here.

[0021] The semiconductor structure preparation method as described above, the step of forming a channel stack structure and a gate structure in the active region comprises:

[0022] depositing an oxide in the first filling slot to form a first oxide semiconductor layer, and the first oxide semiconductor layer covers the barrier layer;

[0023] performing plasma treatment on the first oxide semiconductor layer to aggregate defect vacancies in the first oxide semiconductor layer;

[0024] depositing an isolation material in the first oxide semiconductor layer to form an isolation layer covering the first oxide semiconductor layer;

[0025] etching and removing part of the isolation layer, and retaining part of the isolation layer in the channel region to form a second filling slot and an isolation structure on both sides of the second filling slot;

[0026] forming a gate structure in the second filling slot;

[0027] depositing an oxide on the surface of the gate structure, the isolation structure, and the first oxide semiconductor layer to form a second oxide semiconductor layer, and the second oxide semiconductor layer covers the first oxide semiconductor layer outside the channel region;

[0028] performing plasma treatment on the second oxide semiconductor layer to aggregate defect vacancies in the second oxide semiconductor layer.

[0029] The semiconductor structure preparation method as described above, the step of forming a gate structure in the second filling slot comprises:

[0030] depositing a metal oxide in the second filling slot to form a first gate dielectric layer, and the first gate dielectric layer covers the bottom of the second filling slot;

[0031] depositing a conductive material on the first gate dielectric layer to form a gate layer covering the first gate dielectric layer;

[0032] depositing metal oxide on the gate layer to form a second gate dielectric layer, and the second gate dielectric layer is flush with the second sub-isolation layer.

[0033] The method for preparing a semiconductor structure as described above, the isolation layer comprises a first sub-isolation layer and a second sub-isolation layer, wherein the first sub-isolation layer covers the first oxide semiconductor layer;

[0034] After the first oxide semiconductor layer is subjected to plasma treatment, the method further comprises:

[0035] depositing an isolation material on the first oxide semiconductor layer to form a first sub-isolation layer covering the first oxide semiconductor layer;

[0036] etching and removing part of the first sub-isolation layer, and retaining part of the first sub-isolation layer in the channel region to form a second filling groove;

[0037] depositing metal oxide in the second filling groove to form a first gate dielectric layer, and the first gate dielectric layer covers the bottom of the second filling groove;

[0038] depositing a conductive material on the first gate dielectric layer to form a gate layer covering the first gate dielectric layer;

[0039] depositing an isolation material on the surface of the gate layer to form a second sub-isolation layer, and the second sub-isolation layer covers part of the first sub-isolation layer;

[0040] etching and removing the second sub-isolation layer outside the channel region, the first sub-isolation layer, and the second sub-isolation layer on the surface of the gate layer to form an isolation structure with the first sub-isolation layer on both sides of the gate structure and the second sub-isolation layer;

[0041] depositing metal oxide on the gate layer to form a second gate dielectric layer, and the second gate dielectric layer is flush with the second sub-isolation layer.

[0042] The method for preparing a semiconductor structure as described above, before the step of forming a channel stack structure and a gate structure in the active region, the method further comprises:

[0043] forming a first conductive block and a second conductive block in the first filling groove, the first conductive block and the second conductive block are located on the barrier layer, and the first conductive block and the second conductive block are covered by the channel stack structure.

[0044] The method for preparing a semiconductor structure as described above, in the step of depositing oxide in the first filling groove to form a first oxide semiconductor layer, the first oxide semiconductor layer covers the first conductive block and the second conductive block. BRIEF DESCRIPTION OF DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the semiconductor structure provided in Embodiment 1 of this application;

[0047] Figure 2 A schematic flowchart illustrating the method for fabricating the semiconductor structure provided in Embodiment 1 of this application;

[0048] Figure 3 for Figure 2 A detailed flowchart of step S300 is shown below;

[0049] Figure 4 for Figure 3 A detailed flowchart of step S350 is shown below;

[0050] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step of the preparation method provided in Embodiment 1 of this application;

[0051] Figure 15 This is a schematic diagram of the semiconductor structure provided in Embodiment 2 of this application;

[0052] Figure 16 This is a schematic flowchart of the method for fabricating the semiconductor structure provided in Embodiment 2 of this application;

[0053] Figure 17 for Figure 16 A detailed flowchart of step S300' is shown below;

[0054] Figures 18 to 26 This is a schematic diagram of the structure corresponding to each step of the preparation method provided in Embodiment 2 of this application;

[0055] Figure 27 This is a schematic flowchart of the method for fabricating the semiconductor structure provided in Embodiment 3 of this application;

[0056] Figure 28 for Figure 27 A detailed flowchart of step S300;

[0057] Figures 29 to 37 This is a schematic diagram of the structure corresponding to each step of the preparation method provided in Embodiment 3 of this application.

[0058] Explanation of reference numerals in the attached figures:

[0059] 10-Substrate; 20-Insulating layer; 21-First filling trench; 30-Barrier layer; 40-Channel stack structure; 41-First oxide semiconductor layer; 42-Second oxide semiconductor layer; 50-Isolation structure; 51-Isolation layer; 511-First sub-isolation layer; 512-Second sub-isolation layer; 52-Second filling trench; 60-Gate structure; 61-First gate dielectric layer; 62-Gate layer; 63-Second gate dielectric layer; 70-Source; 80-Drain; 90-Conductive layer; 91-First conductive block; 92-Second conductive block. Detailed Implementation

[0060] As described in the background section, current IGZO thin-film transistors suffer from low channel carrier mobility, affecting their conduction capability. The inventors discovered that this problem arises because existing IGZO semiconductor layers employ a single-layer structure, resulting in a small contact area with the gate structure. This leads to a low oxygen vacancy concentration in the channel region, thus impacting carrier mobility.

[0061] To address the aforementioned technical problems, this application provides a novel semiconductor structure, wherein the channel stack structure includes a first oxide semiconductor layer and a second oxide semiconductor layer stacked together, and a gate structure is embedded between the first oxide semiconductor layer and the second oxide semiconductor layer to increase the interface area rich in oxygen vacancies, thereby increasing the oxygen vacancy concentration in the channel region and thus improving the carrier mobility in the channel region.

[0062] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0063] Example 1

[0064] To facilitate the description of the embodiments of this application, we will first discuss... Figure 1 The coordinate system shown is used for illustration. The X-axis corresponds to the first direction, which can be parallel to the substrate, such as the left or right direction shown in the figure. The Y-axis corresponds to the second direction, which can be perpendicular to the substrate, such as the vertical or thickness direction shown in the figure.

[0065] like Figure 1As shown, the semiconductor structure provided by the embodiments of the present application includes a substrate 10, a source electrode 70, a drain electrode 80 and a gate structure 60. The substrate 10 is generally a semiconductor substrate, which includes a silicon substrate, a germanium substrate, etc. For example, the substrate 10 in the embodiments of the present application is a silicon substrate, which can be an N-type doped silicon substrate or a P-type doped silicon substrate. Of course, the silicon substrate can also be an undoped silicon substrate, which is not limited in the embodiments of the present application.

[0066] The substrate 10 is provided with an isolation trench to divide the substrate 10 into a plurality of active regions, which can be arranged in an array. An insulating layer 20 is arranged in each active region, which can be a silicon oxide layer with a certain thickness formed on the surface of the substrate 10.

[0067] The gate structure 60, the source electrode 70 and the drain electrode 80 are respectively embedded in the insulating layer 20. Along a first direction, the gate structure 60 is arranged at the middle position of the insulating layer 20, and the source electrode 70 and the drain electrode 80 are respectively arranged on the two sides of the gate structure 60. Along a second direction, part of the gate structure 60, the source electrode 70 and the drain electrode 80 are exposed to the surface of the insulating layer 20 to form an electrical connection position on the gate structure 60, the source electrode 70 and the drain electrode 80. For example, the source electrode 70 and the drain electrode 80 are respectively configured as a conductive block embedded in the insulating layer 20, which can be made of metal tungsten.

[0068] Further, the embodiments of the present application further provide a channel stack structure 40 between the source electrode 70 and the drain electrode 80, part of the channel stack structure 40 is respectively electrically connected with the source electrode 70 and the drain electrode 80, and part of the channel stack structure 40 is located below the gate structure 60 and forms a channel region of the semiconductor structure.

[0069] For example, the channel stack structure 40 includes a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42, wherein the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 are respectively IGZO semiconductor layers. Along the second direction, the second oxide semiconductor layer 42 is arranged above the gate structure 60, and the first oxide semiconductor layer 41 is arranged below the gate structure 60.

[0070] Along the first direction, the left and right sides of the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 are connected and surround a cavity, and the gate structure 60 is arranged in the cavity. The upper surface of the gate structure 60 is attached to the second oxide semiconductor layer 42, and the lower surface of the gate structure 60 is attached to the first oxide semiconductor layer 41. In this way, the contact surface area of the channel stack structure 40 and the gate structure 60 can be increased, so that after the subsequent plasma treatment of the first oxide semiconductor layer and the second oxide semiconductor layer, more vacancy defects can be gathered on the surface of the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42.

[0071] For example, in some embodiments, the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 can be injected or doped with hydrogen ions to "steal" oxygen atoms in the oxide, thereby accumulating oxygen vacancies at the interface between the oxide semiconductor layer and the gate structure 60, which can improve the carrier mobility of the channel region of the semiconductor.

[0072] To prevent oxygen atoms in the insulating layer 20 from entering the oxide semiconductor layer, preventing the oxygen atoms from combining with the oxygen vacancies, the embodiment of the present application provides a barrier layer 30 between the channel stack structure 40 and the insulating layer 20, the barrier layer 30 is located below the first oxide semiconductor layer 41 and can cover the first oxide semiconductor layer 41. For example, the barrier layer 30 can be a silicon nitride layer, which can prevent oxygen atoms in the insulating layer 20 located below the channel region from entering the oxide semiconductor layer in the channel region, thereby improving the carrier mobility of the channel region.

[0073] Further, the semiconductor structure provided by the embodiment of the present application further includes an isolation structure 50, the isolation structure 50 is arranged in the cavity surrounded by the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42, and along the first direction, the isolation structure 50 is arranged on both sides of the gate structure 60.

[0074] For example, the isolation structure 50 in the embodiment of the present application includes two isolation blocks, and along the first direction, the two isolation blocks are arranged on both sides of the gate structure 60. In this way, the isolation structure 50 is used to prevent oxygen atoms in the gate structure 60 from entering the channel stack structure 40, so as to accumulate more oxygen vacancies at the interface between the oxide semiconductor layer and the gate structure 60, thereby improving the carrier mobility of the channel region of the semiconductor.

[0075] In the related art, the IGZO semiconductor layer adopts a single-layer structure, which has a small contact area with the gate structure 60, resulting in a low oxygen vacancy concentration in the channel region, which affects the carrier mobility. However, in the embodiment of the present application, the channel stack structure 40 includes a double-layer oxide semiconductor layer, and the gate structure 60 is embedded between the double-layer oxide semiconductor layer, so as to increase the interface area rich in oxygen vacancies, thereby increasing the oxygen vacancy concentration in the channel region, and further improving the carrier mobility in the channel region.

[0076] On the basis of the above-mentioned embodiments, the gate structure 60 of the embodiment of the present application includes a first gate dielectric layer 61, a gate layer 62 and a second gate dielectric layer 63 which are sequentially and laminatedly arranged, wherein along the second direction, the first gate dielectric layer 61 is arranged above the first oxide semiconductor layer 41 and the first gate dielectric layer 61 is attached to the first oxide semiconductor layer 41, and the second gate dielectric layer 63 is arranged below the second oxide semiconductor layer 42 and the second gate dielectric layer 63 is attached to the second oxide semiconductor layer 42.

[0077] It can be understood that the first gate dielectric layer 61 and the second gate dielectric layer 63 can be oxide layers, including but not limited to silicon oxide layers or aluminum oxide layers; the gate electrode layer 62 is arranged between the first gate dielectric layer 61 and the second gate dielectric layer 63, and the gate electrode layer 62 is configured as a metal layer, including but not limited to a tungsten metal layer.

[0078] As shown in Figures 2 to 4 The embodiment of the present application also provides a preparation method of the semiconductor structure, and specifically includes the following steps:

[0079] Step S100: providing a substrate 10, and the active region of the substrate 10 has an insulating layer 20.

[0080] Specifically, the substrate 10 is provided, which includes a silicon substrate, a germanium substrate, etc. The insulating layer 20 is formed on the substrate 10. Further, a plurality of isolation trenches are formed on the substrate 10 to divide the substrate 10 into a plurality of active regions, and each active region has the insulating layer 20.

[0081] For example, an oxide is deposited on the substrate 10, which can be silicon oxide, and covers the insulating layer 20 on the surface of the substrate 10. The substrate 10 and the insulating layer 20 are vertically etched along the second direction to form the isolation trenches on the substrate 10 and form a plurality of active regions, and the surface of each active region has a certain thickness of the insulating layer 20, as shown in Figure 5 .

[0082] Step S200: forming a barrier layer 30 in the insulating layer 20.

[0083] Specifically, the insulating layer 20 is vertically etched along the second direction to form a first filling groove 21, as shown in Figure 6 Then, a barrier material is deposited in the first filling groove 21 to form the barrier layer 30, and the barrier layer 30 covers the bottom of the first filling groove 21, as shown in Figure 7 For example, silicon nitride is deposited in the first filling groove 21 to form the barrier layer 30, so that the subsequently formed channel stack structure 40 is isolated from the insulating layer 20.

[0084] Step S300: forming a channel stack structure 40 and a gate structure 60 in the active region, wherein the channel stack structure 40 covers the barrier layer 30, the channel stack structure 40 includes a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42 arranged in a stack, the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 surround the gate structure 60, and the two sides of the gate structure 60 and the channel stack structure 40 are provided with an isolation structure 50.

[0085] The step S300 in the embodiment of the present application comprises a step S310: depositing an oxide in the first filling groove 21 to form a first oxide semiconductor layer 41, and the first oxide semiconductor layer 41 covers the barrier layer 30, and the structure is as shown in Figure 8 .

[0086] Specifically, after forming the barrier layer 30 on the surface of the insulating layer 20, the oxide is deposited in the first filling groove 21 to form the first oxide semiconductor layer 41, and the first oxide semiconductor layer 41 covers the barrier layer 30, that is, the barrier layer 30 is between the insulating layer 20 and the first oxide semiconductor layer 41. For example, the indium gallium zinc oxide (IGZO) is deposited in the first filling groove 21, that is, the first oxide semiconductor layer 41 can be an IGZO semiconductor layer.

[0087] The step S320: performing plasma treatment on the first oxide semiconductor layer 41 to gather defect vacancies on the surface of the first oxide semiconductor layer 41, and the structure is as shown in Figure 9 .

[0088] Specifically, after forming the first oxide semiconductor layer 41 on the surface of the barrier layer 30, the plasma treatment needs to be performed on the first oxide semiconductor layer 41. For example, the hydrogen ion can be injected or doped into the first oxide semiconductor layer 41 to "steal" the oxygen atom in the indium gallium zinc oxide, so as to gather the defect vacancies on the surface of the first oxide semiconductor layer 41, that is, the oxygen vacancies are gathered at the interface between the first oxide semiconductor layer 41 and the gate structure 60, which can improve the carrier mobility of the channel region of the semiconductor.

[0089] The step S330: depositing an isolation material on the first oxide semiconductor layer 41 to form an isolation layer 51 covering the first oxide semiconductor layer 41, and the structure is as shown in Figure 10 .

[0090] Specifically, after the plasma treatment is performed on the first oxide semiconductor layer 41, in order to prevent the surrounding oxygen atoms from entering the first oxide semiconductor layer 41 and combining with the oxygen vacancies, the isolation material is deposited on the surface of the first oxide semiconductor layer 41 to form the isolation layer 51, and the isolation layer 51 covers the first oxide semiconductor layer 41. For example, the silicon nitride can be deposited on the surface of the first oxide semiconductor layer 41 to form the isolation layer 51, that is, the manufacturing materials of the above-mentioned barrier layer 30 and the isolation layer 51 can be the same.

[0091] The step S340: etching and removing part of the isolation layer 51, and retaining part of the isolation layer 51 located in the channel region to form a second filling groove 52 and an isolation structure 50 located on both sides of the second filling groove 52, and the structure is as shown in Figure 11 .

[0092] Specifically, after the isolation layer 51 is formed on the surface of the first oxide semiconductor layer 41, a vertical etching is performed on part of the isolation layer 51 to expose the first oxide semiconductor layer 41; meanwhile, part of the isolation layer 51 located in the channel region is reserved, and the second filling groove 52 is formed between the reserved isolation layers 51 in the channel region, which is used for forming the gate structure 60 later, and the reserved isolation layer 51 forms the isolation structure 50 on both sides of the gate structure 60.

[0093] For example, a vertical etching is performed on part of the isolation layer 51 located outside the channel region and part of the isolation layer 51 located in the middle of the channel region along the second direction, and the etched part exposes the first oxide semiconductor layer 41; meanwhile, part of the isolation layer 51 located on both sides of the channel region is reserved, and the two reserved isolation layers 51 form two isolation blocks respectively, and the second filling groove 52 is formed between the two isolation blocks.

[0094] Step S350: forming the gate structure 60 in the second filling groove 52, which is as shown in FIG. 5C. Figure 12

[0095] Specifically, after the isolation layer 51 is etched partially and the second filling groove 52 and the isolation structure 50 on both sides of the second filling groove 52 are formed in the channel region, the first gate dielectric layer 61, the gate layer 62 and the second gate dielectric layer 63 can be formed in the second filling groove 52 in sequence.

[0096] For example, the step S350 includes step S351: depositing a metal oxide in the second filling groove 52 to form the first gate dielectric layer 61, and the metal oxide includes but is not limited to aluminum oxide. The first gate dielectric layer 61 covers the bottom of the second filling groove 52 and adheres to the first oxide semiconductor layer 41 exposed in the second filling groove 52.

[0097] Step S352: depositing a conductive material on the surface of the first gate dielectric layer 61. For example, the conductive material includes but is not limited to tungsten, so as to form a tungsten layer on the surface of the first gate dielectric layer 61, which serves as the gate layer 62 and covers the entire first gate dielectric layer 61.

[0098] Step S353: depositing a metal oxide on the gate layer 62, and the metal oxide includes but is not limited to aluminum oxide, so as to form the second gate dielectric layer 63 covering the gate layer 62.

[0099] Further, it needs to be explained that the top surface of the gate structure 60 formed in the second filling groove 52 can be flush with the surface of the isolation structure 50, that is, the surface of the second gate dielectric layer away from the gate layer 62 is flush with the surface of the isolation layer 51 away from the first oxide semiconductor layer 41. In this way, the flatness of the second oxide semiconductor layer 42 formed later can be ensured.​

[0100] Step S360: depositing oxide on the surface of the gate structure 60, the isolation structure 50 and the first oxide semiconductor layer 41 to form a second oxide semiconductor layer 42, and the second oxide semiconductor layer 42 covers the first oxide semiconductor layer 41 outside the channel region, and the structure is as shown in FIG. 4C. Figure 13

[0101] Specifically, after the gate structure 60 is formed in the second filling groove 52, oxide can be deposited on the surface of the entire semiconductor structure to form the second oxide semiconductor layer 42, and the oxide can be indium gallium zinc oxide (IGZO), that is, the second oxide semiconductor layer 42 can be an IGZO semiconductor layer, and the second oxide semiconductor layer 42 covers the gate structure 60, the isolation structure 50 and the first oxide semiconductor layer 41 outside the channel region, and the second oxide semiconductor layer 42 can be attached to the second gate dielectric layer 63.

[0102] Step S370: performing plasma treatment on the second oxide semiconductor layer 42 to gather defect vacancies in the second oxide semiconductor layer 42. This step refers to step S320, which will not be described here; and the structure is as shown in FIG. 4D. Figure 14

[0103] Step S400: forming a source electrode 70 and a drain electrode 80 in the active region, and the source electrode 70 and the drain electrode 80 are located on both sides of the gate structure 60 and are electrically connected to the channel stack structure 40, and the structure is as shown in FIG. 4E. Figure 1

[0104] Specifically, after the plasma treatment is performed on the second oxide semiconductor layer 42, a first electrode and a second electrode are formed on the second oxide semiconductor layer 42, and the first electrode and the second electrode are arranged on both sides of the gate structure 60, wherein the first electrode is electrically connected to the second oxide semiconductor layer 42, and the first electrode is configured as the source electrode 70, and the second electrode is electrically connected to the second oxide semiconductor layer 42, and the second electrode is configured as the drain electrode 80.

[0105] For example, a conductive material is deposited on the surface of the second oxide semiconductor layer 42 to form the first electrode and the second electrode, and the conductive material includes but is not limited to tungsten metal, that is, a tungsten block is formed on the surface of the second oxide semiconductor layer as the first electrode and the second electrode.

[0106] The preparation method of the semiconductor provided by the embodiment of the present application combines the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 together to form the channel stack structure 40, and the gate structure 60 is embedded between the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42, and the two sides of the gate structure 60 are isolated from the channel stack structure 40 by the isolation structure 50, so as to increase the interface area rich in oxygen vacancies.​​​

[0107] Furthermore, in this embodiment, a barrier layer 30 is provided between the channel stack structure 40 and the insulating layer 20, and an isolation structure 50 is provided between the gate structure 60 and the channel stack structure 40. In order to prevent oxygen atoms around the channel stack structure 40 from entering the oxide semiconductor layer, further prevent oxygen atoms from combining with oxygen vacancies, further increase the oxygen vacancy concentration in the channel region, and thereby improve the carrier mobility in the channel region.

[0108] Example 2

[0109] like Figure 15 As shown, based on the first embodiment described above, in this embodiment, at least a portion of the channel stack structure 40 is inserted into the source 70 and the drain 80, so that the channel stack structure 40 is electrically connected to the source 70 and the drain 80, respectively. This arrangement increases the contact area between the channel stack structure 40 and the source 70 and the drain 80, and reduces the contact resistance between the channel stack structure 40 and the source 70 and the drain 80.

[0110] For example, the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42, partially located outside the channel region, are bonded together to form a plug portion, which is inserted into the source 70 and the drain 80. For instance, along the first direction, near the source 70 and the drain 80, the channel stack structure 40 is provided with a first plug portion and a second plug portion, respectively. The first plug portion is located on the side of the channel stack structure 40 near the source 70 and is inserted into the source 70. The second plug portion is located on the side of the channel stack structure 40 near the drain 80 and is inserted into the drain 80.

[0111] Accordingly, such as Figure 16 and Figure 17 As shown, the semiconductor structure fabrication method provided in this application embodiment has similarities to the semiconductor structure fabrication method provided in Embodiment 1. For example, step S100' is the same as step S100, and step S200' is the same as step S200. The similar parts will not be described again here. The difference is that after step S200' and before step S300', the following steps are also included:

[0112] Step S210': A first conductive block 91 and a second conductive block 92 are formed in the first filling groove 21. The first conductive block 91 and the second conductive block 92 are located on the barrier layer 30, and the first conductive block 91 and the second conductive block 92 are covered by the channel stack structure 40.

[0113] Specifically, after forming a barrier layer 30 in the first filling groove 21, a conductive material is deposited in the first filling groove 21 to form a conductive layer 90, and the conductive layer 90 covers the bottom of the first filling groove 21. This structure is as follows: Figure 18As shown.

[0114] Further, the conductive layer 90 is vertically etched to form the first conductive block 91 and the second conductive block 92 in the first filling groove 21, where the first conductive block 91 and the second conductive block 92 are located on both sides of the channel region, and the first conductive block 91 and the second conductive block 92 are arranged in cooperation with the source 70 or the drain 80 formed subsequently. In other words, the first conductive block 91 can be regarded as a part of the source 70, and the second conductive block 92 can be regarded as a part of the drain 80. The structure is as shown in Figure 19

[0115] On the basis of the above-mentioned embodiment, after step S210' is performed, the above-mentioned step S300' can be performed: forming the channel stack structure 40 and the gate structure 60 in the active region, where the channel stack structure 40 covers the barrier layer 30, and the channel stack structure 40 includes the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 arranged in a stack, the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 surround the gate structure 60, and the isolation structure 50 is arranged between both sides of the gate structure 60 and the channel stack structure 40.

[0116] Exemplarily, step S300' includes step S310': depositing an oxide in the first filling groove 21 to form the first oxide semiconductor layer 41, and the first oxide semiconductor layer 41 covers the barrier layer 30, the first conductive block 91 and the second conductive block 92. The structure formed in this step is as shown in Figure 20

[0117] For example, the first oxide semiconductor layer 41 formed in the above-mentioned step S310' covers the first conductive block 91 and the second conductive block 92, that is, the first oxide semiconductor layer 41 is formed on the upper surface of the first conductive block 91 and the second conductive block 92. Wherein the first oxide semiconductor layer can cover part of the surface of the conductive block, so that the source 70 formed subsequently is fitted with the top surface of the first conductive block 91, and the drain 80 is fitted with the top surface of the second conductive block 92.

[0118] Step S320': performing plasma treatment on the first oxide semiconductor layer 41 to gather defect vacancies on the surface of the first oxide semiconductor layer 41. This step can refer to step S320, and the structure formed in this step is as shown in Figure 21

[0119] Step S330': depositing an isolation material on the first oxide semiconductor layer 41 to form the isolation layer 51 covering the first oxide semiconductor layer 41. This step can refer to step S330, and the structure formed in this step is as shown in Figure 22

[0120] ​​​​Step S340': etching and removing part of the isolation layer 51, and retaining part of the isolation layer 51 in the channel region to form the second filling groove 52 and the isolation structure 50 on both sides of the second filling groove 52; this step can refer to step S340, and the formed structure is as shown in FIG. 4D. Figure 23

[0121] Step S350': forming the gate structure 60 in the second filling groove 52; this step can refer to step S350, and the formed structure is as shown in FIG. 4E. Figure 24

[0122] Step S360': depositing oxide on the surface of the gate structure 60, the isolation structure 50 and the first oxide semiconductor layer 41 to form the second oxide semiconductor layer 42, and the second oxide semiconductor layer 42 covers the first oxide semiconductor layer 41 outside the channel region; this step can refer to step S360, and the formed structure is as shown in FIG. 4F. Figure 25

[0123] Step S370': performing plasma treatment on the second oxide semiconductor layer 42 to gather defect vacancies in the second oxide semiconductor layer 42; this step can refer to step S370, and the formed structure is as shown in FIG. 4G. Figure 26

[0124] Step S400': forming the source 70 and the drain 80 in the active region, the source 70 and the drain 80 are located on both sides of the gate structure 60 and are electrically connected with the channel stack structure 40 respectively. This step can refer to step S400, and the formed structure is as shown in FIG. 4H. Figure 15

[0125] The semiconductor structure prepared by the semiconductor preparation method provided in the embodiments of the present application can make part of the channel stack structure 40 inserted into the source 70 and the drain 80 to form a plug part; the contact area of the channel stack structure 40 and the source 70 and the drain 80 can be increased, and the contact resistance of the channel stack structure 40 and the source 70 and the drain 80 can be reduced.

[0126] Embodiment Three

[0127] ​​​​​The semiconductor structure provided by the embodiment of the present application includes a first sub-isolation layer 511 and a second sub-isolation layer 512 in the isolation layer 51 of the isolation structure. In other words, the first sub-isolation layer 511 and the second sub-isolation layer 512 jointly form the isolation structure 50. Accordingly, the embodiment of the present application also provides a corresponding method for manufacturing the semiconductor structure, which has the same parts as the manufacturing methods in the above-mentioned embodiments one and two, and the same parts will not be described here. The difference is that after the step S320 or the step S320', the manufacturing process of the channel stack structure 40 embedded with the gate structure 60 is different according to the structure of the isolation layer 51.

[0128] It should be noted that the embodiment of the present application is based on the embodiment one and will be described in detail as follows.

[0129] As shown in Figure 27 and Figure 28 , the method for manufacturing the semiconductor structure provided by the embodiment of the present application includes the following steps.

[0130] Step S100'': providing a substrate 10, the active region of the substrate 10 has an insulating layer 20, this step is the same as the step S100, and will not be described here again. The structure formed is as shown in Figure 5 .

[0131] Step S200'': forming a barrier layer 30 in the insulating layer 20, this step is the same as the step S200, and will not be described here again. The structure formed is as shown in Figure 7 .

[0132] Step S300'': forming a channel stack structure 40 and a gate structure 60 in the active region, wherein the channel stack structure 40 covers the barrier layer 30, the channel stack structure 40 includes a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42 arranged in a stack, the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 surround the gate structure 60, and the isolation structure 50 is arranged between the two sides of the gate structure 60 and the channel stack structure 40.

[0133] Specifically, the step S300'' includes the step S310'': depositing an oxide in the first filling groove 21 to form the first oxide semiconductor layer 41, and the first oxide semiconductor layer 41 covers the barrier layer 30. This step is the same as the step S310, and will not be described here again. The structure formed is as shown in Figure 8 .

[0134] Step S320'': performing plasma treatment on the first oxide semiconductor layer 41 to gather defect vacancies on the surface of the first oxide semiconductor layer 41. This step is the same as the step S320, and the structure is as shown in Figure 9 .

[0135] Step S330": depositing an isolation material on the first oxide semiconductor layer 41 to form a first sub-isolation layer 511 covering the first oxide semiconductor layer 41, which can be referred to as step S330, and the structure formed is as shown in FIG. 3B. Figure 29

[0136] Step S340": etching and removing part of the first sub-isolation layer 511 and leaving part of the first sub-isolation layer 511 in the channel region to form a second filling groove 52, which can be referred to as step S340, and the structure formed is as shown in FIG. 3C. Figure 30

[0137] Step S351": depositing a metal oxide in the second filling groove 52 to form a first gate dielectric layer 61, and the first gate dielectric layer 61 covers the bottom of the second filling groove 52, which can be referred to as step S351, and the structure formed is as shown in FIG. 3D. Figure 31

[0138] Step S352": depositing a conductive material on the first gate dielectric layer 61 to form a gate electrode layer 62 covering the first gate dielectric layer 61, which can be referred to as step S352, and the structure formed is as shown in FIG. 3E. Figure 31

[0139] Step S353": depositing an isolation material on the surface of the gate electrode layer 62 to form a second sub-isolation layer 512, which covers part of the first sub-isolation layer 511, which can be referred to as step S330", and the structure formed is as shown in FIG. 3F. Figure 32

[0140] Step S354": etching and removing the second sub-isolation layer 512 outside the channel region, the first sub-isolation layer 511, and the second sub-isolation layer 512 on the surface of the gate electrode layer 62 to leave the first sub-isolation layer 511 and the second sub-isolation layer 512 on both sides of the gate structure 60 to form an isolation structure 50, which can be referred to as step S354, and the structure formed is as shown in FIG. 3G. Figure 33

[0141] Specifically, etching and removing part of the first sub-isolation layer 511 and the second sub-isolation layer 512 outside the channel region in the second direction to expose the first oxide semiconductor layer 41, and etching and removing the second sub-isolation layer 512 on the surface of the gate electrode layer 62 in the second direction to expose the gate electrode layer 62. Part of the first sub-isolation layer 511 and the second sub-isolation layer 512 on both sides of the channel region are left, and together form the isolation structure 50 on both sides of the gate structure 60.

[0142] ​​​​​​Step S355'': Metal oxide is deposited on the gate layer 62 to form a second gate dielectric layer 63, and the second gate dielectric layer 63 is flush with the second sub-isolation layer 512. This step can refer to step S353, and the structure formed is as shown in FIG. 4D. Figure 34 It should be noted that the surface of the second gate dielectric layer 63 away from the gate layer 62 is flush with the side surface of the second sub-isolation layer 512 away from the first sub-isolation layer 511.

[0143] Step S360'': Oxide is deposited on the surface of the gate structure 60, the isolation structure 50, and the first oxide semiconductor layer 41 to form a second oxide semiconductor layer 42, and the second oxide semiconductor layer 42 covers the first oxide semiconductor layer 41 outside the channel region. This step can refer to step S360, and details are not repeated here. The structure formed is as shown in FIG. 4E. Figure 35

[0144] Step S370'': The second oxide semiconductor layer 42 is subjected to plasma treatment to aggregate defect vacancies in the second oxide semiconductor layer 42. This step can refer to step S370, and details are not repeated here. The structure is as shown in FIG. 4F. Figure 36

[0145] Step S400'': Source 70 and drain 80 are formed in the active region, and the source 70 and the drain 80 are located on both sides of the gate structure 60 and are electrically connected to the channel stack structure 40, respectively. This step can refer to step S400, and details are not repeated here. The structure is as shown in FIG. 4G. Figure 37

[0146] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the description of the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0147] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the description of the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0148] ​​​Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that, This includes the substrate, channel stack structure, source, drain, and gate structure; An insulating layer is disposed in the active region of the substrate, and the gate structure, the source and the drain are respectively embedded in the insulating layer, with the source and the drain located on both sides of the gate structure; a barrier layer is disposed between the channel stack structure and the insulating layer; The channel stack structure includes a first oxide semiconductor layer and a second oxide semiconductor layer stacked together, the first oxide semiconductor layer and the second oxide semiconductor layer surrounding the gate structure, and isolation structures are provided between the two sides of the gate structure and the channel stack structure. A portion of the channel stack structure is electrically connected to the source and the drain, respectively. A portion of the channel stack structure is configured to form the channel region of the semiconductor structure, and vacancy defects are accumulated in the first oxide semiconductor layer and the second oxide semiconductor layer. A portion of the first oxide semiconductor layer and the second oxide semiconductor layer located in the channel region form a cavity, and the gate structure is located in the cavity.

2. The semiconductor structure according to claim 1, characterized in that, The isolation structure is disposed within the cavity and includes isolation blocks respectively disposed on both sides of the gate structure.

3. The semiconductor structure according to claim 2, characterized in that, The gate structure includes a first gate dielectric layer, a gate layer, and a second gate dielectric layer that are sequentially and stacked. The first gate dielectric layer is bonded to the first oxide semiconductor layer, and the second gate dielectric layer is bonded to the second oxide semiconductor layer.

4. The semiconductor structure according to claim 2, characterized in that, At least a portion of the channel stack structure is inserted into the source and the drain.

5. The semiconductor structure according to claim 4, characterized in that, The first oxide semiconductor layer and the second oxide semiconductor layer, which are partially located outside the channel region, are bonded together to form a plug portion; The plug is inserted into and electrically connected to the source and the drain.

6. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, wherein the active region of the substrate has an insulating layer; A barrier layer is formed within the insulating layer; A channel stack structure and a gate structure are formed in the active region, wherein the channel stack structure covers the barrier layer, the channel stack structure includes a first oxide semiconductor layer and a second oxide semiconductor layer stacked together, the first oxide semiconductor layer and the second oxide semiconductor layer surround the gate structure, and isolation structures are provided between the two sides of the gate structure and the channel stack structure, and vacancy defects are accumulated in the first oxide semiconductor layer and the second oxide semiconductor layer. A source and a drain are formed in the active region, the source and drain being located on opposite sides of the gate structure and electrically connected to the channel stack structure, respectively.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The step of forming a barrier layer within the insulating layer includes: The insulating layer is vertically etched to form a first filling groove; A barrier material is deposited in the first filling tank to form a barrier layer, the barrier layer covering the bottom of the first filling tank.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of forming the channel stack structure and the gate structure in the active region includes: An oxide is deposited in the first filling trench to form a first oxide semiconductor layer, and the first oxide semiconductor layer covers the barrier layer; The first oxide semiconductor layer is subjected to plasma treatment to accumulate defect vacancies within the first oxide semiconductor layer; An isolation material is deposited on the first oxide semiconductor layer to form an isolation layer covering the first oxide semiconductor layer; A portion of the isolation layer is etched away, while a portion of the isolation layer located in the channel region is retained to form a second filling groove and isolation structures located on both sides of the second filling groove; A gate structure is formed within the second filling groove; An oxide is deposited on the surface of the gate structure, the isolation structure and the first oxide semiconductor layer to form a second oxide semiconductor layer, and the second oxide semiconductor layer covers the first oxide semiconductor layer located outside the channel region; The second oxide semiconductor layer is subjected to plasma treatment to accumulate defect vacancies within the second oxide semiconductor layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The step of forming the gate structure in the second filling groove includes: A metal oxide is deposited in the second filling tank to form a first gate dielectric layer, and the first gate dielectric layer covers the bottom of the second filling tank; A conductive material is deposited in the first gate dielectric layer to form a gate layer covering the first gate dielectric layer; A metal oxide is deposited on the gate layer to form a second gate dielectric layer, and the second gate dielectric layer is flush with the isolation layer.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, The isolation layer includes a first sub-isolation layer and a second sub-isolation layer; After plasma treatment of the first oxide semiconductor layer, the process further includes: An isolation material is deposited on the first oxide semiconductor layer to form a first sub-isolation layer covering the first oxide semiconductor layer; A portion of the first sub-isolation layer is etched away, while a portion of the first sub-isolation layer located within the trench region is retained to form a second filling groove; A metal oxide is deposited in the second filling tank to form a first gate dielectric layer, and the first gate dielectric layer covers the bottom of the second filling tank; A conductive material is deposited in the first gate dielectric layer to form a gate layer covering the first gate dielectric layer; An isolation material is deposited on the surface of the gate layer to form a second sub-isolation layer, the second sub-isolation layer covering a portion of the first sub-isolation layer; The second sub-isolation layer, the first sub-isolation layer located outside the channel region, and the second sub-isolation layer located on the surface of the gate layer are etched away to form an isolation structure between the first sub-isolation layer and the second sub-isolation layer on both sides of the gate structure. A metal oxide is deposited on the gate layer to form a second gate dielectric layer, and the second gate dielectric layer is flush with the second sub-isolation layer.

11. The method for preparing a semiconductor structure according to claim 8, characterized in that, Prior to the step of forming the channel stack structure and the gate structure in the active region, the method further includes: A first conductive block and a second conductive block are formed in the first filling groove. The first conductive block and the second conductive block are located on the barrier layer, and the first conductive block and the second conductive block are covered by the channel stack structure.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, In the step of depositing oxide in the first filling trench to form a first oxide semiconductor layer, the first oxide semiconductor layer covers the first conductive block and the second conductive block.

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