A general purpose input output interface circuit and system on chip

Abstract

The application belongs to the technical field of integrated circuits and provides a general input and output interface circuit and a system on chip, which comprises a core voltage detection module and an IO voltage power-on detection module, and a first level shift module, a third level shift module and a first pre-driver module are connected in series between an internal control module and a PMOS tube module; a second level shift module and a second pre-driver module are connected in series between the internal control module and an NMOS tube module; a first bias end of a voltage bias module is connected to the IO voltage power-on detection module, the third level shift module, the first pre-driver module and the PMOS tube module; a second bias end is connected to the first level shift module, the core voltage detection module, the second level shift module, the second pre-driver module and the NMOS tube module, and the core voltage detection module is further connected to the first level shift module and the second level shift module. In the embodiment of the application, no burr is generated in PAD output, and the complexity of circuit design is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a general purpose input / output interface circuit and a system on chip. BACKGROUND

[0002] The general purpose input / output (GPIO) interface circuit is an indispensable module in the system on chip (SOC), and it is a "bridge" for communication between internal circuits and the outside world. The GPIO is a most basic general interface, and can be used for physical layer implementation of a wired communication protocol of a plurality of low-speed or medium-speed interfaces. However, in the power-on process, the positive and negative two input ends and the output end of the level shift circuit are symmetrical, and in the case that the two input ends are both 0, the power-on process randomly outputs a logic high or low, which causes a glitch on the output PAD. Some applications are particularly sensitive to the GPIO glitch, for example, the start control of the power supply system, the reset control of the chip, and the like, and the existence of the glitch may cause the entire chip system to fail to work normally. In order to avoid the influence of the glitch, the common solution is to filter out the glitch by using a large capacitor and a resistor, which not only increases the application cost of the chip, but also limits the function of the GPIO, and further increases the design complexity of the board.

[0003] With the increasingly advanced integrated circuit technology, the working voltage of the device is also increasingly low. For example, in the process below 28nm, the voltage across the device cannot exceed 1.8V, and in order to flexibly apply the system scheme, the GPIO needs to support a wide working power voltage range of 1.8V-3.3V. In the circuit design resistant to 3.3V, the signal transmitted from the internal logic circuit to the external PAD often needs to pass through two levels of level shift circuits, for example, the 0.8V internal signal is first converted into a 1.8V signal through the first level of level shift circuit, and then converted into a 3.3V signal through the second level of level shift circuit, but the use of more levels of level shift circuits further increases the probability of the glitch on the PAD. It can be seen that the existing input / output interface circuit has the problems of the glitch on the PAD and the large complexity. SUMMARY

[0004] The embodiment of the present application provides a general purpose input / output interface circuit, and aims to solve the problems of the existing general purpose input / output interface circuit, such as the glitch of the signal and the large complexity.

[0005] The embodiment of the present application is implemented in the following manner, that is, a general purpose input / output interface circuit is provided, which comprises an internal control module, a voltage biasing module connected to the internal control module, and further comprises:

[0006] The core voltage detection module, the IO voltage power-on detection module, the first level shift module, the second level shift module, the third level shift module, the first pre-driver module, the second pre-driver module, the PMOS tube module, the NMOS tube module, the external interface, and the general input module are connected in series between the internal control module and the PMOS tube module.

[0007] The first level shift module, the third level shift module, and the first pre-driver module are connected in series between the internal control module and the PMOS tube module.

[0008] The second level shift module and the second pre-driver module are connected in series between the internal control module and the NMOS tube module.

[0009] The first bias end of the voltage bias module is connected to the IO voltage power-on detection module, the third level shift module, the first pre-driver module, and the PMOS tube module.

[0010] The second bias end of the voltage bias module is connected to the first level shift module, the core voltage detection module, the second level shift module, the second pre-driver module, and the NMOS tube module, and the core voltage detection module is also connected to the first level shift module and the second level shift module.

[0011] The PMOS tube module and the NMOS tube module are connected in series between the IO power supply end and the ground end, the external interface is connected between the PMOS tube module and the NMOS tube module, and the general input module is connected between the external interface and the internal control module.

[0012] Further, a delay module is also included, which is connected in series between the second level shift module and the second pre-driver module, and is also connected to the second bias end of the voltage bias module.

[0013] Further, the PMOS tube module includes a first driving PMOS tube and a second driving PMOS tube connected in series, the drain of the first driving PMOS tube is connected to the source of the second driving PMOS tube, the first pre-driver module is connected to the gate of the first driving PMOS tube, and the first bias end of the voltage bias module is connected to the gate of the second driving PMOS tube.

[0014] Further, the NMOS tube module includes a first driving NMOS tube and a second driving NMOS tube connected in series, the drain of the first driving NMOS tube is connected to the source of the second driving NMOS tube, the second pre-driver module is connected to the gate of the first driving NMOS tube, and the second bias end of the voltage bias module is connected to the gate of the second driving NMOS tube.

[0015] Further, an electrostatic protection module is further included, one end of the electrostatic protection module is connected to the external interface, and the other end is connected between the drain of the second driving PMOS tube and the drain of the second driving NMOS tube.

[0016] Further, the core voltage detection module includes a third NMOS tube, a first resistor, a first inverter and a second inverter, wherein the output end of the first inverter is connected to the first input end of the second inverter, the first input end of the first inverter is connected to the drain of the third NMOS tube, the second input end of the first inverter, the second input end of the second inverter and the first resistor are connected to the second bias end of the voltage biasing module, the output end of the second inverter is connected to the first level shifting module and the second level shifting module, and the drain of the third NMOS tube is connected to the first resistor, the gate of the third NMOS tube is connected to a core power supply voltage, and the third input end of the first inverter, the third input end of the second inverter and the source of the third NMOS tube are grounded.

[0017] Further, the IO voltage power-on detection module includes a voltage dividing unit, a third PMOS tube, a capacitor and a third inverter, wherein the voltage dividing unit, the source of the third PMOS tube and the second input end of the third inverter are connected to one end of an IO power supply, one end of the capacitor and the first input end of the third inverter are connected to the drain of the third PMOS tube, the other end of the capacitor and the third input end of the third inverter are connected to the first bias end of the voltage biasing module, and the output end of the third inverter is connected to the third level shifting module to control a level signal output by the third level shifting module.

[0018] Further, the voltage dividing unit includes a second resistor and a third resistor, the gate of the third PMOS tube is connected between the second resistor and the third resistor, and the second resistor and the third resistor are connected in series between one end of the IO power supply and a ground end to divide voltage.

[0019] Further, when the IO power supply output voltage does not reach a threshold voltage, the voltage biasing module controls the voltage of the first bias end to be 0 and the voltage of the second bias end to be the IO power supply output voltage according to a control signal output by the internal control module.

[0020] When the IO power supply output voltage reaches the threshold voltage, the voltage biasing module controls the voltage of the first bias end to be the IO power supply output voltage minus the threshold voltage and the voltage of the second bias end to be the threshold voltage according to a control signal output by the internal control module.

[0021] The embodiment of the present application also provides a system on chip, which comprises internal circuits, external circuits and a general input and output interface circuit in any of the embodiments, and the internal circuits and the external circuits are connected in communication through the general input and output interface circuit.

[0022] The embodiment of the present application has the advantages that: the embodiment of the present application provides a core voltage detection module and an IO voltage power-on detection module in the circuit, and during the IO power-on process, the signal output by the first level shift module and the output signal of the third level shift module are pulled to a determined logic low respectively, and are pulled to a logic high after passing through the first pre-driver module with the function of inversion, so as to drive the PMOS tube module to be cut off, and the voltage signal corresponding to the waveform received at the external interface (PAD) will not generate a glitch; secondly, the present application is simple in power supply, wide in voltage range of the IO power supply, and resistant to high voltage, and the GPIO only needs one core power supply and one IO power supply, and realizes voltage conversion under the action of the first level shift module, the second level shift module and the third level shift module, and can realize 1.8V-3.3V working power supply voltage and application under 1.8V voltage-resistant devices. Therefore, the embodiment of the present application can avoid the generation of the glitch on the PAD in the general input and output interface circuit, and reduce the complexity of the circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a circuit schematic diagram of a general input and output interface circuit provided by the embodiment of the present application;

[0024] Figure 2-1 is a waveform diagram of the general input and output interface circuit provided by the embodiment of the present application;

[0025] Figure 2-2 is a waveform diagram of the general input and output interface circuit provided by the embodiment of the present application;

[0026] Figure 3 is a specific circuit schematic diagram of the core voltage detection module provided by the embodiment of the present application;

[0027] Figure 4 is a specific circuit schematic diagram of the IO voltage power-on detection module provided by the embodiment of the present application;

[0028] Wherein, 1, internal control module, 2, voltage bias module, 3, core voltage detection module, 31, third NMOS tube, 32, first resistance, 33, first inverter, 34, second inverter, 4, IO voltage power-on detection module, 41, second resistance, 42, third resistance, 43, third PMOS tube, 44, capacitor, 45, third inverter, 5, first level shift module, 6, second level shift module, 7, third level shift module, 8, first pre-driver module, 9, second pre-driver module, 10, PMOS tube module, 11, NMOS tube module, 12, external interface, 13, general input module, 14, delay module, 15, static protection module. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and not to limit the present application.

[0030] The prior art is prone to generate glitch on PAD during power-on of GPIO, and the glitch is filtered by large capacitor and resistance, which not only has high cost, but also limits the function of GPIO, and further increases the design complexity of the board. However, the present application provides the core voltage detection module and the IO voltage power-on detection module in the circuit, so that the voltage signal received by PAD during power-on of IO power supply does not generate glitch in the corresponding waveform. In addition, the present application has simple power supply, wide voltage range of IO power supply and high voltage resistance, and the GPIO only needs one core power supply and one IO power supply, and the voltage conversion is realized under the action of the first level shift module, the second level shift module and the third level shift module, so that the working power supply voltage of 1.8V-3.3V and application can be realized under 1.8V voltage resistant device. Therefore, the present application can avoid the generation of glitch on PAD in the general input / output interface circuit, and reduce the complexity of circuit design.

[0031] Example One

[0032] In combination Figure 1 As shown in the figure, it is a circuit schematic diagram of a general input / output interface circuit provided by the present embodiment. The general input / output interface circuit comprises an internal control module 1, a voltage bias module 2 connected to the internal control module 1, and further comprises a core voltage detection module 3, an IO voltage power-on detection module 4, a first level shift module 5, a second level shift module 6, a third level shift module 7, a first pre-driver module 8, a second pre-driver module 9, a PMOS tube module 10, an NMOS tube module 11, an external interface 12 and a general input module 13.

[0033] The first level shift module 5, the third level shift module 7 and the first pre-driver module 8 are connected in series between the internal control module 1 and the PMOS module 10.

[0034] The second level shift module 6 and the second pre-driver module 9 are connected in series between the internal control module 1 and the NMOS module 11.

[0035] The first bias end of the voltage bias module 2 is connected to the IO voltage power-on detection module 4, the third level shift module 7, the first pre-driver module 8 and the PMOS module 10 respectively.

[0036] The second bias end of the voltage bias module 2 is connected to the first level shift module 5, the core voltage detection module 3, the second level shift module 6, the second pre-driver module 9 and the NMOS module 11 respectively, and the core voltage detection module 3 is also connected to the first level shift module 5 and the second level shift module 6.

[0037] The PMOS module 10 and the NMOS module 11 are connected in series between the IO power supply end and the ground end, the external interface 12 is connected between the PMOS module 10 and the NMOS module 11, and the general input module 13 is connected between the external interface 12 and the internal control module 1.

[0038] Specifically, as shown in Figure 1 The internal control module 1 is connected to the voltage bias module 2 for controlling the output of the voltage bias module 2, and is also connected to the first level shift module 5 and the second level shift module 6 for controlling the level signal output, thereby controlling the output state of the external interface 12. In addition, the general input module (GPI) is connected to control the enablement of the GPI. When the IO power supply output voltage (VCCO) does not reach the threshold voltage 1.8V, the voltage bias module 2 controls the voltage of the first bias end (VBP) to be 0 and the voltage of the second bias end (VBN) to be VCCO according to the control signal output by the internal control module 1. When the voltage of VCCO reaches 1.8V, the voltage bias module 2 controls the voltage of VBN and VBP to be 1.8V and VCCO-1.8V respectively according to the control signal output by the internal control module 1.

[0039] The IO voltage power-on detection module 4 can be used to detect the voltage of the IO power supply VCCO. The IO voltage power-on detection module 4 is connected to the VBP end of the voltage bias module 2 and the third level shift module 7.

[0040] Specifically, when VCCO is greater than 1.8V (1.8V-3.3V), as shown inFigure 2-1 As shown, when the dp0 and dn0 of the internal control module 1 to the first level shift module 5 and the second level shift module 6 are logic low, and in the process of IO power VCCO power on (VCCO rises to 3.3V), the IO voltage power-on detection module 4 outputs the voltage VCCOC of the third level shift module 7 as logic high (3.3V), that is, the voltage VCCOC follows the voltage of its IO power, and the output node dp2 of the third level shift module 7 is pulled to a certain logic low, which is logic high at node dp3 after passing through the first pre-driver module 8 with inversion function, so that the PMOS tube module 10 is cut off, and the PAD does not produce glitches. When the IO power VCCO power on ends, the output voltage VCCOC becomes logic low (3.3V becomes 1.5V), that is, the voltage 1.5V output by the VBP of the voltage bias module 2.

[0041] Similarly, when VCCO is less than 1.8V, in combination with Figure 2-2 As shown, in the process of IO power VCCO power on (VCCO rises to 1.8V), VBP is 0, VBN rises from 0V to 1.8V (VCCO), the core power VDD is not powered on, VDDOC output is VBN (rises from 0V to 1.8V), the IO voltage power-on detection module 4 outputs the voltage VCCOC of the third level shift module 7 as logic high (1.8V), which pulls the output node dp2 of the third level shift module 7 to a certain logic low, which is logic high at node dp3 after passing through the first pre-driver module 8 with inversion function, so that the PMOS tube module 10 is cut off, and the PAD does not produce glitches. When the IO power VCCO power on ends, the voltage VCCOC becomes logic (0V).

[0042] The above-mentioned core voltage detection module 3 (VDD detect) is used for detecting the voltage of the core power VDD. In combination with Figure 1 As shown, the core voltage detection module 3 is connected to the voltage bias module 2, and when the core power VDD (the power supply of the internal control module 1) has power, the voltage VDDOC output to the first level shift module 5 and the second level shift module 6 is 0, and when the core power VDD has no power, the voltage VDDOC output is the voltage output by the VBN terminal.

[0043] The above-mentioned first level shift module 5 and second level shift module 6 are used for converting the internal core voltage signal of 0-0.8V in the internal control module 1 into a voltage signal of 0-1.8V. The third level shift module 7 is used for converting the 0-1.8V voltage signal converted by the first level shift module 5 into a voltage signal of (VCCO-1.8V)-VCCO, which is conducive to meeting the application scenario of resisting 3.3V high voltage.

[0044] The first pre-driver module 8 (Pre-drv-p) has the function of inverting, and is composed of multiple inverters. The second driver module (Pre-drv-n) is also composed of multiple inverters, but the signal of the second driver module is not inverted. Specifically, the first pre-driver module 8 is connected between the third level shift module 7 and the PMOS tube module 10. When the third level shift module 7 outputs a low-level signal, the first pre-driver module 8 inverts and outputs a high-level signal to the PMOS tube module 10 to drive the PMOS tube module 10 to be cut off. Conversely, a low-level signal is output to the PMOS tube module 10 to drive the PMOS tube module 10 to be turned on.

[0045] The general input module 13 is used for transmitting the signal of the external PAD to the internal control module 1.

[0046] In combination Figure 1 As shown in the figure, the PMOS tube module 10 includes a first driving PMOS tube (MP1) and a second driving PMOS tube (MP2) connected in series. The drain of the first driving PMOS tube is connected to the source of the second driving PMOS tube. The first pre-driver module 8 is connected to the gate of the first driving PMOS tube. The first bias end of the voltage bias module 2 is connected to the gate of the second driving PMOS tube. The NMOS tube module 11 includes a first driving NMOS tube (MN1) and a second driving NMOS tube (MN2) connected in series. The drain of the first driving NMOS tube is connected to the source of the second driving NMOS tube. The second pre-driver module 9 is connected to the gate of the first driving NMOS tube. The second bias end of the voltage bias module 2 is connected to the gate of the second driving NMOS tube. The gate of the second driving PMOS tube and the gate of the second driving NMOS tube are respectively connected to the VBP end and the VBN end of the voltage bias module 2, so that the 1.8V device can withstand a voltage of 3.3V.

[0047] The specific working principle of the embodiment of the application is as follows:

[0048] Reference Figure 1 As shown in the figure, after the core power supply VDD and the IO power supply VCCO are powered on, the output voltage VDDOC of the core voltage detection module 3 is 0, and the output voltage VCCOC of the IO voltage power-on detection module 4 is a logic low VBP. Therefore, the first level shift module 5, the second level shift module 6, and the third level shift module 7 can normally complete the level shifting of the signal and are not affected by the above two control signals.

[0049] If Figure 1 If the node dp0 is a logic low 0, then the node dp1 is a logic low 0V, the node dp2 is a logic low VBP, and the node dp3 is a logic high (IO power supply VCCO) after passing through the first pre-driver module 8 with inversion. The MP1 is cut off.

[0050] If the node dp0 is logic high 1, the node dp1 is logic high 1.8V, the node dp2 is logic high (IO power supply VCCO), and the node dp3 is logic low (the voltage at the VBP end) after passing through the first pre-drive module 8 with inversion, and the MP1 is turned on.

[0051] If the node dn0 is logic low 0, the node dn1 is logic low 0V, the second pre-drive module 9 does not invert, the nodes dn2 and dn3 are logic low 0V, and the MN1 is turned off.

[0052] If the node dn0 is logic high 1, the node dn1 is logic high 1.8V, the nodes dn2 and dn3 are logic high 1.8V, and the MN1 is turned on.

[0053] Therefore, according to the above circuit analysis, it is concluded that after the core power supply VDD and the IO power supply VCCO are powered on, if the nodes dp0 and dn0 are both logic low 0, the MP1 and the MN1 are turned off, and the PAD is in a high resistance state.

[0054] If the node dp0 is logic high 1 and the node dn0 is logic low 0, the MP1 is turned on, the MN1 is turned off, and the PAD output is logic high (IO power supply VCCO).

[0055] If the node dp0 is logic low 0 and the node dn0 is logic high 1, the MP1 is turned off, the MN1 is turned on, and the PAD output is logic low 0V.

[0056] In the embodiment of the present application, since the core voltage detection module 3 and the IO voltage power-on detection module 4 are provided in the circuit, during the IO power supply power-on process, the signal output by the first level shift module 5 and the output signal of the third level shift module 7 can be pulled to a determined logic low, and after passing through the first pre-drive module 8 with inversion function, it is pulled to logic high, so as to drive the MP1 to be turned off, and the voltage signal corresponding to the waveform received at the PAD will not generate a glitch. Secondly, the power supply is simple, the voltage range of the IO power supply is wide, and it is high-voltage resistant, and the GPIO only needs to be powered by one core power supply and one IO power supply, and the voltage conversion is realized under the action of the first level shift module 5, the second level shift module 6 and the third level shift module 7, so that the working power supply voltage and application of 1.8V-3.3V can be realized under the 1.8V voltage resistant device. Therefore, the embodiment of the present application can avoid the generation of the PAD glitch in the general input and output interface circuit, and at the same time, the complexity of the circuit design is reduced.

[0057] Example Two

[0058] With reference to Figure 1As shown, based on Embodiment 1, the general input / output interface circuit also includes a delay module. The delay module 14 is connected in series between the second level shift module 6 and the second pre-drive module 9, and is also connected to the second bias terminal of the voltage bias module 2.

[0059] Specifically, the delay module 14 can appropriately delay the output signal of the second level shift module 6 to match the delay of the third level shift module 7, which helps to keep the time when the output signal of the second level shift module 6 reaches MN1 after passing through the second pre-drive module 9 as consistent as possible with the time when the output signal of the third level shift module 7 reaches MP1.

[0060] As one possible embodiment, the general-purpose input / output interface circuit also includes an electrostatic discharge (ESD) protection module 15, combined with, for example... Figure 1 As shown, one end of the electrostatic discharge (ESD) protection module 15 is connected to the external interface 12, and the other end is connected between the drain of the second driving PMOS transistor and the drain of the second driving NMOS transistor. The ESD protection module 15 only provides ESD protection and does not affect signal transmission.

[0061] Example Three

[0062] In this embodiment, based on Embodiment 1, the core voltage detection module 3 includes a third NMOS transistor 31, a first resistor 32, a first inverter 33, and a second inverter 34. The output terminal of the first inverter 33 is connected to the first input terminal of the second inverter 34, and the first input terminal of the first inverter 33 is connected to the drain of the third NMOS transistor 31. The second input terminals of the first inverter 33, the second input terminals of the second inverter 34, and the first resistor 32 are connected to the second bias terminal of the voltage bias module 2. The output terminal of the second inverter 34 is connected to the first level shift module 5 and the second level shift module 6. The drain of the third NMOS transistor 31 is connected to the first resistor 32, and the gate of the third NMOS transistor 31 is connected to the core power supply voltage. The third input terminal of the first inverter 33, the third access terminal of the second inverter 34, and the source of the third NMOS transistor 31 are grounded.

[0063] Among them, reference Figure 3 As shown, Figure 3 This is a circuit diagram of the core voltage detection module provided in an embodiment of the present invention. M0 is the third NMOS transistor 31, R0 is the first resistor 32, INV1 is the first inverter 33, and INV2 is the second inverter 34.

[0064] Specifically, the kernel power VDD is connected to the gate of the third NMOS tube 31, when the kernel power VDD has electricity, M0 is turned on, and after two times of inversion through INV1 and INV2, VDDOC of 0V is output at the output end of INV2 to the first level shift module 5 and the second level shift module 6. When the kernel power VDD has no electricity, M0 is cut off, and the voltage at the output end of VBN of the voltage bias module 2 is input to INV1 and INV2, and VBN of the output voltage at the output end of INV2 is output to the first level shift module 5 and the second level shift module 6. The output voltage at the output end of VBN can be output according to the power-on state of the IO power supply.

[0065] In the embodiment of the application, by providing the kernel voltage detection module 3, the power-on state of the kernel voltage VDD can be detected, and corresponding voltages are output to the first level shift module 5 and the second level shift module 6 according to the power-on state, so that the first level shift module 5 and the second level shift module 6 output corresponding level signals to MP1 and MN1 in combination with the output voltage of the IO power supply, control the output of the PAD, and realize the PAD output without burr.

[0066] Example Four

[0067] In the embodiment, on the basis of the first embodiment, the IO voltage power-on detection module 4 includes a voltage dividing unit, a third PMOS tube 43, a capacitor 44, and a third inverter 45, wherein,

[0068] The voltage dividing unit, the source of the third PMOS tube 43, and the first input end of the third inverter 45 are respectively connected to one end of the IO power supply, one end of the capacitor 44, and the first input end of the third inverter 45. The other end of the capacitor 44 and the third input end of the third inverter 45 are connected to the first bias end of the voltage bias module 2. The output end of the third inverter 45 is connected to the third level shift module 7, and controls the level signal output by the third level shift module 7.

[0069] The voltage dividing unit includes a second resistor 41 and a third resistor 42. The gate of the third PMOS tube 43 is connected between the second resistor 41 and the third resistor 42. The second resistor 41 and the third resistor 42 are connected in series between one end of the IO power supply and the ground end to divide the voltage.

[0070] Reference Figure 4 As shown, Figure 4 The specific circuit schematic diagram of the IO voltage power-on detection module provided in the embodiment of the application is shown in the figure. R1 is the second resistor 41, R2 is the third resistor 42, M1 is the third PMOS tube 43, C1 is the capacitor 44, and INV3 is the third inverter 45.

[0071] Specifically, during the IO power supply VCCO power-on process, due to the presence of the capacitor 44 and the non-conduction of the PMOS tube, the voltage of the capacitor 44 is the output voltage of the VBP end, and the voltage of the VCCOC after being inverted by the INV3 is VCCO. After the VCCO power-on is completed, due to the weak conduction of the third PMOS tube 43, the voltage on the C1 slowly rises to VCCO, and the voltage of the VCCOC after being inverted by the INV3 is VBP. More specifically, Figure 4 In the embodiment, the resistors R1 and R2 constitute a voltage divider, and the third PMOS tube 43 gradually changes from off to weak conduction, so that the voltage on the C1 cannot quickly follow the power supply voltage, and as the IO power supply is powered on to a higher and higher voltage, the conduction of the third PMOS tube 43 is gradually strengthened, so that the voltage on the C1 can quickly reach the voltage of the IO power supply after the power-on is completed.

[0072] In this way, without using a super large resistor and the capacitor 44, a delay of more than a millisecond can be achieved, the IO voltage power-on detection module 4 can be applied to an application scenario with a millisecond-level power-on speed, the area of the chip is greatly saved and the cost is reduced, and the detection can be quickly completed in an application scenario with a faster power-on speed to save time, and the application is more flexible.

[0073] Example Five

[0074] The embodiment of the application further provides a system on chip, which comprises an internal circuit, an external circuit, and the universal input and output interface circuit in any of the above embodiments, and the internal circuit and the external circuit are in communication connection through the universal input and output interface circuit.

[0075] Specifically, the system on chip provided in the embodiment comprises the universal input and output interface circuit in the above embodiments, and the communication connection between the internal circuit and the external circuit is realized through the universal input and output interface circuit. The universal input and output interface circuit can realize the modes and achieve the technical effects of the above embodiments, which can also be realized in the system on chip provided in the embodiment, and will not be described herein.

[0076] In the embodiment of the present application, since the core voltage detection module 3 and the IO voltage power-on detection module 4 are provided in the circuit, during the IO power-on process, the signal output by the first level shifting module 5 and the output signal of the third level shifting module 7 can be pulled to a certain logic low respectively, and after passing through the first pre-driver module 8 with the inverting function, the logic high is pulled, so as to drive the MP1 to be cut off, and the voltage signal corresponding to the waveform received at the PAD cannot generate a glitch. Secondly, the power supply is simple, the voltage range of the IO power supply is wide, and it is high-voltage resistant, the GPIO only needs to be powered by one core power supply and one IO power supply, and can realize 1.8V~3.3V working power supply voltage and application under 1.8V high-voltage resistant device. Finally, the IO voltage power-on detection module 4 provided by the embodiment of the present application can realize a delay of more than milliseconds without using a super large resistor and capacitor, so as to ensure that the IO voltage power-on detection module 4 can be applied to the application scene of millisecond power-on speed, save the area of the chip, and quickly complete the detection in the application scene of fast power-on speed and save time, and the application is more flexible. Therefore, the embodiment of the present application can avoid the generation of the PAD glitch in the general input and output interface circuit, reduce the complexity of the circuit design, has wide application scenarios, and is low in cost.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the present application will be described with reference to the drawings in which is shown by way of illustration various embodiments of the application. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The use of the terms "including," "comprising," or "having" and variations thereof herein is intended to be broad and encompass the terms "consisting of" and "consisting essentially of," and variations thereof. The use of the terms "first," "second," and the like does not imply any particular order but is used for naming purposes only.

[0078] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. It is expressly understood that any of the embodiments described herein can be incorporated into any other embodiment.

[0079] The above only is the preferred embodiment of the present application, and does not limit the present application, any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A universal input / output interface circuit, comprising an internal control module and a voltage bias module connected to the internal control module, characterized in that, Also includes: The system includes a kernel voltage detection module, an I / O voltage power-on detection module, a first level shifting module, a second level shifting module, a third level shifting module, a first pre-drive module, a second pre-drive module, a PMOS transistor module, an NMOS transistor module, external interfaces, and a general-purpose input module. The first level shift module, the third level shift module, and the first pre-drive module are connected in series between the internal control module and the PMOS transistor module; The second level shifting module and the second pre-drive module are connected in series between the internal control module and the NMOS transistor module; The first bias terminal of the voltage bias module is connected to the IO voltage power-on detection module, the third level shift module, the first pre-drive module, and the PMOS transistor module, respectively. The second bias terminal of the voltage bias module is connected to the first level shift module, the core voltage detection module, the second level shift module, the second pre-drive module, and the NMOS transistor module, respectively, and the core voltage detection module is also connected to the first level shift module and the second level shift module. The PMOS transistor module and the NMOS transistor module are connected in series between one end of the IO power supply and the ground terminal. The external interface is connected between the PMOS transistor module and the NMOS transistor module, and the general-purpose input module is connected between the external interface and the internal control module.

2. The circuit as described in claim 1, characterized in that, It also includes a delay module, which is connected in series between the second level shift module and the second pre-drive module, and is also connected to the second bias terminal of the voltage bias module.

3. The circuit as described in claim 1, characterized in that, The PMOS transistor module includes a first driving PMOS transistor and a second driving PMOS transistor connected in series. The drain of the first driving PMOS transistor is connected to the source of the second driving PMOS transistor. The first pre-drive module is connected to the gate of the first driving PMOS transistor. The first bias terminal of the voltage bias module is connected to the gate of the second driving PMOS transistor.

4. The circuit as described in claim 3, characterized in that, The NMOS transistor module includes a first driving NMOS transistor and a second driving NMOS transistor connected in series. The drain of the first driving NMOS transistor is connected to the source of the second driving NMOS transistor. The second pre-driving module is connected to the gate of the first driving NMOS transistor. The second bias terminal of the voltage biasing module is connected to the gate of the second driving NMOS transistor.

5. The circuit as described in claim 4, characterized in that, It also includes an electrostatic discharge (ESD) protection module, one end of which is connected to the external interface, and the other end is connected between the drain of the second driving PMOS transistor and the drain of the second driving NMOS transistor.

6. The circuit as described in claim 1, characterized in that, The core voltage detection module includes a third NMOS transistor, a first resistor, a first inverter, and a second inverter, wherein... The output terminal of the first inverter is connected to the first input terminal of the second inverter. The first input terminal of the first inverter is connected to the drain of the third NMOS transistor. The second input terminal of the first inverter, the second input terminal of the second inverter, and the first resistor are connected to the second bias terminal of the voltage bias module. The output terminal of the second inverter is connected to the first level shift module and the second level shift module. The drain of the third NMOS transistor is connected to the first resistor. The gate of the third NMOS transistor is connected to the core power supply voltage. The third input terminal of the first inverter, the third access terminal of the second inverter, and the source of the third NMOS transistor are grounded.

7. The circuit as described in claim 1, characterized in that, The IO voltage power-on detection module includes a voltage divider unit, a third PMOS transistor, a capacitor, and a third inverter, wherein... The voltage divider unit, the source of the third PMOS transistor, and the second input terminal of the third inverter are respectively connected to one end of the IO power supply. One end of the capacitor and the first input terminal of the third inverter are connected to the drain of the third PMOS transistor. The other end of the capacitor and the third input terminal of the third inverter are connected to the first bias terminal of the voltage bias module. The output terminal of the third inverter is connected to the third level shift module to control the level signal output by the third level shift module.

8. The circuit as described in claim 7, characterized in that, The voltage divider unit includes a second resistor and a third resistor. The gate of the third PMOS transistor is connected between the second resistor and the third resistor. The second resistor and the third resistor are connected in series between one end of the IO power supply and the ground terminal to perform voltage division.

9. The circuit as described in claim 1, characterized in that, When the output voltage of the IO power supply does not reach the threshold voltage, the voltage biasing module controls the voltage of the first bias terminal to be 0 according to the control signal output by the internal control module, and the voltage of the second bias terminal is the output voltage of the IO power supply. When the output voltage of the IO power supply reaches the threshold voltage, the voltage biasing module controls the voltage of the first biasing terminal to be the IO power supply output voltage minus the threshold voltage, and the voltage of the second biasing terminal to be the threshold voltage, according to the control signal output by the internal control module.

10. A system-on-a-chip, characterized in that, It includes internal circuitry, external circuitry, and a universal input / output interface circuit as described in any one of claims 1-9, wherein the internal circuitry and the external circuitry are communicatively connected through the universal input / output interface circuitry.

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