A broadband high-speed multi-mode programmable frequency divider

Abstract

The present application relates to a kind of broadband high-speed multi-mode programmable frequency divider, including programmable frequency divider module, sigma-delta modulator module, adder module and algorithm control module;The programmable frequency divider module includes pre-frequency divider, P counter and swallow pulse S counter;The pre-frequency divider integrates the frequency division function of M / M+1 And 2M / 2M+1;The sigma-delta modulator is used to generate the random number of-3~4;The adder is used to add the random number with external digital input Int [n:0];The algorithm control module is used to control the working bit number of the swallow pulse S counter and based on the output L [n-1:0] Of the adder, processing satisfies the logic requirement of the programmable frequency divider module.The present application can widen the frequency range of frequency divider work, while reducing the complexity of circuit, power consumption and area.

Description

A broadband high-speed multi-mode programmable frequency divider Technical Field

[0001] This invention relates to a programmable frequency divider, and more particularly to a broadband high-speed multimode programmable frequency divider. Background Technology

[0002] Wireless communication systems and wired interface systems all require phase-locked loop (PLL)-based frequency synthesizers or clock generators to provide carrier / local oscillator or clock signals. High-performance frequency dividers are an essential and critical module in PLL systems. In modern communication systems, to comply with different protocol standards and regional requirements, PLLs are required to provide different output frequencies. This necessitates both a voltage-controlled oscillator (VCO) capable of generating a wide frequency range and a frequency divider capable of operating across a wide bandwidth with varying division ratios. To enhance the flexibility of the frequency divider, programmable frequency divider technology is often employed.

[0003] Currently, there are three main forms of programmable frequency divider technology: programmable frequency dividers based on phase switches, programmable frequency dividers based on pulse swallowing technology, and multi-mode frequency dividers based on 2 / 3 dividers. Traditional programmable frequency dividers have limited operating frequency ranges, mostly operating within a frequency bandwidth of several hundred megahertz. With the development of modern electronic information technology, especially in the application of millimeter-wave radar systems, which employ frequency-modulated continuous wave (FM) operation, the system bandwidth directly determines the ranging accuracy, velocity measurement accuracy, and other system performance of the millimeter-wave radar system. Therefore, frequency dividers are required to operate over a very large bandwidth, reaching several GHz. Existing 77GHz millimeter-wave radars have an operating bandwidth of approximately 4GHz. Existing technologies, when extending the frequency range, design two sets of frequency dividers with different operating frequencies and then switch them using a switch to adapt to different frequency range requirements. However, this approach is often constrained by power consumption and area, significantly increasing design and manufacturing costs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a broadband high-speed multi-mode programmable frequency divider that can broaden the operating frequency range while reducing the complexity, power consumption and area of ​​the circuit.

[0005] The technical solution adopted by this invention to solve its technical problem is as follows: A broadband high-speed multi-mode programmable frequency divider is provided, including a programmable frequency divider module, a sigma-delta modulator module, an adder module, and an algorithm control module. The programmable frequency divider module includes a prescaler, a P-counter, and a pulse-swallowing S-counter. The prescaler integrates M / M+1 and 2M / 2M+1 frequency division functions, ensuring that the output frequency remains the same after processing by the prescaler even when the input frequency increases exponentially, without increasing the operating frequency range of the P-counter and S-counter, thus reducing design difficulty. The sigma-delta modulator is used to generate random numbers from -3 to 4. The adder is used to add the random numbers to an external digital input Int[n:0]. The algorithm control module is used to control the number of bits of the pulse-swallowing S-counter and to process the output L[n-1:0] of the adder to meet the logic requirements of the programmable frequency divider module.

[0006] The P counter includes several D flip-flop units connected in sequence. The low-order D flip-flop units connected to the output of the prescaler are D flip-flop units based on the TSPC structure, and the high-order D flip-flop units connected to the output of the prescaler are static D flip-flop units based on logic gates.

[0007] M is a power of 2, the number of bits in the P counter is greater than or equal to M, the number of bits in the P counter minus one is greater than the number of bits in the pulse swallowing S counter, and the number of bits in the pulse swallowing S counter is log2M, with the most significant bit being log2M-1; the number of bits in the P counter is greater than or equal to log2M+1, with the least significant bit being log2M.

[0008] The algorithm control module includes: an input signal judgment unit, used to judge whether the frequency of the input signal exceeds a threshold; a first processing unit, used to control the prescaler to use a 2M / 2M+1 frequency division function when the frequency of the input signal exceeds the threshold, control the pulse swallowing S counter to operate with a first working bit number K, and send L[n-1:K] of the output L[n-1:0] of the adder as a first control word signal to the P counter, and send L[K-1:0] of the output L[n-1:0] of the adder as a second control word signal to the pulse swallowing S counter; a second processing unit, used to... When the frequency of the input signal does not exceed the threshold, the prescaler is controlled to use the M / M+1 frequency division function, the pulse swallowing S counter is controlled to operate with the second working bit R, the second working bit R is less than the first working bit K, and the third bit of the pulse swallowing S counter is set to zero. The L[R-1:0] of the adder's output L[n-1:0] is sent to the pulse swallowing S counter as the first control word signal, the L[n-2:R] of the adder's output L[n-1:0] is sent to the P counter as the second control word signal, and the L[n-1] of the adder's output L[n-1:0] is discarded.

[0009] After processing by the prescaler, if the input signal frequency has a twofold relationship, the output signal frequency of the prescaler will be the same. This will not increase the operating frequency range of the P counter and S counter, thus reducing the design difficulty.

[0010] Beneficial effects

[0011] Due to the adoption of the above technical solution, this invention has the following advantages and positive effects compared with the prior art: This invention proposes a broadband multi-mode programmable frequency divider to meet the application requirements of wide bandwidth and multiple division ratios. Through algorithmic control optimization, it ensures effective control of the PS counter by the binary code changes of the integrated multi-mode programmable broadband frequency divider with multiple prescalers. This achieves a frequency divider with both integer and fractional division, avoiding the need for two or more frequency dividers operating in different frequency ranges in traditional architectures. This reduces hardware manufacturing costs and circuit complexity, and optimizes power consumption. The configured programmable bit number can achieve a wide range of division ratios, meeting the needs of most application scenarios and greatly enhancing the application flexibility and versatility of the frequency divider. Attached Figure Description

[0012] Figure 1 is a schematic diagram of the structure of the broadband high-speed multimode programmable frequency divider in this embodiment;

[0013] Figure 2 is a schematic diagram of the programmable frequency divider module in this embodiment;

[0014] Figure 3 is a schematic diagram of the structure of the P counter in this embodiment;

[0015] Figure 4 is a flowchart of the algorithm control module in this embodiment. Detailed Implementation

[0016] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0017] The present invention relates to a broadband high-speed multi-mode programmable frequency divider, as shown in Figure 1, comprising a programmable frequency divider module, a sigma-delta modulator module, an adder module, and an algorithm control module. The programmable frequency divider module includes a prescaler, a P-counter, and a pulse-swallowing S-counter. The prescaler integrates M / M+1 and 2M / 2M+1 frequency division functions. The sigma-delta modulator is used to generate random numbers from -3 to 4. The adder is used to add the random numbers to an external digital input Int[n:0]. The algorithm control module is used to control the number of bits of the pulse-swallowing S-counter and to process the output L[n-1:0] of the adder to meet the logic requirements of the programmable frequency divider module.

[0018] In this embodiment, two sets of frequency division ratios with different moduli are integrated into a single prescaler, and the counter bit depth is configured using an algorithm control module, effectively reducing circuit complexity and saving area. Simultaneously, the algorithm control module optimizes the programmable frequency divider chain, reducing power consumption and cost. To ensure that the binary control signal output from the externally input binary code combined with the sigma-delta modulator effectively reflects the constraints of the control codes of the programmable P-counter and pulse-swallowing S-counter, the algorithm control module performs logical processing on the control word and adjusts the bit depth of the programmable P-counter and pulse-swallowing S-counter. Specifically:

[0019] In this embodiment, the programmable frequency divider module can theoretically be any one of three types: a programmable frequency divider based on phase switches, a programmable frequency divider based on pulse swallowing technology, or a multi-mode frequency divider based on 2 / 3 frequency dividers, without any special modifications. This does not increase the design difficulty of the circuit, which is also the advantage of this invention.

[0020] As shown in Figure 2, the programmable frequency divider module in this embodiment consists of a prescaler integrating M / M+1 and 2M / 2M+1 allocation functions, a programmable P counter, and a programmable pulse swallowing S counter. Here, P and S represent the number of bits in the counter, and their sum represents the number of bits n in the entire high-speed broadband programmable frequency divider, i.e., n = P + S. This frequency divider structure can achieve a division ratio of N = M × P + S, which can be greater than M. 2 The continuous division ratio is used, therefore the frequency divider implemented based on this structure is also called the MPS programmable frequency divider. This programmable frequency divider module is mainly based on D flip-flops. Currently, D flip-flops mainly include static flip-flops based on the CML structure, dynamic flip-flops based on the TSPC structure, and static flip-flops based on logic gates. CML can operate in a high frequency range, often above 10GHz, but requires high static power consumption; TSPC only requires a single-phase clock, operates in the frequency range of several hundred to several gigahertz, and may fail at frequencies below several hundred MHz, with relatively low power consumption. Traditional logic gate static flip-flops operate in the frequency range within several hundred megahertz, with the lowest static power consumption. For the purpose of optimizing and reducing power consumption, as shown in Figure 3, the P counter includes several D flip-flop units connected in sequence. The low-order D flip-flop units connected to the output of the prescaler are TSPC-based D flip-flop units, and the high-order D flip-flop units connected to the output of the prescaler are logic gate-based static D flip-flop units. The pulse swallowing S counters all use high-speed DFF units based on the TSPC structure. In this embodiment, the main function of the sigma-delta modulator is to generate random numbers from -3 to 4, which are added to the externally input Int[n:0] by an adder and then sent to the algorithm control module, which in turn inputs the programmable frequency divider module.

[0021] In this embodiment, the prescaler in the programmable frequency divider module operates over a wide frequency band. To enable the P-counter and pulse-swallowing S-counter to adapt to the wide operating frequency and reduce their design complexity, this embodiment integrates both M / M+1 and 2M / 2M+1 frequency division functions in the prescaler. This configuration ensures that the P-counter and pulse-swallowing S-counter process the same frequency over a frequency band twice as wide, significantly reducing the design difficulty and circuit complexity of the P-counter and S-counter. For example, in one embodiment, a wide frequency band of 500MHz to 8GHz needs to be processed. In the range of 500MHz to 4GHz, a 4 / 5 prescaler is used, and in the range of 4GHz to 8GHz, an 8 / 9 prescaler is used. Therefore, the maximum operating frequency of the programmable P-counter and pulse-swallowing S-counter is within 1GHz, reducing the design difficulty of the programmable P-counter and pulse-swallowing counter.

[0022] The above method effectively solves the narrowband operation problem of traditional frequency dividers and proposes optimization methods to reduce power consumption. However, it should be noted that for the MPS structure frequency divider, in order to ensure that the binary control word input from the external control word can be directly reflected in the changes of the P counter and the pulse swallowing S counter, the following relationships must be satisfied in M, P, and S: M is a power of 2, P≥M, P-1>S, and the number of bits of the S counter is log2M, with the most significant bit being log2M-1; the number of bits of the P counter is greater than or equal to log2M+1, with the least significant bit being log2M and the most significant bit being unrestricted. Since the prescaler integrates both 4 / 5 and 8 / 9 division functions, according to the above requirements, the pulse swallowing S counter needs to use different bit widths depending on the bandwidth of the prescaler's operation for 4 / 5 and 8 / 9 division. In this embodiment, the pulse swallowing S counter needs to operate at 2 bits or 3 bits. Traditional solutions often employ two sets of frequency dividers with different frequency ranges, switched via a switch. One set consists of a 4 / 5 prescaler and a 2-bit S-counter suitable for a 500MHz-4GHz bandwidth; the other set consists of an 8 / 9 prescaler and a 3-bit S-counter suitable for a 4GHz-8GHz bandwidth. This approach significantly increases circuit complexity, fabrication area, and design and manufacturing costs. To overcome this problem, this implementation proposes using only one complete frequency divider, combined with an algorithm control module to control the number of bits in the pulse-swallowing S-counter and process the logic operation output L[n-1:0] of the external inputs Int[n-1:0] and Frac[q-1:0] to meet the logic requirements of the MPS architecture frequency divider.

[0023] The algorithm control module in this embodiment includes: an input signal judgment unit, used to judge whether the frequency of the input signal exceeds a threshold; a first processing unit, used to control the prescaler to use a 2M / 2M+1 frequency division function when the frequency of the input signal exceeds the threshold, control the pulse swallowing S counter to operate with a first working bit number K, and send L[n-1:K] of the output L[n-1:0] of the adder as a first control word signal to the P counter, and send L[K-1:0] of the output L[n-1:0] of the adder as a second control word signal to the pulse swallowing S counter; a second processing unit, This is used to control the prescaler to use the M / M+1 frequency division function when the frequency of the input signal does not exceed the threshold, control the pulse swallowing S counter to operate with the second working bit R, the second working bit R being less than the first working bit K, and set the third bit of the pulse swallowing S counter to zero. The L[R-1:0] of the adder's output L[n-1:0] is sent to the pulse swallowing S counter as the first control word signal, the L[n-2:R] of the adder's output L[n-1:0] is sent to the P counter as the second control word signal, and the L[n-1] of the adder's output L[n-1:0] is discarded.

[0024] The workflow of the algorithm control module is shown in Figure 4. In the above embodiment: the programmable frequency divider module adopts the MPS programmable frequency divider shown in Figure 2. The prescaler is an integrated 4 / 5 and 8 / 9 division ratio prescaler. The P counter has 12 bits, denoted as P[11:0], and the pulse swallowing S counter has 3 bits, denoted as S[2:0]. Therefore, the total number of bits in the programmable frequency divider module is 15 bits, and the external input becomes 15 bits accordingly. When the input frequency range is 500MHz~4GHz, the prescaler adopts a 4 / 5 division ratio under the control of the algorithm control module, and the pulse swallowing S counter is set to 2 bits. As mentioned above, in order not to change other settings, the pulse swallowing S counter is controlled by the algorithm logic. The third bit is 0, that is, N[3] = 0. L[1:0] is assigned to N[1:0] and finally input to S[1:0]. L[n-2:2] is assigned to N[n-1:3] and finally input to the P counter. In this state, the L[n-1] bit overflows and is discarded. The frequency division ratio is calculated as N = 4 × L[n-2:2] + S[1:0]. If the output L[n-1:0] = 00000001111111 after the operation of the external input Int[n-1:0] and Frac[q-1:0], then L[n-2:2] = 11111, S[1:0] = 11. Then the frequency division ratio N = 4 × 31 + 3 = 127. If the input is 4 GHz, then the output is 31.5 MHz. When the input frequency range is 4GHz to 8GHz, the prescaler uses an 8 / 9 division ratio controlled by an algorithm. S is set to 3 bits, L[n-1:0] can be directly assigned to N[n-1:0], and L[n-1:3] is assigned to N[n-1:3] which is ultimately input to the P counter. L[2:0] is assigned to N[2:0] which is ultimately input to the S counter. At this time, the prescaler calculation formula is N = 8 × L[n-1:3] + S[2:0]. Similarly, if the external input Int[n-1:0] is... After processing Frac[q-1:0], the output L[N-1:0] = 00000001111111, then L[n-1:3] = 1111, S[2:0] = 111, so the division ratio N = 8 × 15 + 7 = 127. To ensure consistent final output frequency, we only need to set the eighth bit of L[n-1:0] to 1 and the first bit to 0, resulting in N = 8 × 31 + 6 = 254. If the input is 8GHz, the output will be 31.5MHz. The above demonstrates that by adding the algorithm control module, the complexity of the circuit design is greatly reduced without altering the difficulty of the external binary code. It is worth noting that this embodiment uses an integer division ratio for simplification, but in reality, this implementation simultaneously satisfies both integer and fractional division functions.

[0025] It is easy to see that this invention proposes a broadband multi-mode programmable frequency divider to meet the application requirements of wide bandwidth and multiple division ratios. Through algorithmic control optimization, it ensures effective control of the PS counter by the binary code changes of the integrated multi-mode programmable broadband frequency divider with multiple prescalers. It realizes a frequency divider that can perform both integer and fractional division, avoiding the need for two or more frequency dividers operating in different frequency ranges in traditional architectures. This reduces hardware manufacturing costs and circuit complexity, and optimizes power consumption. The configured programmable number of bits can achieve a wide range of division ratios, meeting the needs of most application scenarios and greatly enhancing the application flexibility and versatility of the frequency divider.

Claims

1. A broadband high-speed multi-mode programmable frequency divider, characterized in that, The system includes a programmable frequency divider module, a sigma-delta modulator module, an adder module, and an algorithm control module. The programmable frequency divider module includes a prescaler, a P-counter, and a pulse-swallowing S-counter. The prescaler integrates M / M+1 and 2M / 2M+1 frequency division functions. The sigma-delta modulator generates random numbers from -3 to 4. The adder adds the random numbers to an external digital input Int[n:0]. The algorithm control module controls the number of bits operated by the pulse-swallowing S-counter and processes the output L[n-1:0] of the adder to meet the logic requirements of the programmable frequency divider module. The algorithm control module includes: an input signal judgment unit, used to judge whether the frequency of the input signal exceeds a threshold; a first processing unit, used to control the prescaler to use a 2M / 2M+1 frequency division function when the frequency of the input signal exceeds the threshold, control the pulse swallowing S counter to operate with a first working bit number K, and send L[n-1:K] of the output L[n-1:0] of the adder as a first control word signal to the P counter, and send L[K-1:0] of the output L[n-1:0] of the adder as a second control word signal to the pulse swallowing S counter; a second processing unit, used to... When the frequency of the input signal does not exceed the threshold, the prescaler is controlled to use the M / M+1 frequency division function, the pulse swallowing S counter is controlled to operate with the second working bit R, the second working bit R is less than the first working bit K, and the third bit of the pulse swallowing S counter is set to zero. The L[R-1:0] of the adder's output L[n-1:0] is sent to the pulse swallowing S counter as the first control word signal, the L[n-2:R] of the adder's output L[n-1:0] is sent to the P counter as the second control word signal, and the L[n-1] of the adder's output L[n-1:0] is discarded.

2. The broadband high-speed multi-mode programmable frequency divider according to claim 1, characterized in that, The P counter includes several D flip-flop units connected in sequence. The low-order D flip-flop units connected to the output of the prescaler are D flip-flop units based on the TSPC structure, and the high-order D flip-flop units connected to the output of the prescaler are static D flip-flop units based on logic gates.

3. The broadband high-speed multi-mode programmable frequency divider according to claim 1, characterized in that, M is a power of 2, the number of bits in the P counter is greater than or equal to M, the number of bits in the P counter minus one is greater than the number of bits in the pulse swallowing S counter, and the number of bits in the pulse swallowing S counter is log2M, with the most significant bit being log2M-1; the number of bits in the P counter is greater than or equal to log2M+1, with the least significant bit being log2M.

4. The broadband high-speed multi-mode programmable frequency divider according to claim 1, characterized in that, After processing by the prescaler, if the input signal frequency has a twofold relationship, the output signal frequency of the prescaler will be the same.

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