An R-2R resistor network digital-to-analog converter circuit and its calibration method

Abstract

This invention belongs to the field of analog integrated circuits, specifically relating to an R-2R resistor network digital-to-analog converter circuit and its calibration method, including a main DAC circuit, an auxiliary DAC circuit, a successive approximation circuit, an operational amplifier circuit, a switch S1, and a capacitor C1; the output terminal of the main DAC circuit is connected to the positive terminal of capacitor C1, and the negative terminal of the capacitor is connected to the negative input terminal of the operational amplifier circuit and the switch S1 respectively; the other end of the switch S1 is connected to the output terminal of the operational amplifier circuit; the positive terminal of the operational amplifier circuit is connected to the common-mode level, and the output terminal is connected to the input terminal of the successive approximation circuit; the output terminal of the successive approximation circuit is connected to the input terminal of the auxiliary DAC circuit; the output terminal of the auxiliary DAC circuit is connected to the main DAC circuit, forming a loop; this invention uses an auxiliary DAC to calibrate the circuit in the high-temperature thermometer branch, thereby reducing the chip size and facilitating circuit integration.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuits, and specifically relates to an R-2R resistor network digital-to-analog converter circuit and its calibration method. Background Technology

[0002] Digital-to-analog converters (DACs) are widely used in communications, sensors, and testing instruments. High speed and high precision are the main specifications for DACs. To achieve high precision, large-size components are often used to reduce the impact of component mismatch during the manufacturing process. However, large-size components sacrifice layout area and reduce the speed of the DAC. Furthermore, as the resolution of the DAC increases, the impact of component mismatch on precision becomes greater. To achieve high precision requirements, calibration techniques are used to reduce component mismatch and enable the DAC to meet these requirements.

[0003] Patent application CN202220314235.8, entitled "A Decoding Power Amplifier Circuit Using a Discrete R-2R Digital-to-Analog Converter Circuit," discloses a decoding power amplifier circuit. This circuit includes: a power supply system, an MCU control system, a digital audio processor, an oversampling interpolation digital filter, a discrete R-2R digital-to-analog converter circuit, a low-pass filter and buffer amplifier, an analog volume control module, a signal conversion circuit, and a signal selection circuit. The discrete R-2R digital-to-analog converter circuit converts the serial data output from the oversampling interpolation digital filter into parallel data and outputs an analog audio signal to the low-pass filter and buffer amplifier. The low-pass filter and buffer amplifier is connected to the analog volume control module. The output of the analog volume control module is connected to the output of the signal conversion circuit and outputs a headphone drive signal through a headphone amplifier circuit. This circuit can realize a discrete R-2R structure DAC circuit and apply it to a decoding amplifier circuit, overcoming the difficulty of limited supply of modern new DAC chips.

[0004] However, for resistive digital-to-analog converters, the higher the resolution, the higher the requirements for resistor matching accuracy and the higher the requirements for the process. Due to the limitations of current processes, some high-resolution digital-to-analog converters often require calibration techniques to achieve high accuracy, which makes the manufacturing of the device more complex and its accuracy lower. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes an R-2R resistor network digital-to-analog converter circuit. The circuit structure includes: a main DAC circuit, an auxiliary DAC circuit, a successive approximation circuit, an operational amplifier circuit, a switch S1, and a capacitor C1. The output terminal of the main DAC circuit is connected to the positive terminal of capacitor C1, and the negative terminal of the capacitor is connected to both the negative input terminal of the operational amplifier circuit and the switch S1. The other end of switch S1 is connected to the output terminal of the operational amplifier circuit. The positive terminal of the operational amplifier circuit is connected to a common-mode voltage, and its output terminal is connected to the input terminal of the successive approximation circuit. The output terminal of the successive approximation circuit is connected to the input terminal of the auxiliary DAC circuit. The output terminal of the auxiliary DAC circuit is connected to the main DAC circuit, forming a loop.

[0006] Preferably, the successive approximation circuit includes: one shift register, eight D flip-flops, and an NOT gate; the outputs of the D flip-flops are connected to one input of an AND gate, the other end of the AND gate is connected to a clock signal, the output of the AND gate is connected to the clock port of the eight-shift register, the outputs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 of the shift register are respectively connected to the set inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, FF1, and FF0, the output of the operational amplifier is connected to the inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, and FF1, the output of FF0 is connected to the clock port clk of FF1, the output of FF1 is connected to the clock port clk of FF2, the output of FF2 is connected to the clock port clk of FF3, the output of FF3 is connected to the clock port clk of FF4, the output of FF4 is connected to the clock port clk of FF5, the output of FF5 is connected to the clock port clk of FF6, and the output of FF6 is connected to the clock port clk of FF7.

[0007] A calibration method for an R-2R resistor network digital-to-analog converter (DAC), the method comprising: calibrating the DAC and the successive approximation circuit separately; wherein, the calibration process for the DAC includes:

[0008] When switch S1 is turned on, the lower 6 bits of the input configuration binary DAC are all 1, D_CAL = 1, the higher 8 bits of the thermometer DAC are all 0, and the lower 6 bits of the main DAC output the effective output voltage V. out1 Due to the negative feedback loop, the input voltage of the amplifier is V. cm The voltage difference across capacitor C1 is V. out1 -V cm ;

[0009] With switch S1 open, the lower 6 bits of the binary DAC are all 0, D_CAL = 0. The higher-order thermometer DAC has a signal of 1 on one branch (i), while the rest are all 0. At this time, the amplifier's negative feedback loop is broken, and the voltage difference across C1 will remain constant. The output voltage on the thermometer sub-DAC i branch of the digital-to-analog converter is V. out2 Then the input voltage at the inverting input terminal of the amplifier becomes V. cm +V out2 -V out1 The voltage difference between the positive and negative terminals of the amplifier is V. out2 -V out1 When V out2 -V out1 If the value is greater than 0, the amplifier outputs logic 0. After obtaining the comparison result, the operational amplifier transmits it to the successive approximation circuit to calibrate the output when the i-branch of the high-level thermometer is effective.

[0010] Preferably, the calibration process of the successive approximation circuit includes: when switch S1 is open, the start pulse transmits the clock signal to the clock interface cp terminal of the shift register through the flip-flop and AND gate, and the shift register starts shifting; at this time, D flip-flop FF7 is set to bit 0, Q output is high level, and the reset signals of D flip-flops FF0, FF1, FF2, FF3, FF4, FF5, and FF6 change from 0 to 1 when the pulse arrives, and the reset signal is invalid; at this time, the auxiliary DAC auxiliary codeword changes from 00000 to 10000, and the auxiliary DAC output voltage is V. ref When the positive clock pulse arrives, the shift register shifts to the left. At this time, FF6 is set and Q4 changes from 0 to 1, which serves as the clock pulse for FF7. The result of the comparison by the high-gain op-amp is input into register FF5, and output by D7, to obtain the highest bit codeword of the auxiliary DAC. The changed auxiliary codeword is input into the auxiliary DAC, and the op-amp compares to obtain the logic codeword of the next bit. At the next clock pulse, the output of FF5 changes from 0 to 1, which serves as the clock pulse for FF6. The result of the op-amp comparison is input into register FF6, and output by D6, to obtain the second highest bit codeword of the auxiliary DAC. Similarly, when all the codewords of the 7-bit auxiliary DAC are obtained, Q8 is 0. At this time, the D flip-flop connected to the start signal is reset to 0, and the shift register clock signal is 0. Repeat the above steps to traverse all branches of the high-gain thermometer DAC and obtain all the codewords of the auxiliary DAC. The calibration is then complete.

[0011] The beneficial effects of this invention are:

[0012] This invention uses an auxiliary DAC to calibrate the circuit in the high-level thermometer branch, thereby reducing the size of the chip and facilitating circuit integration. This invention sets up a main DAC circuit and an auxiliary DAC circuit, wherein the main DAC circuit is composed of an 8-bit thermometer DAC and a binary DAC connected in series. In this circuit, the high-level signal is calibrated by the low-level signal, thereby improving the calibration accuracy of the device. Attached Figure Description

[0013] Figure 1 This is the overall structure of the segmented digital-to-analog converter of the present invention;

[0014] Figure 2 The Thevenin equivalent circuit diagram of the auxiliary DAC in the circuit of this invention;

[0015] Figure 3 This is a block diagram of the overall structure of the present invention;

[0016] Figure 4 This is a detailed circuit connection diagram of the successive approximation circuit of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] An R-2R resistor network digital-to-analog converter circuit, such as Figure 3 As shown, the circuit structure includes: a main DAC circuit, an auxiliary DAC circuit, a successive approximation circuit, an operational amplifier circuit, a switch S1, and a capacitor C1. The output terminal of the main DAC circuit is connected to the positive terminal of capacitor C1, and the negative terminal of the capacitor is connected to the negative input terminal of the operational amplifier circuit and the switch S1, respectively. The other end of the switch S1 is connected to the output terminal of the operational amplifier circuit. The positive terminal of the operational amplifier circuit is connected to the common-mode level, and its output terminal is connected to the input terminal of the successive approximation circuit. The output terminal of the successive approximation circuit is connected to the input terminal of the auxiliary DAC circuit. The output terminal of the auxiliary DAC circuit is connected to the main DAC circuit, forming a loop.

[0019] In this embodiment, the main DAC circuit includes an 8-bit thermometer DAC and a binary DAC; the 8-bit thermometer DAC and the binary DAC are connected in series; the 8-bit thermometer DAC consists of 2... 8The binary DAC consists of N branches connected in parallel, each branch consisting of a resistor and a switch connected in series, and the resistor values ​​in each branch are the same; the binary DAC consists of N branches and N-2 resistors with a resistance of R; the first branch includes a switch and a resistor with a resistance of 2R connected in series; the circuit structure of all branches is the same as that of the first branch; the second branch is connected in parallel with the first branch, and the second branch is connected in series with a resistor with a resistance of R and then connected in parallel with the third branch; the connection relationship of the branches is the same as that of the second and third branches.

[0020] For the main DAC circuit, such as Figure 1 As shown, the circuit adopts a 6+8 segment structure, and the binary DAC adopts an R-2R structure, including two different types of resistors with resistance values ​​of R and 2R respectively, D_CAL, D <0> D <1> D <2> D <3> D <4> D <5> The lower 6 bits of the thermometer DAC are used to control the switch input. A resistor with resistance R is connected to a 7-bit auxiliary DAC. Each branch of the higher 8 bits of the thermometer DAC is connected to a resistor with resistance R and a 7-bit auxiliary DAC. The input signal terminal of the auxiliary DAC is connected to the output of the successive approximation circuit.

[0021] Preferably, the auxiliary DAC circuit is a 7-bit binary DAC structure, that is, the number of branches in the binary DAC is 7.

[0022] Successive approximation circuit connection as follows Figure 4 As shown, the start pulse is connected to the clock interface of the D flip-flop, the start pulse is connected to the input of the NAND gate, and the output of the NAND gate is connected to the outputs of FF7, FF6, FF5, FF4, FF3, FF2, and FF1. The output of the D flip-flop is connected to one input of an AND gate, and the other end of the AND gate is connected to a clock signal. The output of the AND gate is connected to the clock port of an 8-bit shift register. The outputs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 of the shift register are connected to the set inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, FF1, and FF0, respectively. The output of the operational amplifier is connected to the inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, and FF1. The output of FF0 is connected to the clock port clk of FF1; the output of FF1 is connected to the clock port clk of FF2; the output of FF2 is connected to the clock port clk of FF3; the output of FF3 is connected to the clock port clk of FF4; the output of FF4 is connected to the clock port clk of FF5; the output of FF5 is connected to the clock port clk of FF6; and the output of FF6 is connected to the clock port clk of FF7. All other interfaces are left floating.

[0023] like Figure 4As shown, the successive approximation circuit includes: one shift register, eight D flip-flops, and an NOT gate; the outputs of the D flip-flops are connected to one input of an AND gate, the other end of the AND gate is connected to a clock signal, the output of the AND gate is connected to the clock port of the eight-shift register, and the outputs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 of the shift register are connected to the set inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, FF1, and FF0, respectively. The output of the operational amplifier is connected to the inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, and FF1; the output of FF0 is connected to the clock port clk of FF1; the output of FF1 is connected to the clock port clk of FF2; the output of FF2 is connected to the clock port clk of FF3; the output of FF3 is connected to the clock port clk of FF4; the output of FF4 is connected to the clock port clk of FF5; the output of FF5 is connected to the clock port clk of FF6; and the output of FF6 is connected to the clock port clk of FF7.

[0024] A calibration method for an R-2R resistor network digital-to-analog converter includes calibrating the digital-to-analog converter and the successive approximation circuit separately. The calibration principle is as follows: for an N-bit R-2R voltage-type DAC... The resistance looking to the left from node k is equivalent to 2R, and the ideal output of the reference voltage controlled by node k should be reduced to 1 / 2. k However, due to resistor mismatch, the actual contribution of k bits to the output voltage is: Where R par (k) is the value of the parallel combination of the resistance at node k viewed from the left and the resistance viewed from the right, R a (k) is the value of the bridge resistor on branch k at node k. Resistor mismatch causes the output voltage to be non-ideal V when k is active. ref / 2 k As the DAC bit depth increases, resistor mismatch has a greater impact on DAC accuracy. To improve the accuracy of the high-bit temperature counter-to-analog converter (DAC) and calibrate the linearity of the high-bit branch, the bridge resistor 2R in the high-bit branch is replaced with a resistor of value R and an R-2R voltage-type auxiliary DAC. The output impedance of the auxiliary DAC does not change with the codeword of the auxiliary DAC signal. Therefore, the auxiliary DAC in the high-bit temperature counter branch is equivalent to a variable voltage and a resistor R in series, such as... Figure 2 As shown, each branch of the high-voltage thermometer is equivalent to a variable voltage source connected in series with a resistor R. Therefore, V out (k)=VC k (DC k )Q k The calibration step estimates the auxiliary DAC auxiliary codeword DC. kThis allows the auxiliary DAC to contribute a voltage to the output, as close as possible to the ideal value. A 7-bit auxiliary DAC is used, with a reference voltage of 2V. ref The output range of the auxiliary DAC is 0-2V. ref The minimum precision is 2V. ref / 2 7 Ideally, the voltage of each branch of the high-8-bit thermometer should be reduced to half the output voltage. 8 For a 14-bit DAC with a 6+8 segmented structure, the auxiliary DAC can adjust the main DAC by a minimum of approximately 1 LSB and a maximum of 64 LSB.

[0025] During circuit calibration, switch S1 is turned on, configuring the lower 6 bits of the binary DAC input to be all 1, D_CAL = 1, and the higher 8 bits of the thermometer DAC input to be all 0. At this time, the main DAC outputs the lower 6 bits of the effective output voltage V. out1 Due to the negative feedback loop, the input voltage of the amplifier is V. cm The voltage difference across capacitor C1 is V. out1 -V cm Subsequently, switch S1 is opened, configuring the lower 6 bits of the binary DAC to be all 0, D_CAL = 0, and the higher bits of the thermometer DAC to be all 0 except for one branch i, where the signal is 1. Since switch S1 is open, the amplifier's negative feedback loop is broken, so the voltage difference across C1 will remain constant. At this time, the digital-to-analog converter outputs the voltage V on the i-branch of the thermometer sub-DAC. out2 Then the input voltage at the inverting input terminal of the amplifier becomes V. cm +V out2 -V out1 The voltage difference between the positive and negative terminals of the amplifier is V. out2 -V out1 When V out2 -V out1 If the value is greater than 0, the amplifier outputs logic 0. After obtaining the comparison result, the operational amplifier transmits it to the successive approximation circuit to calibrate the output when the high-level thermometer i branch is active.

[0026] When switch S1 is open, the start pulse in the successive approximation circuit transmits the clock signal to the clock interface cp terminal of the shift register through the flip-flop and AND gate, and the shift register begins to shift. At this time, D flip-flop FF7 is set to bit 0, Q output is high, and the reset signals of D flip-flops FF0, FF1, FF2, FF3, FF4, FF5, and FF6 change from 0 to 1 when the pulse arrives, rendering the reset signal ineffective. At this time, the auxiliary DAC auxiliary codeword changes from 00000 to 10000, and the auxiliary DAC output voltage is V. refWhen the positive clock pulse arrives, the shift register shifts to the left. At this time, FF6 is set, and Q4 changes from 0 to 1, which serves as the clock transition for FF7. This transition inputs the result of the comparison by the high-gain op-amp into register FF5, outputting D7 to obtain the most significant bit of the auxiliary DAC's codeword. The modified auxiliary codeword is input into the auxiliary DAC, where the op-amp compares the results to obtain the next logical codeword. On the next clock pulse, the output of FF5 changes from 0 to 1, serving as the clock input for FF6. This transition inputs the result of the op-amp comparison into register FF6, outputting D6 to obtain the second most significant bit of the auxiliary DAC's codeword. Similarly, when all 7 bits of the auxiliary DAC's codeword are obtained, Q8 becomes 0. At this point, the D flip-flop connected to the start signal is reset to 0, and the shift register clock signal becomes 0. The calibration of the i-th bit is complete.

[0027] Repeat the above process to traverse all branches of the high-level thermometer DAC, obtain all codewords of the auxiliary DAC, and the calibration is complete.

[0028] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An R-2R resistor network digital-to-analog converter circuit, characterized in that, include: The circuit consists of a main DAC circuit, an auxiliary DAC circuit, a successive approximation circuit, an operational amplifier circuit, a switch S1, and a capacitor C1. The output of the main DAC circuit is connected to the positive terminal of capacitor C1, and the negative terminal of the capacitor is connected to both the negative input terminal of the operational amplifier circuit and the switch S1. The other end of switch S1 is connected to the output terminal of the operational amplifier circuit. The positive terminal of the operational amplifier circuit is connected to the common-mode level, and its output terminal is connected to the input terminal of the successive approximation circuit. The output terminal of the successive approximation circuit is connected to the input terminal of the auxiliary DAC circuit. The output terminal of the auxiliary DAC circuit is connected to the main DAC circuit, forming a loop. The main DAC circuit includes an 8-bit thermometer DAC and a binary DAC; the 8-bit thermometer DAC and the binary DAC are connected in series; the 8-bit thermometer DAC consists of 2... 8 The binary DAC consists of N branches connected in parallel, each branch consisting of a resistor and a switch connected in series, and the resistor values ​​in each branch are the same; the binary DAC consists of N branches and N-2 resistors with a resistance of R; the first branch includes a switch and a resistor with a resistance of 2R connected in series; the circuit structure of all branches is the same as that of the first branch; the second branch is connected in parallel with the first branch, and the second branch is connected in series with a resistor with a resistance of R and then connected in parallel with the third branch; the connection relationship of the branches is the same as that of the second and third branches.

2. The R-2R resistor network digital-to-analog converter circuit according to claim 1, characterized in that, The auxiliary DAC circuit is a 7-bit binary DAC structure.

3. The R-2R resistor network digital-to-analog converter circuit according to claim 1, characterized in that, The successive approximation circuit includes: one shift register, eight D flip-flops, and an NOT gate; the output of another D flip-flop (excluding the eight D flip-flops) is connected to one input of an AND gate, the other end of which is connected to a clock signal. The output of the AND gate is connected to the clock port of the eight-shift register. The outputs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 of the shift register are connected to the set inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, FF1, and FF0, respectively. The output of the operational amplifier is connected to the inputs of D flip-flops FF7, FF6, FF5, FF4, FF3, FF2, and FF1. The output of FF0 is connected to the clock port clk of FF1; the output of FF1 is connected to the clock port clk of FF2; the output of FF2 is connected to the clock port clk of FF3; the output of FF3 is connected to the clock port clk of FF4; the output of FF4 is connected to the clock port clk of FF5; the output of FF5 is connected to the clock port clk of FF6; and the output of FF6 is connected to the clock port clk of FF7.

4. A calibration method for an R-2R resistor network digital-to-analog converter, the method being used to calibrate an R-2R resistor network digital-to-analog converter circuit according to any one of claims 1 to 3, characterized in that, include: The digital-to-analog converter and the successive approximation circuit are calibrated separately; the calibration process for the digital-to-analog converter includes: When switch S1 is turned on, the lower 6 bits of the input configuration binary DAC are all 1, D_CAL = 1, the higher 8 bits of the thermometer DAC are all 0, and the lower 6 bits of the main DAC output the effective output voltage V. out1 Due to the negative feedback loop, the input voltage of the operational amplifier circuit is V. cm The voltage difference across capacitor C1 is V. out1 -V cm ; With switch S1 open, the lower 6 bits of the binary DAC are all 0, D_CAL = 0. The higher-order thermometer DAC has a signal of 1 on one branch (i), while the rest are all 0. At this time, the negative feedback loop of the op-amp circuit is broken, and the voltage difference across capacitor C1 will remain constant. The output voltage on the thermometer sub-DAC i branch of the digital-to-analog converter is V. out2 Then the input voltage at the inverting input terminal of the operational amplifier circuit becomes V. cm +V out2 -V out1 The voltage difference between the positive and negative terminals of the operational amplifier circuit is V. out2 -V out1 When V out2 -V out1 If the value is greater than 0, the operational amplifier circuit outputs logic 0. After obtaining the comparison result, the operational amplifier circuit transmits it to the successive approximation circuit to calibrate the output when the high-level thermometer i branch is effective.

5. The calibration method for an R-2R resistor network digital-to-analog converter according to claim 4, characterized in that, The calibration process for the successive approximation circuit includes: With switch S1 open, the start pulse transmits the clock signal to the clock interface cp of the shift register via a flip-flop and an AND gate, and the shift register begins shifting; at this time, D flip-flop FF7 is set to 0, Q output is high, and the reset signals for D flip-flops FF0, FF1, FF2, FF3, FF4, FF5, and FF6 change from 0 to 1 upon pulse arrival, rendering the reset signals invalid; at this time, the auxiliary DAC's auxiliary codeword changes from 00000 to 10000, and the auxiliary DAC output voltage is V. ref When the positive clock pulse arrives, the shift register shifts to the left. At this time, FF6 is set and Q4 changes from 0 to 1, which serves as the clock pulse for FF7. The comparison result of the op-amp circuit is input to the output of D flip-flop FF5, obtaining the highest bit codeword of the auxiliary DAC. The changed auxiliary codeword is input into the auxiliary DAC, and the op-amp compares to obtain the logic codeword of the next bit. At the next clock pulse, the output of FF5 changes from 0 to 1, serving as the clock pulse for FF6. The comparison result of the op-amp is input to the output of D flip-flop FF6, obtaining the second highest bit codeword of the auxiliary DAC. Similarly, when all the codewords of the 7-bit auxiliary DAC are obtained, Q8 is 0. At this time, the D flip-flop connected to the start signal is reset to 0, and the shift register clock signal is 0. Repeat the above steps to traverse all branches of the high-order thermometer DAC and obtain all the codewords of the auxiliary DAC. The calibration is then complete.

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